KR100710972B1 - Mixed Verification Apparatus for Mixed Emulation/Simulation and Mixed Verification Method Using the Same - Google Patents

Abstract

The present invention relates to a mixed verification method of emulation and simulation and a mixed verification apparatus for the design verification of a designed digital circuit, which can be performed quickly and accurately by using an arbitrary prototyping board and an arbitrary simulator.

In the present invention, the server computer is designed to generate a programming pattern for a probe additional circuit that enables the implementation of the digital circuit to be verified and the input / output probe, and the programming pattern is downloaded to each RFPD on an arbitrary prototyping board. The circuit to be verified is implemented on an arbitrary prototyping board, and the added memory device input / output probe and the memory read / write additional circuit are used for the input / output probe and memory for all or a part of the memory elements in the user circuit. By performing read / write through the mixed verification device, emulation and simulation can be performed automatically one or more times to verify user circuits.

Description

Mixed Verification Apparatus for Mixed Emulation / Simulation and Mixed Verification Method Using the Same}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows an emulation and simulation mixing verification apparatus of the present invention.

Fig. 2 is a diagram schematically showing an example in which the implementation of the memory probe supplementary circuit is implemented as a finite state machine for the memory probe;

Fig. 3 is a diagram showing an asynchronous circuit example, showing a 4-bit asynchronous binary counter.

4 (a) and (b) schematically show symbols and functional functions of a single input D flip-flop having one data input D;

4 (c) and (d) schematically show symbols and functional functions of a single input D-type flip-flop having one data input (D) and an asynchronous set / reset (AR / AS) input.

4 (e) and (f) schematically show the symbol and functional function of a dual input D flip-flop having two data inputs D1 and D2;

4 (g) and (h) schematically show symbols and functional functions of a dual input D-type flip-flop having two data inputs D1 and D2 and a validated (EN) input.                 

Fig. 5 is a diagram schematically showing an example of a shift register array structure in which a parallel load and a serial load showing an IOP probe additional circuit according to the present invention are possible in accordance with an input / output mode.

FIG. 6 is a schematic illustration of another example of a shift register array structure in which the parallel and serial loads of FIG.

FIG. 7 is a schematic illustration of an implementation example of the dual input D-type flip-flop of FIG. 4 (a); FIG.

Fig. 8A is a diagram schematically showing a situation in which an additional circuit for IOP-probe is added to the design verification subject circuit in Fig. 3;

FIG. 8B is a diagram schematically showing the control circuit used in the situation where the IOP-probe supplementary circuit is added to the design verification subject circuit of FIG. 3 and defined by a truth table; FIG.

Fig. 9 (a) is a schematic diagram showing a situation in which any flip-flop of a design verification target circuit has an asynchronous set and an asynchronous reset.

Fig. 9B is a schematic diagram showing a situation in which the flip-flop of Fig. 9A is converted in the extended design verification target circuit.

Figure 9 (c) is a diagram defining the truth table of the control circuit used in Figure 9 (b).

Fig. 10 illustrates the configuration of a latch with a flip-flop and a multiplexer in a circuit functionally equivalent to the latch.

FIG. 11 is a flowchart illustrating a design verification method according to an embodiment of a mixed verification of emulation and simulation using FIG. 1. FIG.                 

12 is a flowchart for explaining a design verification method according to another embodiment of mixed verification of emulation and simulation using FIG. 1;

<Description of the symbols for the main parts of the drawings>

12: RFPD 20: Computer for Server

26: relay cable 30: relay module

32: mixed verification system means (or modules)
34: random simulator

44: random prototyping board 74: multiplexer

75: dual input D flip flop 76: single input D flip flop

77: dual input flip-flop with asynchronous set and asynchronous reset

78: Single Input Flip-Flop with Asynchronous Set and Asynchronous Reset

79: Tri-state buffer

80: latch

81: read / write control signal to memory

82: address signal

83: memory input multiplexer 1 84: selection input signal

85: memory clock signal 86: memory output terminal

87 flip-flops at the memory output

88: shift register of data input terminal

89: memory input multiplexer 2 90: finite state machine for memory probe

The present invention relates to a design verification technique for verifying a designed digital circuit, and in particular, in the process of rapidly prototyping a designed digital circuit into programmable elements (or chips) to implement the same form as real hardware and verifying based on emulation. Automatically switch during emulation to verify successive verifications on a simulation-based basis as a simulator running on a computer or upside down on a simulation-based verification as a simulator running on a computer and subsequently verify successive verifications on an emulation basis. The present invention relates to an emulation and simulation mixed verification method that can repeatedly verify the same emulation and simulation one or more times, and a hybrid verification device for the same.

Recently, with the rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuit design is increasing and its configuration is becoming complicated. In addition, competition in the market is getting fiercer, so it is necessary to develop excellent products in a short time. Therefore, there is an increasing need for an effective verification method to efficiently verify a designed circuit in a short time.

Until now, software simulators have been mainly used to verify the designed digital circuits. The simulation-based verification method using the simulator can use various delay models for the circuit, which enables not only functional verification but also timing verification, and all the data in the circuit during the debugging process. Although it has the advantage of providing complete visibility of signal lines, etc., the simulator sequentially executes software composed of sequential instruction sequences on a computer (so, in this patent, a design object modeled by software on a computer is applied to the simulator). The entire process performed on a computer is defined as simulation), which takes a very long time to verify and integrates with other surrounding hardware environments to verify the entire system (this is called ICE, In-Circuit Emulation). . Moreover, simulation verification has not been able to keep up with the complexity of millions or tens of millions of gate-class digital circuits, where the performance of computers that rely on simulation software and single processors is rapidly increasing. It requires longer verification times. On the other hand, the hardware emulation-based design verification method is designed to verify digital circuits by operating the implemented hardware in parallel, enabling design verification up to one million times faster than simulation and other peripheral hardware environments. Transient ICE environments can be configured and integratedly verified. Emulation, however, has the disadvantage that debugging is much more inconvenient than simulation. The main reason for this is the visibility of the logic value of signal lines existing inside a circuit implemented in programmable devices (or chips). This is because it falls far short of the simulation.

Reusable Field Programmable Devices (hereinafter referred to as "RFPDs"), which are programmable devices (or chips), are the key devices for emulation-based design verification. These RFPDs are field programmable gate arrays (FPGAs). Field Programmable Gate Array (CPLD) and Complex Programmable Logic Devices (CPLDs) are available. Recent advances in semiconductor technology have resulted in a high degree of integration of RFPDs, resulting in highly complex digital circuits. It is now possible to prototype using only RFPD. This makes prototyping economical, but when prototyping, most of the many signal lines on the digital circuit that are subject to design verification exist inside the RFPD, making the probes more difficult to debug. This results in a very serious problem with less visibility. This will become a bigger problem in the future when more integrated RFPD is used.

Therefore, in order to verify the design of digital circuits, it is best to maximize the effectiveness of the verification by alternately using the emulation method and the simulation method in the design verification process. In other words, the design verification is based on emulation, and at a specific point or situation where very detailed verification is required, high-speed functional verification is performed, and at this point, the verification method is automatically converted from emulation to simulation based on the circuit to be verified. Performing functional or timing verification with 100% complete visibility and, if necessary, verifying by performing one or more such transitions between emulation and simulation is verified to maximize the effectiveness of the verification.

However, if the designer wants to verify the design of the digital circuit designed by the designer in an emulation-based environment using a prototyping board arbitrarily implemented using RFPDs, which are programmable devices (or chips), the emulation-based verification There is no method and a mixed verification device that can be mixedly verified by using the above-described emulation and simulation, which solve the disadvantages of the method by using a simulation-based verification method.

In particular, when the simulation is to be performed and then the emulation is to be performed, the emulation of the memory elements (flip-flop or latch) and the logic values of the memories (RAM or ROM) of the design verification target circuit obtained by the simulation is performed. It is imperative that the memory elements and memories present in the circuit implemented in the RFPD to be performed have prior to the start of emulation. However, in recent circuit designs, the asynchronous situation in which a gated clock or a locally generated clock signal is applied to a clock input of a memory device present in a design verification circuit is very frequent. In this situation, there is no method to freely change the logic values of the memory elements in the circuit implemented in the RFPD to specific logic values obtained as a result of the simulation.

Accordingly, an object of the present invention is to provide a method for verifying by effectively using a combination of emulation and simulation for a circuit implemented on a prototyping board arbitrarily manufactured by a programmable chip for effective design verification of a digital circuit. To provide a mixed verification device for.                         

In order to achieve the above object, the emulation and simulation mixed verification apparatus according to the present invention provides an interface module, an interface cable, and a mixed verification system means (or module). The mixed verification system means (or module) is run on a server computer, which is connected via a computer network with another computer having any simulator or having any simulator. The relay module and the relay cable connect the computer for the server with the mixed verification system means (or modules) and any boards equipped with one or more RFPDs in which the designed digital circuitry is implemented (hereafter referred to as any prototyping board). Another important function of the relay module is a mixed probe system means (or module) that includes a probe clock, an operation mode control signal, a probe mode control signal, a probe memory read / write signal, and the like, which are required for the mixed verification of the emulation and the simulation. Control the operation of any prototyping board by generating it under the control of a) and feeding it to any prototyping board as needed. 1 is a diagram schematically showing an emulation and simulation mixed verification apparatus according to the present invention composed of a mixed verification system means (or module) operating in a server computer, a connection cable and a connection module. As a specific example, the relay module may be mounted in a PCI slot to be connected to a Peripheral Computer Interface (PCI) bus of a servo computer, and may be connected to an emulation board through a relay cable from the relay module.

Mixed verification system means (or modules) provide complete state information of the design verification target circuit implemented on any prototyping board to enable automatic switching of simulation and emulation at any point or situation desired by the user during the design verification process. (State Information) or partial state information can be read from the prototyping board at any point in time, or vice versa, or written as a specific state information value. Here, the state information refers to the values of the memory elements (flip-flop or latch) of the digital circuit and the contents of the memory (RAM or ROM). The complete state information means the values of all the memory elements of the circuit for design verification. Partial state information refers to the value of the memory elements of the part of the circuit to be verified and / or the content of the part of the memory. In addition, the memory device and the memory are different, and the memory device means flip-flop or latch, and the memory means random access memory (RAM) or read only memory (ROM).

In order to perform mixed verification in an automated manner between emulation and simulation, performance switching between emulation and simulation is automatically performed. This is called execution mode switching. Such performance mode switching is performed when certain conditions are satisfied. For example, when a specific value is written twice to a specific register in a circuit), such a condition is called a execution mode switching condition. The execution mode switching condition may be two or more times temporally related to the entire verification process. In such a case, the emulation mode is performed when the condition is satisfied in the order of the condition set first in the order from the first set in the later. Execution mode switching from simulation or simulation to logic emulation occurs. To do this, it is necessary to store the execution mode switching conditions in a queue, which is called the execution mode switching condition queue, and keeps it in the form of a data structure inside the mixed verification system means (or module).

First, the mixed verification method in the present invention will be described on the assumption that no memory exists in the design verification target circuit, and the case where the memory exists will be described later. The mixed verification system means (or module) includes an input / output probe circuit synthesizer for converting a design verification target circuit into an input / output probe in order to enable the automatic switching of simulation and emulation as described above. The circuit synthesizer adds an IOP-probe add-on circuit (described below) to the design verification circuit to generate a completed circuit (called the extended design verification circuit). The role of the additional circuit for IOP probe included in the extended design verification target circuit is that in the output probe mode, the circuit part formed by adding the additional circuit becomes the shift register structure, so that the shifting operation synchronized with the probe clock is performed immediately before the shifting operation. The logic values of the shift register have the logic values of all or a part of the memory elements in the circuit to be output probe.In the input probe mode, the circuit part formed by adding an additional circuit has a shift register structure to perform the shifting operation. This shifting operation is used for synchronous set or reset operations, or asynchronous set or reset operations, for all or part of the memory elements in the circuit being the input probe. This can be followed by a synchronous set or reset or asynchronous set or reset operation. The synchronous disable operation makes the logic values of the memory elements to be input probes the input probe values, and in the normal mode, the functional logical behavior of the circuit to be verified for design is reduced even though the additional circuit is added. It is to create a circuit that does not deform. Or when the design verification object is dictated by a hardware oral language (hereinafter referred to as HDL) code, the HDL additional code representing the behavior of the IOP-probe supplementary circuit is added to the HDL code to be verified by design. In the output probe mode, the HDL portion formed by adding the additional HDL code expresses the shift register behavior, so that the shifting operation synchronized with the probe clock is the register HDL code in the HDL code expressing the shift register behavior immediately before the shifting operation. The signal values of the signal line have the output signal values of all or a part of the memory element to be output probe.In the input probe mode, the HDL code part formed by adding additional HDL code has a shift register structure to the probe clock. Synchronous shifting operation is performed. Asynchronous set or reset operations, or asynchronous set or reset operations, on signals in the HDL code that represent the memory element behavior of the HDL code being probed. It is a synchronous disable operation following a miracle set or reset or asynchronous set or reset operation so that the logic value of the signals that are the input probe target is the input probe value.In the normal mode, an additional circuit for IOP probe is added. Even if the HDL code does not change the behavior of the design verification HDL code, it is also called an IOP-probe supplementary circuit.

/탐침모드) 신호선들을 이용하여 입력탐침 대상이 되는 메모리소자의 비동기 셋과 비동기 리셋을 의도대로 제어할 수 있어야 하는데, 이는 간단한 조합적 함수를 이용하여 정의하고 구현할 수 있다. 이 메모리소자 탐침용 유한상태기의 함수적 행위(functional behavior) 및 역할은 추후 예제를 가지고서 구체적으로 설명하기로 한다. 또한 설계검증 대상회로에서 사용한 메모리소자들의 일부 혹은 전부가 비동기적 셋과 비동기적 리셋을 이미 가지고 있으며 이들 메모리소자들의 클럭 입력에 시스템 클럭이 직접 연결되어 있지 않는 경우에는 입력탐침 대상이 되는 해당 메모리소자들을 그대로 사용하면서 비동기 셋과 비동기 리셋 입력들을 구동(drive)하는 제어회로부를 포함하여 추가되는 IOP-탐침용 부가회로로써 상기 이미 언급한대로 회로 변환을 시도하면서 원래의 설계검증 대상회로의 함수적 논리성질을 정상모드에서 변형하지 않도록만 될 수 있도록 고려하면 되는데 이는 어려운 일이 아니며, 이 또한 추후 예제를 가지고서 구체적으로 설명하기로 한다.An example of one method of implementing the function of the IOP probe additional circuit is that the IOP probe additional circuit flips the signal lines and the double input flip of the memory device on the probe in at least one RFPD in which the design verification target circuit is implemented. Shift register arrays in which parallel-load and serial-loads are all logically equal in length by one flop (length is the number of flip-flops on the shift register array structure). The amount of shift register array structures that can be structured or that the longest parallel and serial loads can both be modulated by mode conversion. In the output probe mode, each of the dual input flip-flops Each input is connected to the output signal lines of the memory device on the output probe to enable each of the logic values on the output probe on the output probe to be loaded in parallel to each of the dual input flip-flops, and then at least one shift register array structure. The output of the flip-flop is logically connected to one of the I / O pins that serve as one or more output probes of the corresponding RFPD, and according to the shifting operation synchronized with the probe clock of the shift register. The logic values of all the flip-flops are sequentially displayed on the input / output pin serving as the output probe line.In the input probe mode, one or more parallel loads and serial loads exist in each of the shift register array structures capable of changing mode. The input of one flip-flop acts as one or more input probes of the corresponding RFPD. Logically connected to one of the input and output pins so that the input probe value sequentially supplied from the outside through the input and output pins acting as the input probe line by the shifting operation synchronized with the probe clock to be loaded into the shift register in a serial manner. The output of each of the flip-flops constituting the shift register array capable of parallel loading can be a system clock (a system clock, which is used globally for a circuit for design verification). A single user clock, or a master clock used to generate one or more user clocks used in the design verification circuit), if directly connected, each of which drives each of the corresponding input probe signal lines. Individual dual-input replacements for memory elements When a system clock is not directly connected to one of the flop data inputs or the clock input of the memory device being probed, an asynchronous set of each memory device driving each of the input probe signal lines is performed. ) And the asynchronous set input and asynchronous reset input of the flip-flop in the flip-flops of the shift register array to replace the input probe value for the memory device on which this probe is located. It is controlled by the output line of the flip-flop, the operation mode control line and the output line of the finite state machine for the memory device probe, and the output line of the flip-flop having the input probe value for the memory device. One data input of the dual input flip-flop replacing the memory element of the user circuit The output of the memory device, which is the input probe target, is set to 0 or 1, which is a logic value of a flip-flop having an input probe value for the memory device, through an asynchronous set or reset followed by an asynchronous set or reset. You can implement it by enabling it. For this purpose, the above-mentioned finite state machine (Finite State Machine) for the memory element is additionally required. The role of the finite state machine used here is a shift register array only when the asynchronous set and asynchronous reset of the memory element to be input probe are required. In addition to generating and supplying a set / reset enable signal such that an asynchronous set or asynchronous reset occurs according to a signal value supplied from the same, the asynchronous set or asynchronous reset followed by a synchronous set or asynchronous reset. The dual input flip-flop is supplied with an input data selection signal of a dual input flip-flop which causes a miracle reset to occur as a logic value of a flip-flop having an input probe value for the memory device. To do this, the flip-flops of the shift register array have the output line of the flip-flop having the input probe value for the memory device that is on the probe, the set / reset enable signal line from the finite state machine for the memory device probe, and the operation mode control (

/ Probe mode) Signal lines should be used to control the asynchronous set and asynchronous reset of the memory device to be input probe as intended. This can be defined and implemented using a simple combination function. The functional behavior and role of the finite state device for the memory device probe will be described in detail later with examples. In addition, if some or all of the memory devices used in the design verification target circuit already have an asynchronous set and an asynchronous reset, and the system clock is not directly connected to the clock input of these memory devices, the corresponding memory device to be input probe target. Functional logic of the original design verification circuit while attempting to convert the circuit as mentioned above as an additional IOP probe additional circuit including a control circuit for driving asynchronous set and asynchronous reset inputs while using the It can be considered that it can only be modified in normal mode, which is not difficult, and this will be described later with an example.

As another example of implementing the function of the IOP-probe supplementary circuit, a memory element or a locally generated signal using a clock input gated by a mixed verification system means (or module) is examined by a circuit for design verification. In the case of a memory device using a clock input, a mixed verification system means (or module) is a function that is functionally equivalent to the original design verification target circuit and is fully synchronous to the system clock. The newly synthesized circuit uses a circuit fully synchronized with the system clock as a new design verification circuit instead of the original design verification circuit, so that the IOP-probe supplementary circuit is included in at least one RFPD in which the design verification circuit is implemented. The signal lines and dual input flip-flops of the device And the serial register can be a shift register array structure that can both be modulated by mode conversion, or the parallel and serial loads with the longest parallel load and serial load can be different by shift mode. Is a positive integer multiple of all possible shift register array structures in accordance with the mode conversion. In the output probe mode, one input of each of the dual input flip-flops is connected to the output signal lines of the memory device on the output probe, thereby outputting the signal line on the output probe. Inputs and outputs of one flip-flop in each of the one or more shift register array structures to enable parallel loading of each of the logical values on the dual input flip-flop into each of the one or more shift register array structures. Logically connected to one pin In accordance with the shifting operation synchronized with the probe clock of the shift register, the logic values of all the flip-flops of the shift register are sequentially displayed on the input / output pin serving as the output probe line.In the input probe mode, one or more parallel loads and serial As long as the load is present in each shift register array structure that is fully modifiable, the flip-flop's inputs are logically connected to one of the input and output pins, which serve as one or more input probes of the RFPD, for synchronized shifting operation with the probe clock. Flip-flops constituting a shift register array capable of loading the input probe values sequentially supplied from the outside through an input / output pin serving as the input probe line to the shift register in a serial manner and enabling the parallel load. Each output The system clock is directly connected to the clock inputs of all memory devices to be probed, so that it is connected to one input of each dual input flip-flop that replaces each memory device driving each of the input probe signal lines. Can be implemented. However, the case where the memory element used in the design verification target circuit is the latch will be described later.

In addition, the design verification circuit includes memory such as RAM or ROM, and these memories are also provided on-chip memory (specifically, for example, distributed RAM or block RAM of Xilinx FPGA). In the case of using an embedded system block of Altera FPGA, a memory read / write additional circuit is additionally included in the IOP probe additional circuit. The memory read / write additional circuit is controlled by the mixed verification system means (or module), and in the output probe mode, the contents of all regions or specific regions of the memory in the design verification target circuit implemented in the RFPD are all arranged in a predetermined order. It can be read and read in an automated way by the mixed verification system means (or module) through the relay module and the relay cable through the output probe.In the input probe mode, the data held by the mixed verification system means (or module) can be relayed. Through the cable and the relay module, through the RFPD input probe, write is performed in an automated manner in a predetermined order in all areas or specific areas of the writable memory existing in the design verification target circuit implemented inside the RFPD. do.

As a specific example of such a memory read / write additional circuit, first, a read / write control signal for the memory and an address sequence for all memory regions to be read / write are generated, and clocked as necessary. In the case of a memory, it can be configured using a finite state machine, a multiplexer, and a flip-flop for a memory probe that generates clock signals. FIG. 2 schematically illustrates such an example. . The operation of the memory read / write additional circuit will be described in detail as follows.

/탐침모드) 신호선과 탐침모드제어(

/출력탐침) 신호선과 탐침용메모리읽기쓰기(

/있음) 신호선, 그리고 탐침 클럭을 입력으로 하여 메모리에 대한 읽기/쓰기 제어 신호(81), 특정 번지의 어드레스 신호(82)와 메모리입력단 멀티플렉서1(83)의 선택입력 신호(84), 그리고 필요시 메모리 클럭신호(85)까지를 발생하여 상기 메모리에 대한 읽기/쓰기 제어 신호(81)와 특정 번지의 어드레스 신호(82), 그리고 필요시 메모리 클럭신호(85)까지를 메모리입력단 멀티플렉서1(83)의 출력부에 나타나게 하여 특정 번지에 있는 현재내용이 메모리 출력단(86)에 나타나게 한 후에, 메모리 출력단의 플립플롭들(87)에 대한 활성화(enable) 신호를 생성하여 메모리 출력단(86) 값을 메모리출력단의 플립플롭들(87)에 저장시키고서 메모리 출력단의 플립플롭들(87)에 대한 입력선택 신호를 생성하여 메모리 출력단의 플립플롭들(87)이 탐침 클럭에 동기화된 쉬프트레지스터 구조가 되어서 쉬프팅 동작을 통하여 상기 특정 번지에 있는 현재내용이 출력탐침선에 순차적으로 나타나게 함으로서 메모리의 특정 번지에 있는 현재내용을 읽어낼 수 있는데, 메모리탐침용 유한상태기(90)는 이와 같은 메모리의 특정 번지에 대한 읽기 수행을 읽기 대상이 되는 모든 메모리 번지들에 대하여 순서적으로 자동화된 방식으로 수행한다.In the output probe mode, the finite state machine 90 for memory probes operates in the operation mode (

Signal line and probe mode control

Read / write of signal line and probe memory

Read / write control signal 81 for the memory, address signal 82 of a specific address, selection input signal 84 of the memory input multiplexer 1 83, and required Up to a memory clock signal 85 at a time, and read / write control signal 81 for the memory, an address signal 82 at a specific address, and a memory clock signal 85 if necessary, to the memory input multiplexer 1 (83). After the current contents at a specific address are displayed at the memory output terminal 86, an enable signal is generated for the flip-flops 87 of the memory output terminal. A shift register in which the flip-flops 87 of the memory output stage are synchronized with the probe clock by generating an input selection signal for the flip-flops 87 of the memory output stage by storing them in the flip-flops 87 of the memory output stage. The current structure at the specific address of the memory can be read out sequentially by making the current structure at the specific address appear in the output probe line through the shifting operation. The memory probe finite state machine 90 A read operation on a specific address of the memory is performed in an orderly and automated manner for all memory addresses to be read.

/탐침모드) 신호선과 탐침모드제어(

/출력탐침) 신호선과 탐침용메모리읽기쓰기(

/있음) 신호선, 그리고 탐침 클럭을 입력으로 하여 메모리에 대한 읽기/쓰기 제어 신호(81), 특정 번지의 어드레스 신호(82)와 메모리입력단 멀티플렉서1(83)의 선택입력 신호(84)를 메모리입력단 멀티플렉서1(83)의 출력부에 나타나게 하여 메모리쓰기 대상이 되는 특정 번지를 쓰기로서 억세스하고, 탐침클럭을 입력으로 하여 메모리의 데이터입력단의 쉬프트레지스터(88)가 탐침클럭에 동기화된 쉬프팅 동작에 의하여 상기 메모리쓰기 대상이 되는 특정 번지에 쓰여질 데이터 내용을 입력탐침선을 통하여 순차적으로 입력되는 논리값으로써 쉬프팅 동작이 완료되는 시점에 상기 데이터입력단의 쉬프트레지스터(88)에 저장하게 하고, 메모리의 데이터입력단의 멀티플렉서2(89)의 선택입력의 신호선에 대한 선택 신호를 발생시키고, 필요시 메모리 클럭신호(85)까지를 발생하여 상기 메모리쓰기 대상이 되는 특정 번지에 상기 데이터입력단의 쉬프트레지스터(88)에 저장되어 있는 상기 데이터 내용이 쓰여지도록 하는데, 메모리탐침용 유한상태기(90)는 이와 같은 메모리의 특정 번지에 대한 쓰기 수행을 쓰기 대상이 되는 모든 메모리 번지들에 대하여 순서적으로 자동화된 방식으로 수행한다.In the input probe mode, the finite state machine for memory probes 90 controls the operation mode.

Signal line and probe mode control

Read / write of signal line and probe memory

Signal line and probe clock as inputs, read / write control signal 81 for the memory, address signal 82 of a specific address, and selection input signal 84 of memory input stage multiplexer 1 (83) to the memory input stage. Appears on the output of the multiplexer 1 (83) to access a specific address which is a memory write target, and as a probe clock as an input, the shift register 88 at the data input terminal of the memory is synchronized by a shifting operation synchronized with the probe clock. The data contents to be written to the specific address to be written into the memory are sequentially input through the input probe line, and are stored in the shift register 88 of the data input terminal at the time when the shifting operation is completed. Generates a selection signal for the signal line of the selection input of multiplexer 2 (89), and if necessary, memory clock signal (85). The data contents stored in the shift register 88 of the data input terminal are written to a specific address to be the memory write target, and the finite state machine 90 for the memory probe has a specific address of the memory. The write operation is executed in the ordered and automated manner for all the memory addresses to be written to.

The memory probe finite state machine 90 has a built-in address generator for the memory address area to be read / written for memory read / write. The memory read / write additional circuit described above has a dual port memory. (Two-port Memory) can be similarly applied.

delete

In the present invention, the output probe line and the input probe line may exist as separate independent unidirectional probes, or may exist as bidirectional probes in which the output probes and the input probes are combined.

The mixed verification system means (or module) comprises the steps of inputting the onboard signal lines and memory present in the design verification target circuit or the onboard signals and memory block present in the design verification HDL code, For the generation of programming patterns for one or more RFPDs mounted on a typing board, the signal lines on the output probe or the logic values at a specific time period or when a specific situation occurs in the memory area to be read only for a certain period of time. Design verification targets assigned to one or more RFPDs mounted on any prototyping board so that the signal lines on the input probe or the memory area to be written to may have logical values applied to the input probe at specific times. By adding an IOP probe additional circuit to the circuit, Further comprising: the property. In addition, for the signal lines on the output probe and the memory area to be read, the logic values and the contents of the memory at a specific time period on the signal lines on the output probe are displayed on the output probe of the corresponding RFPD by using the IOP probe additional circuit. The value shown in the output probe is transmitted to the server computer through the relay cable and the relay module so that the simulator can have the current status information of the design verification target circuit as the initial status value for the simulation. For the memory area, after generating the input probe data from the state information obtained through the simulation in the server computer, apply it to the signal line on the input probe of the corresponding RFPD by synchronizing with the probe clock only through the relay module and the relay cable, or Probe Mode with Synchronization with Probe Clock RFPD is applied by changing the probe mode between the input probe mode and the output probe mode through the control signal line so that the logic value of the signal lines on the input probe and the contents of the memory area to be written have the logic values transmitted through the input probe line. And setting the state information of the design verification target circuit implemented in the simulator equal to the state information generated through the simulation for a predetermined period of time in the simulator.

The emulation and simulation mixed verification method according to the present invention comprises the steps of inputting a design verification target circuit and an ASIC vendor library name to a server computer, and designating the signal lines and memory areas on the coveted design verification target circuit required for the hybrid verification. And the logic value at the specific time zone of the signal probe on the output probe and the memory area only appears for a certain time on the output probe and the logic value at which the signal wire and memory area on the input probe is applied to the input probe at a specific time period. Generating an extended design verification circuit by adding an IOP probe additional circuit to the design verification circuit that is implemented in one or more RFPDs, and implementing the extended design verification circuit in one or more RFPDs. Technology mapping, layout and wiring, and programming pattern generation steps, Mixed verification system means (or modules) at any time set by the user or at any time during the operation of the design verification target circuit implemented in one or more RFPDs mounted on an arbitrary prototyping board with a programming pattern Output probe of the at least one RFPD by performing an output probe on the at least one RFPD under the control of In addition to the steps shown in the above, the value of the output probe line so sent to the server computer via the relay module and the relay cable to automatically set to the initial value of the simulation to perform the simulation by the simulator, the user during the simulation through the simulator At any point in time or in any situation Input of at least one RFPD mounted on an arbitrary prototyping board via the relay cable and the relay module from the server computer using the input probe method using the input probe method using the IOP probe additional circuit obtained through the simulation By having the memory element and the memory area that is on the input probe through the probe line, it is possible to automatically perform the emulation following the simulation.

In the emulation and simulation hybrid verification method according to the present invention, inputting a design verification target HDL code and an ASIC vendor library name into a server computer, and performing a step-by-step signal and memory region on the design verification target HDL code required for the hybrid verification. Specifying that the signals on the output probe and the logic value at a specific time zone of the memory area appear only on the output probe for a certain period of time, and the signals on the input probe and memory area are applied to the input probe at the specified time zone. Generating an extended design verification HDL code by additionally adding an additional HDL code for IOP-probe to a design verification target HDL code implemented in at least one RFPD to have a logic value, and adding the extended design verification target HDL code to 1 Synthesis and technology mapping, layout and wiring, and programming patterns for implementation in the above RFPD And any point or situation set by the user during the operation of a circuit functionally equivalent to the design verification target HDL code implemented in one or more RFPDs mounted on any prototyping board by the programming pattern. The output probe of the at least one RFPD is performed by performing an output probe on the at least one RFPD at the time of occurrence, and using the IOP probe additional circuit to display the logic values and the contents of the memory area of the memory devices on the output probe. In addition to the steps shown in the above, the value of the output probe line so sent to the server computer via the relay module and the relay cable to automatically set to the initial value of the simulation to perform the simulation by the simulator, the user during the simulation through the simulator At any point in time or in any situation The state information of the HDL code to be verified through design is obtained by using one or more RFPDs mounted on an arbitrary prototyping board via a relay cable and a relay module from a server computer by using an input probe method using an IOP probe additional circuit. By having the memory element and the memory area to be on the input probe through the input probe, it is possible to automatically perform the emulation following the simulation.

Other objects and advantages of the present invention in addition to the above object will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram schematically showing an emulation and simulation mixed verification apparatus according to the present invention composed of a mixed verification system means (or module) operating in a server computer, a connection cable and a connection module.

2 illustrates, as an example of a specific implementation of a memory read / write additional circuit, first generates a read / write control signal for a memory and an address sequence for all memory regions to be read / write, and clocks as necessary. In the case of the locked memory, an example of a finite state machine for generating a clock signal, a multiplexer, and a flip-flop are shown.

In the emulation and simulation mixed verification method according to the present invention, a mixed verification system means (or module) generates an IOP probe additional circuit for input / output probing of a logic value and a memory area of a memory element of a design verification target circuit. And adding to the circuit to be verified to create an extended circuit for design verification. First, in the case where the design verification target circuit does not have a memory and a flip-flop is used as the memory element, it is assumed that all of the flip-flops are D-type flip-flops.

In this step, the circuit designed by adding an additional circuit in the output probe mode is an extended design verification target circuit, which is a circuit made by adding an IOP-probe supplementary circuit to the design verification target circuit. Synchronized shifting operation is performed by the shift value of the shift register immediately before the shifting operation with the logic value of the signal lines to be output probe.In the input probe mode, the circuit part formed by adding additional circuit is shifted by shift register structure. By using this shifting operation, a synchronous set or synchronous reset operation for a flip-flop that is an input probe object, or a synchronous set or an asynchronous reset operation or an asynchronous reset operation is performed. Synchronous following synchronous reset or asynchronous set or asynchronous reset operation Disable operation makes the logic value of the flip-flops to be the input probe value as the input probe value.In the normal mode, the functional logical behavior of the circuit for design verification even if the additional circuit for IOP probe is added. ) Is to have an unalterable behavior. An example of an asynchronous circuit used to specifically illustrate this is illustrated in FIG. The clock inputs of all the flip-flops in the circuit of FIG. 3 do not physically connect the system clocks of the circuits (as opposed to logically connected in the sense of physically connected), such as a gated clock. . The circuit of Figure 3 is a 4-bit Asynchronous Binary Counter, where the system clocks of the circuit are not physically connected to the clock inputs of the three flip-flops except the flip-flop of the least significant bit.

FIG. 4 is a diagram schematically showing symbols and functional functions of various D-type flip-flops, and FIG. 5 is an example of a parallel loadable shift register array structure showing an additional circuit for an IOP probe according to the present invention. FIG. 6 is a diagram schematically showing another example of the structure of a shift register array capable of parallel loading in FIG. 5, and FIG. 7 is an example of implementing the dual input D-type flip-flop of FIG. It is a figure which shows schematically. An extended design verification subject circuit to which an IOP probe additional circuit is added to enable input / output probes to all 4-bit output lines of a 4-bit asynchronous binary counter as shown in FIG. 3 is shown in FIG.

/탐침모드) 신호선들을 이용하여 입력탐침 대상이 되는 플립플롭의 비동기 셋과 비동기 리셋을 제어할 수 있도록 도8 (b) 와 같은 조합회로 기능이 필요하다. 도8 (b)에서의 조합회로의 입력들과 출력들에 대한 의미를 다르게 코딩하는 경우에는(예로 FSMOut의 0과 1의 의미를 바꾸어서 해석 등) 물론 도8 (b)의 진리표(truth table)가 달라지게 된다.In the output probe mode, the circuit of Fig. 8 (a) is logically 4 in length by the signal line and the double input flip-flops (PFF0, PFF1, PFF2, and PFF3 in Fig. 8 (a)) together with the circuit for design verification. And a parallel-loadable shift register array structure in which a single input of each of the dual input flip-flops is connected to each of the signal lines on the coveter so that the logic values of the signal on the coveter are parallel to the dual input flip-flop. As long as the output is probed, the output of the flip-flop (in this case, the rightmost PFF3) can be logically connected to the input / output probe as long as it exists in the shift register array structure. One input of one flip-flop present in each of the lengthwise parallel-loadable shift register array structures The output of each of the flip-flops (p0, p1, p2, and p3 in Fig. 8 (a)) is connected to the input probe line and the output of each of the flip-flops constituting the parallel-loadable shift register array is input. Dual-input flip-flop (FF0 in FIG. 8 (a)) which is replaced among respective flip-flops (FF0, FF1, FF2, and FF3 in FIG. 3) for driving each of the probe signal lines (here, y0, y1, y2, and y3). Either one is connected to one of the inputs (if the system clock is connected to the clock input of the corresponding flip-flop, so only FF0 is used here) or each flip-flop is a dual-input flip-flop with an asynchronous set and an asynchronous reset. Substitute the flip flop to control the asynchronous set input and the asynchronous reset input of the flip flop so that the values of the flip flop are the desired input probe values, and then, among the flip flops constituting the shift register array, (Here, D ₂₎ via a data input of the dual-type flip-flop coupled to the output by allowing to set the output of the flip-flop to the final synchronous three or synchronously reset to 0 or 1 (the clock for the flip-flop This is the case when the system clock is not connected to the input. Therefore, FF1, FF2, and FF3 can be implemented. This requires an additional finite state machine for the memory device probe. The finite state device for the memory element probe used here is such that the asynchronous set or asynchronous reset occurs by the signal value supplied from the shift register array only when the asynchronous set and the asynchronous reset of the flip-flop to be input probe are required. In addition to controlling, the final synchronous set or synchronous reset of the dual-input flip-flop occurs with the logic value of the corresponding flip-flop among the flip-flops constituting the shift register array. For this purpose, the signal line from the shift register array, the signal line from the finite state machine for the memory element probe, and the operation mode control (

/ Combined mode) A combination circuit function as shown in FIG. 8 (b) is required to control the asynchronous set and asynchronous reset of the flip-flop to be the input probe object using the signal lines. In the case of differently coding the meanings of the inputs and outputs of the combination circuit in FIG. 8 (b) (for example, by changing the meaning of 0 and 1 in FSMOut, etc.), the truth table in FIG. 8 (b) is of course. Will be different.

Figure 9 (a) shows that any one or more flip-flops in the design verification target circuit already have an asynchronous set and an asynchronous reset, and a locally generated local clock without a system clock directly connected to their clock inputs. Or the gated clock is connected. In such a case, the circuit conversion as described above is performed as an additional IOP probe additional circuit including a combination control circuit driving the asynchronous set and asynchronous reset inputs while using the corresponding flip-flops that are the input probe targets as described above. In the normal mode, the functional logic properties of the original design verification target circuit are not deformed. FIG. 9 (b) illustrates such a situation and the truth table of the combined control circuit used at this time is shown in FIG. 9 (c). Is shown. The role of the finite state device for the memory element probe which is driven in synchronization with the probe clock is that in the input probe mode, the asynchronous set input and asynchronous reset input of the dual input flip-flop which replaces the flip-flop which is the input probe target are selected. An asynchronous set / reset enable signal that controls the input probe value stored in a specific flip-flop of the shift register array constituting the IOP-probe supplementary circuit in the cycle so that the input probe occurs only at the specific cycle of the probe clock. (In this case, active), and in an input probe mode an asynchronous set of the dual input flip-flops that replaces the particular flip-flop that is the input probe target in cycles other than the specific cycle of the dual input probe clock. To generate an asynchronous set / reset enable signal that disables (In this case, deactivated), and in normal operation mode, it generates an asynchronous set / reset enable signal that allows the extended design verification circuit to be functionally equivalent to the original design verification circuit (in this case, Inactivation) driving a control circuit connected to the asynchronous set input and the asynchronous reset input of the dual input flip flop replacing the flip flop on the input probe, and the corresponding flip among the flip flops constituting the shift register array. The logical value of the flop controls the final synchronous set or synchronous reset of the dual input flip flop.

The extended design verification target circuit generated by adding the IOP-probe supplementary circuit to the design verification target circuit is converted into a programming pattern and downloaded and implemented in one or more RFPDs on an arbitrary prototyping board. In the process of performing emulation-based verification, when a transition to simulation is required at a specific time or when a specific situation occurs, the mixed verification system means (or module) detects this and stops the emulation. One or more outputs connected to the output of one flip-flop present in each of the one or more shift register array structures when the probe clock is applied to the RFPD after the corresponding one or more RFPDs are switched from the normal mode to the output probe mode under the control of the means (or modules). On the signal lines that are probed through the probe Logic values are transmitted to the server computer through the relay module and the relay cable, and the current state information consisting of these logic values is provided to the simulator as an initial state for the simulation of the simulator so that the conversion from emulation to simulation can be performed automatically. To be able. However, in the emulation, the timing of switching the simulation may be determined statically before the emulation is performed, and may be determined dynamically such as when a specific situation occurs during the emulation, and the emulation stops at the same time as the specific situation occurs. To determine the situation, an external device such as a logic analyzer can be used to observe and stop the emulation, or by adding an additional Event Detector circuit that detects the situation inside the RFPD. May be observed and mixed validation system means (or modules) may stop the emulation. When the condition detector circuit is additionally added to the design verification circuit in addition to the IOP-probe supplementary circuit in the RFPD, its automatic generation and addition is also in charge of the mixed verification system means (or module).

Conversely, if the simulation is stopped at a certain point in time during the simulation by the simulator or when a specific situation occurs, the mixed verification system means (or module) detects this and the corresponding one or more from the last state information of the design verification target circuit obtained by the simulation. After generating the input probe data for the RFPD, and then switching the operation mode to the input probe mode under the control of the mixed verification system means (or module), the probe clock is applied to the RFPD to each of the one or more shift register array structures. The input probe data transmitted from the server computer through the relay cable and the relay module through one or more input probes logically connected to the input of the flip-flop present are stored in the flip-flops existing in each of the one or more shift register array structures. Saved inputs The immersion data finally sets the flip-flops on the input probe into a synchronous set or reset operation, or an asynchronous set or reset operation followed by a synchronous set or reset or asynchronous set or reset. Synchronous disabling followed by operation allows the state information of one or more RFPDs mounted on any prototyping board to be the same as the state information generated by the simulation, so that the emulation can be switched automatically in the simulation. To be.

By doing the above, the design verification of the design verification target circuit can be alternately performed freely without any limit on the number of conversions by emulation and simulation.

All RFPD products currently on the market have a large number of flip-flops inside the device, all of which are D-type flip-flops. If the flip-flop used in circuit design uses RS, JK, or T type instead of D type, use a simple combination circuit with the D type flip flop to form a functionally equivalent circuit. The equivalent circuit will be implemented. Therefore, the method of generating the probe additional circuit in the probe method according to the present invention is a method that can be applied to any type of flip-flop used in the circuit.

In addition, in the case where the memory element used in the design verification target circuit is a latch, first, before using the above methods, each latch is converted using a flip-flop and a combination circuit as shown in FIG. 10 to be functionally equivalent to the original latch. After obtaining the above methods are applied.

FIG. 11 is a flowchart for explaining step by step a method of timing and functional temporal mixing verification according to an embodiment of the present invention, which is performed by the server computer 20 shown in FIG.

In step 100, after inputting the design verification target circuit and the ASIC vendor library name used in the design using the server computer, the IOP probe is added to the RFPD of any prototyping board capable of input / output probe according to the present invention. Create a programming pattern for implementing the extended design verification circuit with circuits added and download it to the RFPD on any prototyping board so that the extended design verification circuit can be implemented on the RFPD, Prepare to perform simulation of the design verification target circuit using the simulator (S100). In step 102, initial state information (value for all memory elements (flip-flops or latches) in the circuit) for the design-validation target circuit, which is the emulation and simulation mixed verification target, is used by using the server computer 20. Current state information of simulation circuit for arbitrary simulator and emulation circuit for arbitrary prototyping board with the initial state information and determine the verification stop time or stop condition to determine the current verification stop time or stop. It is set as conditions (S102). In step 104, it is determined whether to perform simulation verification or emulation verification with the current state information (S104). If emulation verification is performed, the process proceeds to step 106 and emulation verification is performed until the current verification stop time or stop condition is satisfied using the arbitrary prototyping board (S106). In step 108, the execution of the verification is stopped when the current verification stop time or the stop condition is satisfied, and then it is examined whether additional verification is required. If no additional verification is required, the entire verification process is ended, and if further verification is required, the flow proceeds to step 110 (S108). In step 109, a new current verification stop time or stop condition is determined (S109). In operation 110, it is examined whether switching of the verification method is necessary (S110). If it is not necessary to switch the verification method, the process proceeds to step 112 and it is checked whether the current verification method is an emulation verification or a simulation verification (S112). If the current verification method is emulation verification, the flow proceeds to step 106, and if the simulation verification proceeds to step 120. When the simulation verification is performed in step 104, the process proceeds to step 120, and simulation verification is performed until the current verification stop time or stop condition is satisfied using an arbitrary simulator on the server computer (step 108). S120). If it is necessary to switch the verification method in operation 110, the process proceeds to operation 130 to determine whether the verification conversion is a transition from simulation verification to emulation verification, or whether the transition from emulation verification to simulation verification is performed (S130). If the verification transition is a transition from simulation verification to emulation verification, proceed to step 132 to implement current state information of the design verification target circuit at the current verification stop point obtained through the simulation on the server computer in the RFPD on any prototyping board. In step S132, the input probe of the present invention is performed on the RFPDs so that the extended design verification target circuit may have the same. If the verification transition is a transition from emulation verification to simulation verification, proceed to step 134 and at the current verification stop obtained through the output probe of the present invention for the extended design verification target circuit implemented in the RFPD on any prototyping board. The present invention performs the output probe of the present invention on RFPDs on any prototyping board so that the current state information of the design verification target circuit of the circuit can be equally maintained by any simulator on the server computer. Proceed to step (S134).

FIG. 12 is a flowchart for explaining step by step a simulation and emulation mixing verification method according to another embodiment of the present invention, which is performed by the server computer 20 shown in FIG.

After inputting the design verification target HDL code and the RFPD vendor library name using the server computer in step 300, using this to express the behavior of the IOP-probe supplementary circuit of the present invention to the RFPDs on any prototyping board. Create a programming pattern for implementing the extended design verification target HDL code with the added HDL code (called the HDL supplementary code for the IOP-probe) and download it to the RFPD on the prototyping engine. Simultaneously with the implementation of the RFPDs, the server computer prepares to perform simulation of the design verification target HDL code using an arbitrary simulator (S300). In step 302, the initial state information of the design-verification target HDL code to be simulated and emulated mixed verification is input using the server computer 20, and the current state of the simulation HDL code for the arbitrary simulator and the HDL code for emulation is input. The information is made the same as the initial state information, and the verification intermediate stop time or stop condition is determined to be the current verification stop time or stop condition (S302). In step 304, it is determined whether to perform simulation or emulation with the current state information (S304). If emulation is performed, the process proceeds to step 306 and verification is performed until the current verification stop time or stop condition is satisfied using the above-described arbitrary prototyping board (S306). In step 308, the execution of the verification is stopped when the current verification stop time or the stop condition is satisfied, and then it is examined whether additional verification is required. If no additional verification is required, the entire verification process is ended, and if further verification is required, the process proceeds to step 310 (S308). In step 309, a new current verification stop time or stop condition is determined (S309). In operation 310, it is examined whether switching of the verification method is necessary (S310). If it is not necessary to switch the verification method, the flow proceeds to step 312 to determine whether the current verification method is emulation or simulation (S312). If the current verification method is emulation, the method proceeds to step 306 and, if the simulation, proceeds to step 320. If the simulation is performed in step 304, the process proceeds to step 320, and the verification is performed until the current verification stop time or stop condition is satisfied using an arbitrary simulator on the server computer (S320). . If it is necessary to switch the verification method in operation 310, the flow proceeds to operation 330 to determine whether the verification conversion is a conversion from simulation to emulation or a conversion from emulation to simulation (S330). If the verification transition is a transition from simulation to emulation, the flow proceeds to step 332 where the current state information of the current verification target HDL code obtained through the simulation on the server computer is transferred to the RFPDs on the arbitrary prototyping board. The input probe of the present invention is performed on the RFPDs on the arbitrary prototyping boards so that the implemented extended design verification target HDL code may have the same (S332). If the verification transition is a transition from emulation to simulation, the flow proceeds to step 334 where the current verification stop obtained through the output probe of the present invention for the extended design verification target HDL code implemented in the RFPDs on the arbitrary prototyping board. The output probe of the present invention is applied to the RFPDs on any prototyping board so that the current state information of the design verification target HDL code is equally retained by any simulator on the server computer. The process proceeds to step 320 (S334).

As described above, the emulation and simulation mixed verification apparatus according to the present invention and the mixed verification method using the same are implemented in one or more RFPDs mounted on an arbitrary prototyping board and emulated in the design verification target circuit and any simulator By enabling the exchange of state information between the simulated design verification target circuits in an automated manner, it is possible to perform high-speed functional verification and accurate timing verification alternately, and thus, very effective verification can be performed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the scope of the claims.                     

Claims (20)

In an emulation and simulation mixed verification apparatus comprising a mixed verification system means (or a module), a relay module, and a relay cable, The mixed verification system means (or module) is HDL representing the behavior of an IOP-probe supplementary circuit or an IOP-probe supplementary circuit for a design subject circuit implemented in one or more RFPDs mounted on any prototyping board. A code can be generated and a programming pattern for the one or more RFPDs can be generated by adding an HDL code representing an action of an IOP-probe supplementary circuit or an IOP-probe supplementary circuit to a design verification target circuit or an HDL code. At any point in time or in any situation during the operation of the design verification subject circuit implemented in one or more RFPDs by performing input / output probes using HDL codes representing the behavior of the probe supplementary circuit or the IOP probe additional circuit. Pass full or partial status information to the simulator in an automated manner, or obtain from the simulator in an automated manner And can help, Emulation and simulation mixed verification device for such a state information transfer is made in an automated manner between the relay module and one or more RFPD on any prototyping board and any simulator running on a computer via the relay cable. The method of claim 1, Prior to automatically generating the HDL code representing the behavior of the IOP-probe supplementary circuit or IOP-probe supplementary circuit by performing the mixed verification system means (or module), the design verification subject circuit or design verification subject HDL code Is used as a mixed verification system means (or module) to generate a new design verification target circuit or design verification target HDL code that is functionally equivalent to the original circuit or HDL code and fully synchronized with a single system clock. Emulation and simulation mixed verification device, characterized in that used as the verification target circuit. The method of claim 1, A circuit part formed by adding an additional circuit in the output probe mode in which the extended design verification circuit is completed by adding the IOP-probe supplementary circuit to the design verification circuit is shiftable in parallel to the memory device on the output probe. The shifting operation synchronized with the probe clock by the register structure is executed by parallel loading immediately before the shifting operation, and the logic value of this shift register has the logic values of the memory elements that are the output probe targets. The contents of the area can be read by a read operation. In the input probe mode, a circuit portion formed by adding an additional circuit has a shift register structure that can be loaded in a serial manner for a memory device on the input probe. Using shifting motion Synchronous set or reset operation, or asynchronous set or reset operation for each of the memory elements targeted for input probes, or synchronous set or reset or asynchronous set, or By selectively applying the synchronous disable operation following the reset operation, the logic values of the memory elements that are the input probe targets are input probe values, and if necessary, the write operation of the corresponding area is written to the memory on the input probe. In the normal mode, the emulation and simulation mixed verification device, comprising a circuit which does not deform the functional logic properties of the circuit for design verification even if an additional circuit for IOP probe is added. When the design verification target is dictated by the HDL code, the extended HDL code that is completed by adding the HDL additional code representing the behavior of the IOP-probe supplementary circuit to the design verification HDL code is additional HDL code in the output probe mode. The HDL part formed by adding the code expresses the shift register behavior that can be loaded in parallel to the memory device on the output probe.The shifting operation synchronized with the probe clock is expressed by the HDL code immediately before the shifting operation. The signal values of the signal line of the register HDL code in the circuit have the signal values to be the output probe target by parallel load and can read the specific area of the memory on the output probe by the read operation. HDL code part formed by adding code is input A shift register structure that can be loaded in a serial manner for the memory device on the probe bed performs a shifting operation synchronized with the probe clock, and uses the shifting action to express the memory element behavior of the HDL code that is the input probe target. A synchronous set or reset operation on the signals of a signal, or an asynchronous set or reset operation followed by a synchronous set or reset or asynchronous set or reset operation. With the disable operation, the logic value of the signals that are the target of the input probe is set as the input probe value.If necessary, the write of the corresponding area can be written to the memory on the input probe as the write operation.In normal mode, the IOP probe is used. It is special to construct HDL code that does not change the behavior of design verification HDL code even if additional circuit is added. Emulation and simulation mixed verifying apparatus as set. The method of claim 3, wherein Extended design validation circuits with IOP-probe supplementary circuits are used in output probe mode for memory devices on output probes, in addition to the design validation circuits assigned to this RFPD in the probe bed RFPD and on the probe The flip-flops make the shift register array structure capable of logically loading parallel lengths of one or more lengths, or the shift register array structure capable of the longest parallel load lengths of the shift register array structure. An input probe of each of the dual input flip-flops is connected to the signal boards on the coveted signal line, allowing each of the signal boards to be loaded into the dual input flip-flop in parallel and output probe. In each of one or more shift register array structures The output of a flip-flop is logically connected to one or more output probe lines of this RFPD, and additionally, if necessary, the memory on the output probe is controlled by the memory probe finite state machine built into the RFPD. A flip-flop output present in each shift register array structure that stores the contents read by the read operation is indicated by a shift operation on one or more output probe lines of the RFPD. A flip-flop input in each of the shift register array structures capable of one or more parallel loads is logically connected to one or more input probe lines of the RFPD, thereby shifting the input probe value by a shifting operation synchronized with the probe clock. One or more of the registers by serially loading the registers When the output of each of the flip-flops constituting the shift register array that can be loaded in parallel has a system clock connected to the clock input of each memory device driving each of the input probe target signal lines, each of the corresponding memory devices is replaced. The memory device to be connected to one input of a dual input memory device of the memory device, or to set each of the memory devices to be a synchronous set or a synchronous reset with an output value of each of the flip-flops constituting the shift register array capable of performing one or more parallel loads. When a combination clock is added to the device data input terminal or a system clock is not physically connected to the clock input of the memory device for each of the memory devices driving each of the input probe target signal lines, the memory device is asynchronously set. Memory device with reset and asynchronous reset And a combination circuit for controlling the asynchronous set input and the asynchronous reset input of the memory device, and including the asynchronous set or asynchronous reset operation for the memory device. It can be implemented by setting it to a specific input probe value, and if necessary, additionally, at least one of the RFPD is input to each of the first flip-flop inputs in each of the shift register array structures in the memory data input stage. The logic register can be applied by the shifting operation from the input probe and the shift register in the memory data input terminal is designated as the write operation by the corresponding region by the memory probe finite state built in the RFPD after the shifting operation is completed. time In the subsequent memory to be written with the contents of the probe groups finite state for the emulation, characterized in that for performing the probe input to the memory to write to the particular memory address and simulation mixed verification device. In a design verification target circuit that is an input probe target, one or more flip-flops in which a locally generated local clock or a gated clock is input without a system clock being integrated into the clock input of one or more flip-flops present in the design verification target circuit. Design and test circuit for input probe additional circuit having finite state and control circuit that generates and outputs serial load-enabled shift register array structure and asynchronous set / reset enable signal for a specific time of probe clock. In addition, in the probe input mode, an input probe value is sequentially loaded from the outside through the serial loading synchronized to the probe clock, and then the flip of the shift register array is performed. Loaded on each of the flops Among the input probe values, the input probe value for the flip-flop that is the input probe target, the asynchronous set / reset activation output value for the flip-flop that is the input probe target generated from the finite state machine, and the operation mode control applied from the outside. It generates the signal values that control the asynchronous set and asynchronous reset of the flip-flop through the control circuit in the value, so that the asynchronous set input and the asynchronous reset input of the flip-flop that is the input probe target are controlled by the signal values in the input probe mode. The input probe is made through a process including an operation, and in the normal operation mode, the extended design verification target circuit generated by adding the input probe additional circuit to the original design verification target circuit is the original design verification target circuit. Probe method that allows you to perform functional equivalents with Emulation and simulation verification method using mixture. An emulation and simulation mixed verification device having a mixed verification system means (or module) that can automatically generate an additional circuit for an IOP probe, and a relay module and a relay cable, which can alternately perform emulation and simulation in an automated manner. . The method of claim 6, Mixed Verification System An emulation and simulation blend verification apparatus that means (or modules) can automatically generate a situation detector. At least one RFPD that implements the extended design verification HDL code in which the extended design verification target circuit or the design verification HDL code is added to the design verification target circuit or the design verification target HDL code. Emulation method to verify by using and simulation method to verify the design verification target circuit or design verification target HDL code by using the simulator is emulated as needed through the transfer of state information in an automated manner between any prototyping board and any simulator. An emulation and simulation hybrid verification method that alternates from simulation to simulation or from simulation to emulation one or more times. The method of claim 8, Emulation-to-simulation or simulation as needed, using IOP-probe supplementary circuits or IOP-probe HDL supplemental code-based input / output probe methods for automated state information transfer between any prototyping board and any simulator. A method of verifying emulation and simulation mixture that alternates one or more times from emulation to. The method of claim 8, Design verification implemented in one or more RFPDs on any prototyping board by simulation using state information collected from the prototyping board through automated state information transfer between any prototyping board and any simulator. Verification method that enables high visibility of the target circuit or design verification target HDL code. delete delete delete delete delete delete delete delete delete delete

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