KR100704681B1 - The device and method for synchronizing frame counter signal at a base station - Google Patents

Abstract

The present invention relates to an apparatus and method for generating frame counter signal synchronized between base stations.

The base station generates a frame counter signal synchronized with the frame clock signal by using absolute time information received from a GPS (Global Positioning System) satellite. That is, a time setting clock signal is generated using absolute time information provided by GPS, and a frame counter signal used as a discriminator for distinguishing a frame order is generated using the time setting clock signal.

Therefore, the frame counter signal of the base stations is synchronized, and as a result, the base station and the terminal can know the absolute order of all frames currently used, and can perform efficient hand-over.

Base station, frame counter, GPS time information

Description

An apparatus and method for synchronizing frame counter signal between base stations {1 device and method for synchronizing frame counter signal at a base station}

1 is a structural diagram of an apparatus for generating a frame counter signal synchronized between base stations according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed structural diagram of the GPS receiver shown in FIG. 1.

3 is a timing diagram between an absolute time setting clock signal, a 1 PPS clock signal, and a system clock signal according to an exemplary embodiment of the present invention.

4 is a detailed structural diagram of a clock generator shown in FIG. 1.

5 is a timing diagram between clock signals of frame counter signal generators synchronized between base stations according to an exemplary embodiment of the present invention.

The present invention relates to a method and apparatus for generating a frame counter signal, and more particularly, to a method and apparatus for generating a frame counter signal synchronized between base stations.

In general, in a mobile communication system, a base station generates a clock signal used for synchronization of various devices in a base station, and there is a base station clock board that provides a clock to an internal device for generating the clock signal.

The base station clock board is developed by applying a GPS receiving module, and outputs the absolute time information synchronized between all base stations based on the absolute time information provided by the GPS satellites using a GPS receiver in the base station clock board, and uses an internal oscillator ( osillator to generate its own system clock signal.

Each clock signal used in the base station includes a system clock signal, a sampling clock signal, a frame clock signal, and a 1 PPS clock signal synchronized internally in each base station. The frame counter signal, which is generated based on the frame clock signal and used to distinguish each frame order, is typically composed of 12-bit serial data to indicate each frame order.

However, the existing frame counter signal is not a frame counter signal synchronized between all base stations of the mobile communication system, but a frame counter signal synchronized only with a frame clock signal generated by each base station. Therefore, a frame counter that is not synchronized between all base stations is used, and thus, it is difficult to distinguish the frame order from each other.

The present invention is to solve the conventional problem, by generating a frame counter signal synchronized between all the base stations, not only the base stations but also the terminals connected to it can accurately identify the frame order, inter-base station synchronized frame An apparatus and method for generating a counter signal are provided.

The frame counter signal generating apparatus according to an aspect of the present invention for achieving the technical problem, in the mobile communication base station, receiving the time information provided from the GPS satellite and generating the frame counter signal, and receives the time information A GPS receiver configured to generate a time setting clock signal synchronized with the system clock signal based on the time information; And a clock generation unit synchronized with the time setting clock signal and generating a frame counter signal having a same value as each sampling clock signal having a predetermined frequency and increasing a predetermined value for each predetermined frame clock signal.

According to another aspect of the present invention, there is provided a method for generating a frame counter signal in a frame counter signal generation method of an apparatus for processing time information provided from a GPS satellite based on a system clock signal of the base station in a mobile communication base station. Receiving time information of the serial data and one PPS clock signal; Converting time information of the serial data into parallel data; Logic operation of a predetermined bit of the converted parallel data to generate an operation value, and outputting the operation value as a time setting clock signal in synchronization with the system clock signal; Dividing the system clock signal to generate a sampling clock signal and a frame clock signal of a predetermined frequency, respectively; And generating and outputting a frame counter signal synchronized with a predetermined time point of the time setting clock signal, the period of each bit being equal to the period of the sampling clock signal, and increasing by a predetermined value according to the frame clock signal. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

In an embodiment of the present invention, a time setting clock signal is generated by using absolute time information provided by a GPS satellite so that the frame order can be distinguished using a frame counter signal synchronized between all base stations. A frame counter signal is generated in synchronization with the timed clock signal.

 1 is a diagram illustrating a schematic structure of an apparatus for generating a frame counter signal synchronized between base stations according to an exemplary embodiment of the present invention. As shown in FIG. 1, an apparatus for generating a frame counter signal synchronized between base stations (hereinafter, referred to as a frame counter signal generator for convenience of description) 1 includes an antenna 10, a GPS receiver 20, and And a clock generator 30.

The GPS receiver 20 receives time information and position information from the GPS satellite through the antenna 10 and interprets the time information and position information, and converts the analyzed time information from serial data to parallel data. The absolute time setting clock signal is generated using the time information converted into parallel data. Since the timed clock signal according to the embodiment of the present invention is a clock signal generated based on absolute time information provided from a GPS satellite, it may be referred to as an "absolute timed clock signal."

The GPS receiver 20 synchronizes a time setting clock signal with a system clock signal of the base station itself, and converts the time information, time setting clock signal, 1 pulse per second (PPS) clock signal, and system clock signal converted into the parallel data. Outputs The system clock signal is a signal synchronized with the time setting clock signal. In addition, one PPS clock signal means one pulse generated per second, and the GPS satellite generates one PPS signal for time information.

Figure 2 shows the detailed structure of such a GPS receiver.

As shown in FIG. 2, the receiver 20 according to an exemplary embodiment of the present invention may include a serial / parallel converter 21, a register 22, an OR logic element 23, and a D flip-flop. (24).

The time information provided by the GPS satellites is composed of 32-bit serial data, which is incremented by one binary number per second based on a specific time. Thus, it is possible to represent an absolute time up to 32 square seconds of 2 at a particular reference time.

The serial / parallel converter 21 converts time information of serial data received from the GPS satellites into parallel data. The register 22 is a 32-bit register, and stores the time information converted into the parallel in a 4-bit nibble unit.

The OR logic element 23 generates an absolute timed clock signal based on the time information. To do this, each bit value of the lowest nibble of the time information stored in the nibble unit in the register 22 is received as an input. At this time, the OR logic element output value "0" is output only when all the bit values of the least significant 4 bits (nibbles) are all "0". That is, an output value of "0" is output for one second every four square seconds of two (16 seconds). The signal output in this manner is referred to as a time setting clock signal, and is also referred to as a 16 second clock signal in the embodiment of the present invention.

The D flip-flop 24 receives the system clock signal and the time setting clock signal of the base station itself, and then outputs them in synchronization with the time setting clock signal and the system clock signal. That is, in order to synchronize the 16 second clock signal, which is a time setting clock signal output from the OR logic element 23, with the system clock signal of the base station itself, the 16 second clock signal is output on the falling edge of the system clock signal. Let's do it. In an embodiment of the present invention, a system clock signal is set to 60 MHz which is commonly used by a base station.

On the other hand, the clock generator 30 receives the respective clock signals and time information output from the GPS receiver 20 having the structure as described above, the sampling clock signal, the frame clock signal and the frame counter signal used in the base station Create The clock signals are output together with the system clock signal and the 1 PPS clock signal to predetermined components of a base station (not shown).

3 is a timing diagram of signals according to an embodiment of the present invention. In detail, the clock waveform generated by adjusting the clock duty of the generated 16 second clock signal, the time setting clock signal, the 1 PPS clock signal output from the PS receiver, and the system clock signal of 60 MHz is shown.

The 16 second clock signal is periodically repeated every 16 seconds. The time interval of "0" is 100 nsec corresponding to 6 clock cycles of the 60 MHz system clock signal, and the 1 PPS clock signal is periodically cycled every second. Repeated and the time interval of "0" is likewise 100 nsec. At this time, the 16 second clock signal, the 1 PPS clock signal and the 60 MHz system clock signal are all synchronized to the falling edge.

Since the 60 MHz system clock signal and the 1 PPS clock signal shown in FIG. 3 are generally the same signals as the clock signals used in the base station, they are used without modification.

4 is a detailed structural diagram of a clock generator of a base station clock board according to an exemplary embodiment of the present invention. As shown in FIG. 4, the clock generator 30 includes a sampling clock divider 31, a frame clock divider 32, and a frame counter generator 33.

The sampling clock divider 31 receives the 1 PPS clock signal and the 60 MHz system clock signal synchronized to the falling edge shown in FIG. 3, divides, divides, and divides the synchronized 60 MHz system clock signal in the base station. Generate the 10 MHz sampling clock signal used. The 10 MHz sampling clock signal is output in synchronization with the 1 PPS clock signal.

In addition, the frame clock divider 32 receives a 1 PPS clock signal and a 60 MHz system clock signal synchronized to a falling edge shown in FIG. 3, and divides the synchronized 60 MHz system clock signal to be used for a base station. Generate a 5msec frame clock signal. The 5msec frame clock signal is output in synchronization with the 1 PPS clock signal.

The frame counter generator 33 receives the 16 second clock signal, the 10 MHz sampling clock signal, and the 5 msec frame clock signal generated by the GPS receiver, synchronizes the respective clock signals with the 16 second clock signal, The period of each bit is one period of the 10 MHz sampling clock signal, and a frame counter signal is generated and output periodically increasing from 0 to 3199 by 1 for each of the 5 msec frame clock signals.

5 is a timing diagram between clock signals finally output from the frame counter signal generating apparatus according to an embodiment of the present invention. All clock signals output from the frame counter signal generating apparatus according to an embodiment of the present invention are synchronized with the falling edge of the 60 MHz system clock signal.

The 1 PPS clock signal is repeatedly repeated as a low-level signal for 100 nsec, which corresponds to 6 cycles of a 60 MHz system clock every second.

The 5msec frame clock signal is also repeated with a low level signal for 100nsec, synchronized to the falling edge of the 60MHz system clock signal.

The 10 MHz sampling clock signal is repeated continuously with the falling edge signal in a period of 100 nsec.

The frame counter signal is synchronized with the falling edge of the 5msec frame clock signal, and signals corresponding to a total of 13 bits including the sync signal bits for indicating the starting point are repeated. Here, the content of the frame clock signal is changed repeatedly from 0 to 3199, which is a time corresponding to 16 seconds.

According to this embodiment, each base station generates a frame counter signal based on the absolute time information provided by the GPS satellites, so that the frame counter signal between each base station is synchronized.

Meanwhile, in the above-described embodiment, the frequencies of the signals are exemplified and are not necessarily limited to those described above.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to an embodiment of the present invention, by generating a time setting clock signal generated using GPS absolute time information and generating a frame counter signal based thereon, the frame counter signals output from all base stations are synchronized with each other.

Therefore, each base station and terminals connected to the base station can distinguish the exact order of the frames transmitted based on the frame counter signal. Accordingly, efficient hand-over can be performed.

Claims (8)

In an apparatus for receiving, at a mobile communication base station, time information provided from a GPS satellite and generating a frame counter signal, A GPS receiver for receiving the time information and generating a time setting clock signal synchronized with the system clock signal of the base station based on the time information; And A clock generation unit synchronized with the time setting clock signal and generating a frame counter signal having a same value as a sampling clock signal having a predetermined frequency and increasing a predetermined value for each predetermined frame clock signal; Frame counter signal generation device comprising a. The method of claim 1 The GPS receiver, The time information is serial data, and a serial / parallel converter for converting time information of the serial data into parallel data; A register for storing time information converted into the parallel data; A logic element for performing a logical operation on a predetermined bit of time information stored in the register and outputting a corresponding operation value; And A flip-flop for outputting the operation value output from the logic element as the time setting clock signal in synchronization with the system clock signal Frame counter signal generating device comprising a. The method of claim 2 And the logic element comprises an OR logic element that performs an OR operation on the lowest predetermined bit of the time information. The method according to any one of claims 1 to 3 The clock generator, The sampling clock signal is divided to generate the sampling clock signal of the predetermined frequency, and the sampling clock is synchronized with a predetermined time point of one pulse per second (PPS) clock signal which is synchronized with the system clock signal and generates one pulse per second. A sampling clock divider outputting a signal; A frame clock divider which divides the system clock signal to generate the frame clock signal, and outputs the frame clock signal in synchronization with a predetermined time point of the one PPS clock signal; And A frame counter generator for generating and outputting a frame counter signal that is synchronized with a predetermined time point of the time setting clock signal and whose period of each bit is the same as that of the sampling clock signal and increases by one according to the frame clock signal Frame counter signal generation device comprising a. The method according to any one of claims 1 to 3 The frame counter signal is a serial signal consisting of a plurality of bits including a sync signal bit, the value of the frame counter signal generating apparatus characterized in that the value is repeatedly changed from 0 to a set number. The method of claim 5, And the sync signal bit indicates a start point of the frame counter signal at a predetermined time point of the frame clock signal. In the mobile communication base station, in the frame counter signal generation method of the device for processing time information provided from the GPS satellite based on the system clock signal of the base station, Receiving time information of serial data and a 1 PPS clock signal from the GPS satellites; Converting time information of the serial data into parallel data; Logic operation of a predetermined bit of the converted parallel data to generate an operation value, and outputting the operation value as a time setting clock signal in synchronization with the system clock signal; Dividing the system clock signal to generate a sampling clock signal and a frame clock signal of a predetermined frequency, respectively; And Generating and outputting a frame counter signal in synchronization with a predetermined time point of the time setting clock signal, the period of each bit being equal to the period of the sampling clock signal, and increasing by a predetermined value according to the frame clock signal; Frame counter signal generation method comprising a. The method of claim 7, wherein The one PPS clock signal is synchronized with the system clock signal, and the sampling clock signal and the frame clock signal are output in synchronization with a predetermined time point of the one PPS clock signal.

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