KR100701702B1 - Device for precharging data line - Google Patents

Abstract

A data transfer device is provided to improve accuracy in data transfer by removing a precharging PMOS(Positive Metal Oxide Semiconductor) transistor from a VBLP precharging scheme. A data transfer device delivers data to and from a DRAM(Dynamic RAM) and includes a segment IO/IOB line pair(sio,siob), a local IO/IOB line pair(lio,liob), a switching element, and a precharge unit. The switching element is arranged between the IO/IOB line pair and the local IO/IOB line pair and changes the connection state between the IO/IOB line pair and the local IO/IOB line pair, so that the data transfer device is turned on when the DRAM is activated and turned off when the DRAM is precharged. The precharge unit is connected between the IO/IOB line pair and the local IO/IOB line pair. When the switching element is turned off, the precharge unit supplies a bit line precharge voltage for precharging the segment IO/IOB line pair corresponding to a local IO reset signal from the outside.

Description

Device for precharging data line

1 is a conceptual diagram of a bank configuration of a conventional DRAM and a local lio precharge circuit;

2 is a conceptual diagram illustrating a data transfer path of a conventional DRAM;

3 is a circuit diagram of a local Io precharge of FIG.

4 is a circuit diagram of a data transfer device (IOSW) of FIG.

5 is a timing diagram for describing an operation of the data transfer device of FIG. 4;

6 is a circuit diagram of a data transfer device according to an embodiment of the present invention;

7 is a circuit diagram of a data transfer device according to another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device, and more particularly, a data transfer device that increases cell eficiency of a DRAM and decreases accuracy of signal transfer through a data line by reducing an area of a data line precharge circuit. It is about.

Generally, DRAM is a device whose basic operation is to write and read data. Externally input data is written in the form of electrical signals (HIGH, LOW) to a cell, which is a storage location, through a certain data line, and can be read through the opposite path when the data is stored. have.

Here, the data line refers to a path to a cell in performing a read and write operation, and includes a BL (bit line), sio (segment IO), loi (local IL), and gio (global IO). do. Typically, BL means a data line from a cell to a bit line sense amp (BLSA), sio means a data line from a switch called Yi transistor in BLSA to IOSW (IOSW), which is a transfer device, and lio The data line from the IOSW to the IO sense amp (IOSA), which is the amplifying device, refers to the data line from the IOSA to the external pin.

On the other hand, data is transmitted through data lines to read and write data to a designated cell, and a precharge concept is required to efficiently read and write data to all cell arrays through a certain number of data lines. . In other words, it is efficient to reset the potential of the data line to a certain level in the meantime because one data is passed through the data line and then another data is passed through the same data line. It's a charge.

The precharge can be classified according to the potential of the data line to be reset. When the potential of the data line to be reset is a high data potential stored in the cell, it is called a VCORE precharge scheme. When the potential is half of the high data potential stored in the cell, it is referred to as a VBLP precharge scheme. Therefore, the VBLP potential is half of VCORE.

Hereinafter, a conventional data line precharge circuit and a data line transfer device will be described.

1 is a conceptual diagram of a bank configuration of a conventional DRAM and a local lio precharge circuit. Referring to FIG. 1, one bank is composed of several mats, and a sio line and a lio line are disposed between the mats. The precharge circuit is generally located at the point A (hereinafter, referred to as a data line transmission device (IOSW: IO switch)) where the sio line and the lio line meet and the ends B and C of the lio line. In this case, the matte refers to a cell array.

2 is a conceptual diagram illustrating a data transfer path of a conventional DRAM. Referring to FIG. 2, a path through which data is transmitted from a cell to a lio line in the read operation will be described. When a word line transitions to HIGH, a high potential is applied to a gate connected to the word line, and the cell transistor is turned on by the high potential applied to the gate. on) so that the data of the cell is loaded on the bit line bl. The bit line sense amp (BLSA) is connected to a bl line blb (paired with bl) where bl and no data are loaded, and amplifies the bl and blb signals.

The amplified signal is transferred to the sio line when the Yi switch selected by the column address is turned on. The amplified signal transmitted to the sio line is transferred to lio through a data line transmission device (IOSW).

3 is a circuit diagram of a local Io precharge of FIG. 1. Referring to FIG. 3, the local IO precharge circuit operates by the lio_rstb signal. The lio_rstb signal is a signal that transitions to a low level when the lio line is precharged. When the lio_rstb signal is low, the VBLP potential is transferred to lio / liob, and an equalizing operation is performed by a transistor between lio and liob.

4 is a circuit diagram of the data transfer device IOSW of FIG. 2. As shown in FIG. 4, the data transfer device receives an isow signal and connects or disconnects the sio / siob line and the lio / liob line to each other, and the source of the nMOS transistors n40 and n41 and the nMOS transistors n40 and n41. PMOS transistors (p40, p41) connected to the drain and the lio_rstb signal to precharge the sio / siob line and the lio / liob line, and an nMOS transistor to precharge the sio / siob line to the VBLP upon receiving the bleq signal. n42, n43, n44).

That is, the data transfer device connects the sio / siob line and the lio / liob line to each other when the iosw signal becomes high when the DRAM is active, and the iosw signal transitions to low when the precharge is performed. Separate the / siob and lio / liob lines.

Hereinafter, the operation of the data transfer device IOSW will be described in more detail with reference to the basic operation of the DRAM.

FIG. 5 is a timing diagram illustrating the operation of the data transfer device of FIG. 4. Each of the inputs to the data transfer device during the basic operation of the DRAM, such as ACT (active), WT (write), RD (read), and PCG (precharge). The changing state of the signals is shown.

When the ACT (active) command comes in first, the word line is turned on. Before the word line is turned on, the bleq signal transitions from high to low, leaving the data transfer device out of the precharge state. In addition, when the ACT command comes in, the iosw signal transitions from low to high to connect the sio / siob line with the lio / liob line.

When the PCG command is input, the word line WL is turned off to perform the precharge operation, and the bleq is shifted to the high level so that the data transfer device performs the precharge operation. In addition, when the PCG command comes in, the iosw signal transitions from high to low to separate the sio / siob line and the lio / liob line. That is, the word line, bleq signal, and iosw signal change depending on the ACT command and the PCG command, but they do not respond to the WT (write) and RD (read) commands.

On the other hand, the lio_rstb signal does not respond to the ACT command and the PCG command, but changes according to the WT command and the RD command. That is, if the lio_rstb signal is not a read or write operation, the lio / liob is precharged by maintaining a low state, and when the ACT or WT command is input, the lio_rstb signal may be read and written. Make sure When the DRAM adopts the lio line VBLP precharge scheme, the waveform of the signal carried in lio / liob is shown in FIG. 5.

The conventional data transfer device (IOSW) performs a precharge operation efficiently in the lio line VCORE precharge scheme, but is less efficient in the lio line VBLP precharge scheme described above. This is explained in more detail.

As shown in FIG. 5, when the ACT command is input, the iosw signal becomes HIGH and remains high until the PCG command is input. The bleq signal, on the other hand, goes low when the ACT command comes in and remains low until the PCG command comes in. That is, when an ACT command is received, the data transfer device (IOSW) connects the lio / liob line and the sio / siob line with each other by the iosw signal and maintains the connection state until the PCG command is received.

On the other hand, the bleq signal transitions low when the ACT command comes in and remains low until the PCG command comes in. This is an nMOS transistor constituting the precharge circuit receiving the bleq signal from the data transfer device (IOSW). (N42, n43, n44 in Fig. 4) does not operate. In other words, the operation of precharging the lio / liob line and the sio / siob line to transmit data according to the read / write command after the ACT command is input is performed by the liob_rstb signal. Accordingly, it can be seen that the conventional data transfer device includes unnecessary precharge pMOS transistors and unnecessary bleq signals.

These unnecessary circuits and signals can be a problem when the density of DRAMs increases as today. For example, as the density of DRAM increases, it becomes more difficult to arrange circuits in the sub-hole area where the data transfer device (IOSW) is located. Unnecessary circuits in the sub-hole area and unnecessary signals to drive them Dedicated lines for these are major losses in DRAM design and fabrication.

In addition, unnecessary transistors connected to the lio and sio lines have an unnecessary junction cap on the data line that transfers data by charge sharing during read operation, which adversely affects data transformation. There is a problem giving.

The present invention has been made to solve the problem of adversely affecting area issues and data transfer, including a circuit in which the data transfer device is unnecessary in the lio line VBLP precharge scheme. It is an object of the present invention to provide a data transfer device from which a signal is removed.

In order to achieve the above object, the data transfer device of the present invention is a data transfer device for switching a segment Io / Ioba line pair and a local I / Io line pair, the segment I / I in accordance with a switching signal input from the outside Switching means for switching an over line pair and the local Iowa line pair; And supplying a bit line precharge potential (VBLP) to the segment Io / Iova line pair and the local Io / Iova line pair according to a local Io reset signal input from the outside. And precharge means for precharging the local Iowa line pair.

The switching means may include a first transistor positioned between the segment io line and the local io line, and a second transistor positioned between the segment iobar line and the local io line. Preferably, the switching signal is input to a gate of a transistor and the second transistor.

In addition, the precharge means may include a third transistor having a source connected to the segment io line and a bit line precharge potential VBLP supplied to a drain, and a source connected to the segment iobar line and the bit line connected to a drain. And a fourth transistor to which a precharge potential is supplied, wherein the local IoReset signal is input to the gates of the third transistor and the fourth transistor.

The precharge means may further include equalizing means for making an electric potential of the segment io line and the segment iobar line to an equipotential according to the local iolet reset signal, wherein the equalizing means has a drain connected to the segment io line. And a source is a fifth transistor connected to the segment iobar line, and the local iolet reset signal is input to the gate of the fifth transistor.

The first to fifth transistors are preferably NMOS transistors.

In addition, in order to achieve the above object, the data transmission device of the present invention is a data transmission device for switching a segment Io / Ioba line pair and a local Io / Iova line pair, the segment I / / in accordance with a switching signal input from the outside Switching means for switching an iobar line pair and the local io / ioba line pair; And supplying a bit line precharge potential (VBLP) to the segment Io / Iova line pair and the local Io / Iova line pair according to a local Io reset bar signal input from the outside. And precharge means for precharging the local Iowa line pair.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

6 is a circuit diagram of a data transfer device according to an embodiment of the present invention. As shown in FIG. 6, the data transfer device according to the exemplary embodiment of the present invention includes a switching means and a precharge means, and inputs and outputs data by switching segment I / O line pairs and local I / I line pairs. To pass. Here, one end of the local Io / Iova line pair, which is not connected to the data transfer device, is preferably connected to the cell array external data line precharge circuit, for example the precharge circuit shown in FIG.

The switching means includes an nMOS transistor n60 positioned between the segment io line and the local lio line, and an nMOS transistor positioned between the segment iob line and the local iob line. n61). The nMOS transistors n60 and n61 switch segment io / ioba line pairs and local io / ioba line pairs when a switching signal is applied to the gate.

Here, the switching signal becomes HIGH when the DRAM is active to connect the segment io / iob line pair and the local lio / iob line pair to each other, When charged, the signal transitions to low to separate the segment io / siob line pair and the local lio / iob line pair. In the present embodiment, an iosw signal applied to the gates of the nMOS transistors n70 and n71 is illustrated as a switching signal.

The precharge means includes an nMOS transistor n63 having a source connected to a segment io line and a bit line precharge potential VBLP supplied to a drain, and a source connected to a segment iobar line and connected to a drain. NMOS transistor n64 to which a bit line precharge potential is supplied.

The nMOS transistors n63 and n64 have a segment io / siob line pair and a local lio / iodb line pair when a high local IO reset signal is input to the gate. The bit line precharge potential VBLP is supplied to precharge the segment io / siob line pair and the local lio / iob line pair. The bit line precharge potential is preferably 1/2 of the VCORE potential (data level potential of the cell).

The precharge means may further include an equalizing means for making an electric potential of the segment io line and the segment iobar line in equipotential according to the local io reset signal.

The equalizing means may include an nMOS transistor n62 having a drain connected to a segment io line, a source connected to a segment iobar line, and a local io reset signal applied to a gate.

That is, the data transfer device according to an embodiment of the present invention removes the pMOSs p40 and p41 for equalizing the conventional data transfer device (see FIG. 4), and is responsible for charging and equalizing. By having a structure in which the lio_rst signal is input to the gate of the nMOS (n42, n43, n44) instead of the bleq signal, unnecessary circuits and unnecessary signals are removed in the lio line VBLP precharge scheme. Junction caps removed by the circuits are eliminated, which can solve the conventional problem of adversely affecting data transformation. In particular, the removal of the junction cap increases the accuracy of data transmission by increasing ΔV between pairs of data lines due to charge sharing during a read operation. ΔV is a sensing margin voltage.

The following describes the operation of the data transfer device according to an embodiment of the present invention.

First, before the DRAM is active, the iosw signal remains low such that the nMOS transistors n60 and n61 of the data transfer device are turned off and thus segmented io / iobar line pairs. And the local lio / liob line pair are separated from each other.

At this time, the precharge circuit outside the cell array receives the lio_rstb signal and precharges the local io / iob line to the VBLP potential, and is located on the segment io / siob line. The nMOS transistors n62, n63, and n64 receive the lio_rst signal and precharge the segment io / sio line to the VBLP potential.

Next, when the active command comes in and the iosw signal goes high, the nMOS transistors n60 and n61 of the data transfer device are turned on, thus the segment io / ioba line pair and the local io ( The lio / liob line pairs are connected to each other.

Then, when a read or write operation is performed and a read or write operation is performed, the data transfer device and the external data line precharge circuit are stopped by the lio_rst signal and the lio_rstb signal, and the data transfer device uses the segment Io ( sio / siob line pairs and local lio / liob line pairs transmit and receive data. Once the data transfer is complete, the io / siob line pair and the local lio / iob line pair can be precharged again before the next data comes in and the above described operation can be repeated. .

That is, the data transfer device according to an embodiment of the present invention performs the precharge function by operating the nMOS transistors n62, n63, and n64 with lio_rst signals instead of the conventional bleq signals. Although the nMOS transistors n62, n63, and n64 have not previously performed a precharge function, in an embodiment of the present invention, the data transfer device receiving the lio_rst signal plays a precharge role and is also a precharge outside the cell array. The circuitry helps to precharge the local line within a set amount of time, ensuring correct delivery of data continuously in read or write.

7 is a circuit diagram of a data transfer device according to another embodiment of the present invention. As shown in FIG. 7, the data transfer device according to another embodiment of the present invention includes a switching means and a precharge means, as in the data transfer device described with reference to FIG. 6, and includes a segment io / ioba line pair and a local io / eye. Transmits input and output data by switching over line pairs.

In this case, the configuration of the switching means and the structure of the local I / O line pair connected to the cell array external data line precharge circuit are the same as the configuration of the data delivery circuit described with reference to FIG.

The precharge means includes a pMOS transistor p71 having a source connected to a segment io line and a bit line precharge potential VBLP supplied to a drain, and a source connected to a segment iobar line and connected to a drain. PMOS transistor (n72) to which bit line precharge potential is supplied, drain is connected to segment io line, source is connected to segment iobar line, and pMOS transistor (n70) to which local io reset signal is applied to the gate It is configured to include).

That is, unlike the precharge means described with reference to FIG. 6, the precharge means of the data transfer device according to another embodiment of the present invention is configured using pMOS transistors n70, n71, and n72, so that the local IR reset signal is substituted. Therefore, it has a structure that operates by receiving a local IR reset bar signal which is low.

A data transfer device according to another embodiment of the present invention also removes the equalizing pMOS (p40, p41) of the conventional data transfer device (see Figure 4), and is responsible for charging and equalizing (equalizing) Since the bleq signal applied to the gates of the nMOSs n42, n43, and n44 is removed, the same effect as that of the data transfer apparatus described with reference to FIG. 6 is obtained.

As described above, the data transfer device of the present invention eliminates unnecessary precharge pMOS transistors in a conventional lio line VBLP precharge scheme, and uses a signal such as lio_rst instead of a bleq signal to provide cell eficiency. ) To solve the conventional area issue and to improve the accuracy of data transfer.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (12)

In the data transfer device for transferring data of the DRAM (DRAM), Segment io / ioba line pair; Local io / ioba line pairs; The Io line is configured between the Io / Iova line pair and the local Io / Iova line pair, and is turned on in response to the active of the DRAM by the externally input switching signal and turned off in response to the precharge. Switching means for switching a connection state between the local Iowa line and a connection state between the Iova line and the local Iova line; The bit line precharge voltage for precharging the segment I / O line pairs is connected between the segment I / O line and the segment I / O line pair when the switching means is turned off. Precharge means for supplying; Data transmission device comprising a. The method of claim 1, wherein the switching means, A first transistor located between the segment io line and the local io line, and a second transistor located between the segment iobar line and the local io line; And the switching signal is input to the gates of the first transistor and the second transistor. The method of claim 2, The first transistor and the second transistor are NMOS transistors Data transfer device. The method of claim 1, wherein the precharge means A third transistor having a source connected to the segment Io line and supplied with the bit line precharge potential VBLP to a drain; A source is connected to said segment iobar line and includes a fourth transistor to which said bit line precharge potential is supplied to a drain; The local IoReset signal is input to the gates of the third and fourth transistors. Data transfer device. The method of claim 4, wherein The third transistor and the fourth transistor are NMOS transistors Data transfer device. The method of claim 1, wherein the precharge means Equalizing means for equalizing the potential of the segment Io line and the segment Iova line in accordance with the local Io reset signal; Data transfer device. 7. The apparatus of claim 6, wherein the equalizing means is A drain is connected to the segment io line and a source is connected to the segment iobar line and is a fifth transistor, and the local io reset signal is input to the gate of the fifth transistor. Data transfer device. The method of claim 7, wherein The fifth transistor is an NMOS transistor. Data transfer device. In the data transfer device for transferring data of the DRAM (DRAM), Segment io / ioba line pair; Local io / ioba line pairs; The Io line is configured between the Io / Iova line pair and the local Io / Iova line pair, and is turned on in response to the active of the DRAM by the externally input switching signal and turned off in response to the precharge. Switching means for switching a connection state between the local Iowa line and a connection state between the Iova line and the local Iova line; Bit line precharge voltage for precharging the segment I / O line pairs by a local I O reset bar signal, which is connected between the segment I / O line and the segment Iova line and the switching means is turned off. Precharge means for supplying; Data transmission device comprising a. The method of claim 9, wherein the precharge means Equalizing means for equalizing the potential of the segment Io line and the segment Iova line in accordance with the local Io reset bar signal; Data transfer device. The method of claim 10, The precharge means may include a sixth transistor having a source connected to the segment Io line and a bit line precharge potential VBLP supplied to a drain, and a source connected to the segment Iova line, and the bit line free to a drain. A seventh transistor to which a charge potential is supplied, The equalizing means is an eighth transistor having a drain connected to the segment Io line and a source connected to the segment Io line, The local IOS reset bar signal is input to the gates of the sixth to eighth transistors. Data transfer device. The method of claim 11, The sixth to eighth transistors are PMOS transistors. Data transfer device.

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