KR100699683B1 - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device Download PDF

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Publication number
KR100699683B1
KR100699683B1 KR1020050131201A KR20050131201A KR100699683B1 KR 100699683 B1 KR100699683 B1 KR 100699683B1 KR 1020050131201 A KR1020050131201 A KR 1020050131201A KR 20050131201 A KR20050131201 A KR 20050131201A KR 100699683 B1 KR100699683 B1 KR 100699683B1
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KR
South Korea
Prior art keywords
gate electrode
polysilicon layer
plasma etching
forming
semiconductor device
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Application number
KR1020050131201A
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Korean (ko)
Inventor
안효상
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동부일렉트로닉스 주식회사
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Priority to KR1020050131201A priority Critical patent/KR100699683B1/en
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Publication of KR100699683B1 publication Critical patent/KR100699683B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to form easily a gate electrode of diverse shape by controlling the rate of SF6 and C4F8 gases and to prevent side attack by using SF6, C4F8 and O2 gases. An oxide layer(110) and a polysilicon layer(120) are sequentially stacked on a substrate(100). A photoresist pattern(130) is coated on the polysilicon layer to form a gate electrode. A plasma etching process is then performed by using the photoresist pattern as a mask and using mixed gases of SF6, C4F8 and O2. At this time, by controlling the gas rate of SF6 and C4F8, the gate electrode of diverse shape is formed. The gas rate of SF6 and C4F8 is 1:1 to 1:2.

Description

TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device,

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A and FIG. 1B illustrate a method of manufacturing a semiconductor device according to a first embodiment of the present invention;

2A and 2B illustrate a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

3A to 3C are diagrams illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

4A and 4B illustrate a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

Description of the Related Art

100: semiconductor substrate 110: oxide film 120: polysilicon layer

130: Photoresist

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of realizing various critical dimensions (CDs) according to characteristics of semiconductor devices.

BACKGROUND ART [0002] With recent high integration of semiconductor devices, there is a growing demand for processing technology for film formation used in the manufacture of semiconductor devices. This is because various films including an insulating film, a conductive film, and the like are formed in a multilayer structure and a structure having a fine pattern of a design rule of 0.1 m or less is formed.

In general, a MOS transistor is a type of field effect transistor (FET), and has a structure in which a gate oxide film and a gate are formed on a semiconductor substrate on which a source / drain region and a source / drain region formed on a semiconductor substrate are formed .

In the MOS transistor structure, a metal wiring for applying an electrical signal is connected to the source, the drain, and the gate, respectively, to operate the element.

In this MOS transistor fabrication process, a gate oxide film and a polysilicon film of a predetermined width are laminated on the surface of an active region of a silicon wafer and patterned to form a gate electrode.

Then, LDD (Lightly Doped Drain) is formed on the silicon wafer in the device region by implanting a P-type or N-type dopant at a low concentration into the silicon wafer in the device region using the gate electrode as a doping mask.

After sidewalls are formed on both side walls of the gate electrode, a dopant of the same conductivity type as that of LDD is ion-implanted into the silicon wafer in the device region at a high concentration using sidewalls and polysilicon as a doping mask, Source / drain is formed in the silicon wafer in the element region.

As the degree of integration of the semiconductor device is improved, the line width of the circuit becomes narrower, and accordingly, the size of the gate becomes smaller, and so-called nano gate is emerging.

In the conventional method of manufacturing a semiconductor device, it is impossible to realize a gate having a small size such as a nanogate due to the limitation of a photolithography process for forming a gate.

It is an object of the present invention to propose a method of fabricating a semiconductor device capable of simultaneously forming a gate electrode of various shapes by isotropic etching and lateral protection of an etched portion.

Another object of the present invention is to propose a semiconductor device manufacturing method capable of increasing the reliability of semiconductor devices by forming gate electrodes of various shapes according to characteristics of semiconductor devices.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, including: providing a semiconductor substrate and an oxide layer and a polysilicon layer sequentially formed on the semiconductor substrate, Applying the photo-resist to the substrate; And performing a plasma etching using the photoresist as an etching mask, wherein the plasma etching process is performed in a ratio of SF 6 and C 4 F 8 in a range of 1: 1 to 1: 2, By adjusting the ratio of SF 6 and C 4 F 8 , gate electrodes of different shapes are produced.

A method of fabricating a semiconductor device according to another embodiment of the present invention includes sequentially forming an oxide layer and a polysilicon layer on a semiconductor substrate; Forming a patterned photoresist over the polysilicon layer; And performing a plasma etching using the photoresist as an etching mask to form a gate electrode, wherein SF 6 and C 4 F 8 are used in the plasma etching process, and SF 6 and C 4 F < 8 > is changed so that gate electrodes of different shapes are produced.

According to the method for fabricating a semiconductor device as described above, isotropic etching and lateral protection of an etched portion can be performed at the same time, and gate electrodes having various shapes can be formed.

In addition, by forming gate electrodes having various shapes according to characteristics of semiconductor devices, it is possible to increase the reliability of semiconductor devices.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood, however, that there is no intention to limit the scope of the invention to the particular embodiments disclosed, and that those skilled in the art, upon reading and understanding the spirit of the invention, .

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The same reference numerals are used for similar parts throughout the specification. Whenever a portion of a layer, film, region, or plate is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between.

In various embodiments of the present invention, SF 6 and C 4 F 8 gases are used to protect the side of the etched portion with isotropic etching.

In particular, SF 6 is used as a material for isotropic etching by a fluorine radical, and C 4 F 8 forms a compound of (C x F y) n composition so that it can act as a protective film for protecting the side.

Further, by additionally forming the O 2 compound has high strength in accordance with the addition of O 2, it will exhibit an even greater effect in terms of protection.

1A and 1B are views illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

First, referring to FIG. 1A, an oxide film 110 and a polysilicon layer 120 are sequentially stacked on a semiconductor substrate 100.

A patterned photoresist 130 for forming a gate electrode is formed on the polysilicon layer 120.

The polysilicon layer 120 may be deposited by a process such as CVD (Chemical Vapor Deposition), and the polysilicon layer 120 may be formed using a doped or undoped silicon layer, It can be doped to have a conductivity.

Referring now to FIG. 1B, plasma etching based on SF 6 / C 4 F 8 / O 2 gas is performed and is performed under conditions that the sides of the etched portions can be protected with isotropic etching.

In detail, the photoresist 130 is used as an etching mask under the condition that the ratio of SF 6 and C 4 F 8 is maintained at 1: 2 and 10 sccm of O 2 is applied. In this process, It does not.

Thus, a gate electrode having the same line width as the photoresist 130 can be obtained by a polymer side-surface protection film (not shown) having high strength.

2A and 2B are views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

2A, an oxide film 110 and a polysilicon layer 120 are sequentially stacked on a semiconductor substrate 100, as described above.

Then, a patterned photoresist 130 for forming a gate electrode is applied on the polysilicon layer 120.

Next, referring to FIG. 2B, plasma etching according to an embodiment of the present invention is performed using the photoresist 130 as an etching mask.

Specifically, SF 5 is performed under the condition that the ratio of SF 6 and C 4 F 8 is 1: 1.5 while O 2 is applied at 5 sccm. Isotropic etching is performed by SF 6 and C 4 F 8 , (Not shown).

As shown in the figure, as compared with the first embodiment, a smaller amount of O 2 is used to reduce the line width as compared with the photoresist 130, and the line width can be adjusted according to the process conditions .

In addition, the generation of the polymer by C 4 F 8 makes it possible to obtain a gate electrode having a vertical shape.

3A to 3C are views for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

Referring to FIG. 3A, an oxide film 110 and a polysilicon layer 120 are sequentially stacked on a semiconductor substrate 100, as described above.

Then, a patterned photoresist 130 for forming a gate electrode is applied on the polysilicon layer 120.

Referring to FIG. 3B, a portion of the photoresist 130 is removed to have a line width smaller than the line width of the photoresist 130, thereby reducing the line width.

Referring to FIG. 3C, plasma etching according to an embodiment of the present invention is performed using the photoresist 130a as an etching mask.

In detail, the polysilicon layer 120 and the oxide film 110 are etched while changing the ratio of SF 6 and C 4 F 8 from 1: 2 to 1: 1.5. That is, a change in the flow rate of SF 6 and C 4 F 8 is performed during a plasma etching process for forming a gate. And, O 2 can be applied at 10 sccm.

The shape of the gate electrode to be manufactured may vary with the passage of time when the ratio of SF 6 to C 4 F 8 is changed.

Accordingly, as shown in the figure, a gate electrode having a smaller line width from the lower part to the upper part is formed, which can be used for a semiconductor device for improving a short channel effect.

4A and 4B are views illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

Referring to FIG. 4A, an oxide film 110 and a polysilicon layer 120 are sequentially stacked on a semiconductor substrate 100, as described above.

Then, a patterned photoresist 130 for forming a gate electrode is applied on the polysilicon layer 120.

Referring to FIG. 4B, a plasma etching according to an embodiment of the present invention is performed using the photoresist 130 as an etching mask.

In detail, the polysilicon layer 120 and the oxide film 110 are etched while changing the ratio of SF 6 and C 4 F 8 from 1: 1 to 1: 2. That is, a change in the flow rate of SF 6 and C 4 F 8 is performed during a plasma etching process for forming a gate. And, O 2 can be applied at 5 sccm. The gate electrode may be formed to have a different shape according to the elapse of time when the ratio of SF 6 to C 4 F 8 is changed.

Accordingly, it is possible to obtain a gate electrode having a shape in which a lower line width is much smaller than that of the upper portion, and in particular, a gate electrode of 5 nm or less can be realized. Also in this embodiment, isotropic etching and lateral protection of the etched portion are performed by SF 6 and C 4 F 8 .

In the embodiment of the present invention, various shapes of gate electrodes can be formed by using the SF6, C4F8, and O2 to protect the isotropic etching and the sides, and by adjusting the ratio of SF6 and C4F8.

This allows the gate electrode to be formed in accordance with various characteristics of the semiconductor device, and it can be widely used such as MEMS (Micro-Electro-Mechanical System), FEDs (Field Emission Devices) and AFM (Atomic Force Microscope).

According to the method for fabricating a semiconductor device as described above, isotropic etching and lateral protection of an etched portion can be performed at the same time, and gate electrodes having various shapes can be formed.

In addition, by forming gate electrodes having various shapes according to characteristics of semiconductor devices, it is possible to increase the reliability of semiconductor devices.

Claims (5)

There is provided a semiconductor substrate and an oxide film and a polysilicon layer sequentially formed on the semiconductor substrate, Forming a patterned photoresist for forming a gate electrode on the polysilicon layer; And And performing plasma etching using the photoresist as an etching mask, The plasma etching process is performed so that SF 6 and C 4 F 8 are performed in a ratio in the range of 1: 1 to 1: 2, and that the gate electrodes of different shapes are produced by controlling the ratio of SF 6 and C 4 F 8 and, The SF 6 serves to perform isotropic etching during plasma etching, Wherein the C 4 F 8 serves to protect the side surface of the etched portion by forming a compound of (C x F y) n composition. delete The method according to claim 1, Wherein an O 2 gas is further used in the plasma etching process. Sequentially forming an oxide film and a polysilicon layer on a semiconductor substrate; Forming a patterned photoresist over the polysilicon layer; And And performing plasma etching using the photoresist as an etching mask to form a gate electrode, SF 6 and C 4 F 8 are used in the plasma etching process and the ratio of SF 6 and C 4 F 8 is changed during the etching process, Wherein a shape of a gate electrode to be manufactured is different according to the elapse of time in which the ratio of SF 6 to C 4 F 8 is changed in the plasma etching process. delete
KR1020050131201A 2005-12-28 2005-12-28 Method of fabricating semiconductor device KR100699683B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200050140A (en) * 2018-11-01 2020-05-11 한국기초과학지원연구원 Method for forming nanostructures using plasma

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980026094A (en) * 1996-10-07 1998-07-15 김광호 Pattern Formation Method
KR20020043961A (en) * 2000-12-05 2002-06-12 박종섭 Manufacturing method of fine pattern for a semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980026094A (en) * 1996-10-07 1998-07-15 김광호 Pattern Formation Method
KR20020043961A (en) * 2000-12-05 2002-06-12 박종섭 Manufacturing method of fine pattern for a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200050140A (en) * 2018-11-01 2020-05-11 한국기초과학지원연구원 Method for forming nanostructures using plasma
KR102297890B1 (en) 2018-11-01 2021-09-06 한국핵융합에너지연구원 Method for forming nanostructures using plasma

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