KR100696337B1 - Apparatus for multi-downloading DSP in BSC of mobile communication system - Google Patents

Abstract

According to the present invention, when a CPU in a control station downloads a program to a digital signal processor (DSP), the digital signal processor multi-controls at the control station of the mobile communication system to simultaneously download to a plurality of digital signal processors. BACKGROUND OF THE INVENTION The present invention relates to a downloading apparatus, wherein the present invention provides an output from the central processing unit and a central processing unit for generating an address and a control signal for down-loading a plurality of digital signal processors simultaneously and outputting data for down-loading. A multi-loading control unit that generates a chip select signal, a multi-downloading control signal, an input data strobe signal, and a buffer enable signal of a specific digital signal processor by combining the address and the control signal. Output from the CPU according to a buffer enable signal output from a loading controller A buffer for buffering data and transferring the data to the plurality of digital signal processors, a chip selection signal output from a multi-loading controller, a multi-downloading control signal, and an input data strobe signal to simultaneously output data output from the buffer to its internal memory. And a digital signal processor including the plurality of digital signal processors stored in the digital signal processor.

Mobile Communication System, Digital Signal Processor, Program Downloading, Multi-Downloading

Description

Applicator for multi-downloading DSP in BSC of mobile communication system             

1 is a schematic structural diagram of an apparatus for downloading a program to a digital signal processor in a control station of a conventional mobile communication system,

2 is a block diagram of a digital signal processor multi-downloading device in a control station of a mobile communication system according to the present invention;

FIG. 3 is a diagram illustrating an embodiment of the multi-loading controller of FIG. 2.

<Explanation of symbols for the main parts of the drawings>

100 ..... Central Processing Unit

200 ..... multi loading control

210 ..... decoder

220, 230 ..... First and second logical products

300 ..... Buffer

400 ..... Digital Signal Processing Unit

401 ~ 400 + N ..... Digital Signal Processor

The present invention relates to a digital signal processor (DSP) multi-downloading device in a control station (BSC) of a mobile communication system. In particular, the central processing unit (CPU) in the control station is a digital signal processor (DSP). The present invention relates to a digital signal processor multi-downloading device in a control station of a mobile communication system which downloads a plurality of digital signal processors simultaneously.

In general, a control station of a code division multiple access (CDMA) mobile communication system uses a digital signal processor (DSP) to control a vocoder board in charge of vocoding.

In a control station of such a general CDMA mobile communication system, an apparatus for downloading a program from a conventional central processing unit in a control station to a digital signal processor is as shown in FIG.

Here, reference numeral 10 denotes a central processing unit that controls data download by generating data, address, and control signals when the program is downloaded by the plurality of digital signal processors 41 to 40 + N in the digital signal processor 40. Reference numeral 20 denotes a decoder which decodes an address and control signal output from the CPU 10 to generate a chip select signal, a write strobe signal, a read strobe signal, and a read strobe signal of a status register. Denotes a buffer for buffering the data output from the CPU 10 and outputting the buffer to the digital signal processor 40, and reference numeral 40 denotes the buffer corresponding to each control signal output from the decoder 20. The digital device includes a plurality of digital signal processors 41 to 40 + N for recording and reading data output from the 30. It shows a signal processing unit.

The apparatus for downloading a program from the central processing unit in the conventional control station configured as described above to the digital signal processor firstly includes one digital signal processor (for example, 41) in the digital signal processing unit 40 in the central processing unit 10. When the program is downloaded to the CPU 10, the CPU 10 outputs a control signal and an address for controlling the corresponding digital signal processor to the decoder 20, and simultaneously buffers the program (data) to be downloaded. To send).

The decoder 20 combines an address and a control signal output from the CPU 10 to form a chip select signal Pcs (low active), a write strobe signal (Pids: low active), and a read strobe signal (Pods: low). Active), and generates a read strobe signal (Pstat: high active) of the status register, and transmits each generated signal to the digital signal processor # 1 (41) in the digital signal processor (40).

In addition, the buffer 30 buffers the input data and transfers the data to the digital signal processor # 1 (41), and the digital signal processor # 1 (41) receives data input to the data terminal according to each control signal input. This will read / write the program.

Next, even when downloading a program to another digital signal processor (for example, 40 + N), the digital signal processor 40+ is executed by the CPU 10 by performing the above-described downloading operation. N) will download the program.

In other words, when a program is downloaded to a plurality of digital signal processors in a digital signal processor in a central processing unit in a conventional control station, the program is downloaded by downloading a program to one digital signal processor at a time. Therefore, in case of 10 digital signal processors, the program can be downloaded to all the digital signal processors by performing 10 program download processes.

Therefore, the conventional method of downloading a program from the central processing unit in the control station to the digital signal processor has a disadvantage in that the more digital signal processors, the longer the program download time is.

This drawback consequently leads to a deterioration of the overall control station performance.

Accordingly, the present invention has been proposed in order to solve various problems that occur when downloading a program to a digital signal processor in the control station of the conventional mobile communication system,

An object of the present invention is to provide a digital signal at a control station of a mobile communication system that allows a central processing unit (CPU) in a control station to download a program to a digital signal processor (DSP) simultaneously. It is to provide a processor multi-downloading device.                         

The digital signal processor multi-downloading device in the control station of the mobile communication system according to the present invention for achieving the above object,

An apparatus for downloading a program to a plurality of digital signal processors in a digital signal processor in a central processing unit in a control station of a mobile communication system,

A central processing unit for generating an address and a control signal for simultaneously down-loading the plurality of digital signal processors and outputting data for down-loading;

Combining the address and control signal output from the central processing unit to generate a chip select signal, a multi-downloading control signal, an input data strobe signal, a buffer enable signal of a specific digital signal processor to control the multi-downloading A loading control section;

A buffer that buffers the data output from the CPU according to the buffer enable signal output from the multi-loading control unit and delivers the data to the plurality of digital signal processors;

A digital signal including the plurality of digital signal processors configured to simultaneously store data output from the buffer in its internal memory according to a chip select signal, a multi-downloading control signal, and an input data strobe signal output from the multi loading controller; Characterized in that it comprises a processing unit.

In the above, the multi loading control unit,

A decoder which combines an address and a control signal output from the central processing unit to generate a chip select signal, a multi-downloading control signal, an input data strobe signal, and a buffer enable signal of a specific digital signal processor;

A first logical element for multiplying the chip select signal output from the decoder and the multi-downloading control signal and outputting the resultant signal as a chip select signal;

And a second logical element which multiplies the input data strobe signal output from the decoder and the multi-downloading control signal and outputs the resultant signal as an input data recording signal.

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above.

2 is a block diagram of a digital signal processor multi-downloading apparatus in a control station of a mobile communication system according to the present invention.

), 멀티-다운로딩 제어신호(mul-cs

), 입력 데이터 스트로브 신호(mul-ids

), 버퍼 인에이블 신호(

)를 생성하여 멀티-다운로딩을 제어하는 멀티-로딩 제어부를 나타내고, 참조부호 300은 상기 멀티-로딩 제어부(200)에 서 출력되는 버퍼 인에이블 신호에 따라 상기 중앙처리장치(100)에서 출력되는 데이터를 버퍼링하여 상기 복수개의 디지털 신호 처리기로 전달해주는 버퍼를 나타내고, 참조부호 400은 상기 멀티 로딩 제어부(200)에서 출력되는 칩 선택 신호, 멀티-다운로딩 제어신호 및 입력 데이터 스트로브 신호에 따라 상기 버퍼(300)에서 출력되는 데이터를 동시에 자신의 내부 메모리에 저장하는 상기 복수개의 디지털 신호 처리기(401 ~ 400+N)를 포함하는 디지털 신호 처리부를 나타낸다.Here, reference numeral 100 denotes a central processing unit which generates an address Addr and a control signal Cntl for down-loading a plurality of digital signal processors at the same time and outputs data to be down-loaded. The 200 selects the chip selection signal Pics of the specific digital signal processor by combining the address and the control signal output from the CPU 100.

), Multi-downloading control signal (mul-cs

), Input data strobe signal (mul-ids

), Buffer enable signal (

) And a multi-loading control unit for controlling the multi-downloading, and the reference numeral 300 is output from the central processing unit 100 according to the buffer enable signal output from the multi-loading control unit 200. A buffer buffers data and transmits the data to the plurality of digital signal processors, and reference numeral 400 denotes the buffer according to a chip select signal, a multi-downloading control signal, and an input data strobe signal output from the multi loading controller 200. A digital signal processor including the plurality of digital signal processors 401 to 400 + N for simultaneously storing data output from 300 in its internal memory.

The operation of the digital signal processor multi-downloading apparatus in the control station of the mobile communication system according to the present invention configured as described above will be described in detail with reference to FIG.

First, the CPU 100 generates an address Addr and a control signal Cntl for simultaneously down-loading the plurality of digital signal processors 401 to 400 + N, and transmits the generated signals to the multi loading controller 200. Data to be downloaded and output is output to the buffer 300.

), 멀티-다운로딩 제어신호(mul-cs

), 입력 데이터 스트로브 신호(mul-ids

), 버퍼 인에이블 신호(

)를 생성하여 멀티-다운로딩을 제어하게 된다.The multi-loading control unit 200 combines an address and a control signal output from the CPU 100 to select a chip selection signal of a specific digital signal processor (Pics).

), Multi-downloading control signal (mul-cs

), Input data strobe signal (mul-ids

), Buffer enable signal (

) To control multi-downloading.

The operation of the multi loading controller 200 will be described in more detail as follows.

3 is a diagram illustrating an embodiment of the multi loading controller 200.

), 멀티-다운로딩 제어신호(mul

)(mul-

), 입력 데이터 스트로브 신호(

), 버퍼 인에이블 신호(

)를 생성하는 디코더(210)와; 상기 디코더(210)에서 출력되는 칩 선택 신호(

)와 멀티-다운로딩 제어신호(mul

)를 논리곱하여 그 결과 신호를 칩 선택 신호로 출력하는 제1논리곱소자(220)와; 상기 디코더(210)에서 출력되는 입력 데이터 스트로브 신호(

)와 상기 멀티-다운로딩 제어신호(mul-

)를 논리곱하여 그 결과 신호를 입력 데이터 기록신호로 출력하는 제2논리곱소자(230)로 구성된다.As shown in FIG. 2, the chip select signal of a specific digital signal processor may be combined by combining an address and a control signal output from the CPU 100.

), Multi-downloading control signal (mul

) (mul-

), Input data strobe signal (

), Buffer enable signal (

A decoder (210) for generating a); The chip select signal output from the decoder 210 (

) And multi-downloading control signals (mul

) And a first logical unit 220 for outputting the result signal as a chip select signal; The input data strobe signal output from the decoder 210 (

) And the multi-downloading control signal (mul-

) And a second logical product 230 for outputting the resultant signal as an input data recording signal.

), 입력 데이터 스트로브 신호(

), 출력 데이터 스트로브 신호(

), 버퍼 인에이블 신호(

)를 생성하게 된다. 여기서 생성되는 신호들은 중앙처리장치(100)가 각각의 디지털 신호 처리기(DSP)를 액세스할 때 필요한 신호들이다.The multi-loading control unit 200 configured as described above, first, by combining the address (Addr) and the control signal (Cntl) output from the central processing unit 100 in the decoder 210 (chip selection signal of the specific digital signal processor (

), Input data strobe signal (

), Output data strobe signal (

), Buffer enable signal (

Will be generated. The signals generated here are signals necessary for the CPU 100 to access each digital signal processor (DSP).

)(mul-

)를 발생한다. In addition, the decoder 210 is a multi-downloading control signal (mul) for multi-downloading

) (mul-

Will occur).

)와 멀티-다운로딩 제어신호(mul

)를 논리곱하여 그 결과 신호를 칩 선택 신호(pics

)로 출력하여 디지털 신호 처리부(400)로 전달한다.Next, the first logical product 220 is a chip select signal (output from the decoder 210)

) And multi-downloading control signals (mul

) And the result is the chip select signal (pics

And outputs the same to the digital signal processor 400.

)와 상기 멀티-다운로딩 제어신호(mul-

)를 논리곱하여 그 결과 신호를 입력 데이터 기록신호(pids

)로 출력하여 디지털 신호 처리부(400)로 전달한다.In addition, the second logical element 230 is an input data strobe signal output from the decoder 210 (

) And the multi-downloading control signal (mul-

) And the result signal is input data recording signal (pids

And outputs the same to the digital signal processor 400.

Meanwhile, when the buffer enable signal output from the decoder 210 is in a constant state, the buffer 300 buffers the input data to the digital signal processor 400, and accordingly, the digital signal processor 400. The plurality of digital signal processors 401 to 400 + N therein simultaneously write data to their boot ROM in response to an input control signal.

That is, when the central processing unit 100 downloads a program to the digital signal processors 401 to 400 + N, it selects a multi-address and downloads the program to all the digital signal processors, and accesses each digital signal processor. In this case, the address of the digital signal processor is selected and accessed.

)는 구현하지 않았다. Since the digital signal processor downloading is a recording operation for the central processing unit, simultaneous recording is possible, while the read operation of the digital signal processor cannot be simultaneously read.

) Is not implemented.

Once again, the operation of the CPU when downloading to the digital signal processor is briefly described as follows.

)(mul-

)를 로우로 어서트(Assert)하여 디지털 신호 처리기의 pi

신호와 pi

신호를 로우로 어서트하게 된다.Typically, digital signal processors have an internal memory for storing user programs therein. When the central processing unit 100 multi-downloads the digital signal processor, the central processing unit 100 selects the multi-loading address and records the corresponding program. Control signal (mul

) (mul-

) To low to pi the digital signal processor

Signal and pi

It will assert the signal low.

The boot ROM inside the digital signal processor then stores the data (user program) into its internal memory. Once all the user programs have been saved, the downloading operation will end.

According to the above-described "digital signal processor multi-downloading device in the control station of the mobile communication system" described above, since the central processing unit can download the user program to the plurality of digital signal processors at the same time, This has the advantage of improving the download performance of the digital signal processor.

Claims (2)

An apparatus for downloading a program to a plurality of digital signal processors in a digital signal processor in a central processing unit in a control station of a mobile communication system, A central processing unit for generating an address and a control signal for simultaneously down-loading the plurality of digital signal processors and outputting data for down-loading; Combining the address and control signal output from the central processing unit to generate a chip select signal, a multi-downloading control signal, an input data strobe signal, a buffer enable signal of a specific digital signal processor to control the multi-downloading A loading control section; A buffer that buffers the data output from the CPU according to the buffer enable signal output from the multi-loading control unit and delivers the data to the plurality of digital signal processors; A digital signal including the plurality of digital signal processors configured to simultaneously store data output from the buffer in its internal memory according to a chip select signal, a multi-downloading control signal, and an input data strobe signal output from the multi loading controller; A digital signal processor multi-downloading device in a control station of a mobile communication system, comprising a processing unit. The method of claim 1, wherein the multi loading control unit, A decoder which combines an address and a control signal output from the central processing unit to generate a chip select signal, a multi-downloading control signal, an input data strobe signal, and a buffer enable signal of a specific digital signal processor; A first logical element for multiplying the chip select signal output from the decoder and the multi-downloading control signal and outputting the resultant signal as a chip select signal; And a second logical element which multiplies the input data strobe signal output from the decoder and the multi-downloading control signal and outputs the resultant signal as an input data recording signal. Signal Processor Multi-Downloading Device.

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