KR100691099B1 - Method of forming silicide layer of semiconductor device - Google Patents

Method of forming silicide layer of semiconductor device Download PDF

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KR100691099B1
KR100691099B1 KR1020050133227A KR20050133227A KR100691099B1 KR 100691099 B1 KR100691099 B1 KR 100691099B1 KR 1020050133227 A KR1020050133227 A KR 1020050133227A KR 20050133227 A KR20050133227 A KR 20050133227A KR 100691099 B1 KR100691099 B1 KR 100691099B1
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wafer
sputtering equipment
film
thin film
metal thin
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KR1020050133227A
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Korean (ko)
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주성중
이한춘
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for forming a silicide layer in a semiconductor device is provided to effectively impurities and a native oxide layer while avoiding damage to a gate polysilicon and a surface of a substrate by performing an annealing process in an atmosphere of hydrogen and ammonia instead of a pre-cleaning process. Elements for a PAI(pre-amorphorized implant) process are ion-implanted into the front surface of a wafer. An annealing process is performed in an atmosphere of hydrogen and ammonia for a time interval of 10~60 minutes and at a temperature of 200~300 deg.C so as to eliminate impurities and a native oxide layer of the wafer from sputtering equipment. A metal thin film of cobalt for forming a silicide layer is deposited on the front surface of the wafer in the sputtering equipment. A barrier metal layer of titanium and titanium nitride is deposited on the front structure of the metal thin film in the sputtering equipment.

Description

반도체 소자의 실리사이드막 형성 방법{Method of Forming Silicide Layer of Semiconductor Device}Method of forming silicide layer of semiconductor device {Method of Forming Silicide Layer of Semiconductor Device}

도 1은 본 발명의 실시예에 따른 실리사이드막 형성 방법을 나타내는 흐름도.1 is a flow chart showing a silicide film forming method according to an embodiment of the present invention.

도 2a 내지 도 2d는 도 1에 도시된 각 단계를 개략적으로 나타내는 단면도.2A to 2D are cross-sectional views schematically showing each step shown in FIG.

<도면에 사용된 참조 번호의 설명><Description of Reference Number Used in Drawing>

10: 실리콘 기판 11: 소스/드레인10: silicon substrate 11: source / drain

12: 게이트 13: 게이트 절연막12: gate 13: gate insulating film

14: 측벽 스페이서 15: PAI 원소14 sidewall spacer 15 PAI element

16: 이온 주입 장비 17: 스퍼터링 장비16: ion implantation equipment 17: sputtering equipment

18: 금속 박막 19: 식각 정지막18: metal thin film 19: etch stop film

본 발명은 반도체 소자의 제조 기술에 관한 것으로서, 좀 더 구체적으로는 실리사이드 전-세정 공정에 의한 기판 표면의 물리적 손상을 최소화하여 반도체 소자의 특성 저하 및 오동작을 방지하고 신뢰성을 향상시킬 수 있는 실리사이드막 형 성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technology of a semiconductor device, and more particularly, a silicide film capable of minimizing physical damage to the surface of a substrate by a silicide pre-cleaning process to prevent deterioration and malfunction of semiconductor devices and to improve reliability. It is about how to form.

일반적으로 MOSFET 소자에서는 컨택 저항을 낮추기 위하여 코발트(Co), 니켈(Ni), 티타늄(Ti) 등의 금속을 이용한 자기정렬 실리사이드(self aligned silicide) 기술을 이용하고 있다. 자기정렬 실리사이드 공정은 몇 가지 선행 공정을 필요로 한다.In general, MOSFET devices use a self aligned silicide technology using a metal such as cobalt (Co), nickel (Ni), titanium (Ti), or the like to lower contact resistance. Self-aligned silicide processes require several prior processes.

우선, 금속 박막을 증착하기 전에 몰리브덴(Mo), 비소(As) 등의 무거운 원소를 이온 주입함으로써 실리콘과 폴리실리콘의 입자 크기(grain size)를 작게 만드는 PAI(pre-amorphourized implant) 공정을 진행하고 있다. 또한, PAI 공정에서 발생하는 불순물이나 자연적으로 생성되는 자연 산화막을 제거하기 위하여 세정 공정을 진행하고 있다. 이때의 세정 공정은 불순물이나 자연 산화막이 후속 실리사이드 공정의 장애 요인으로 작용하는 것을 방지하기 위한 것이다.First, prior to depositing the metal thin film, a pre-amorphourized implant (PAI) process is performed to ionize heavy elements such as molybdenum (Mo) and arsenic (As) to reduce the grain size of silicon and polysilicon. have. In addition, a cleaning process is performed to remove impurities generated in the PAI process and naturally occurring natural oxide films. The cleaning process at this time is to prevent impurities or natural oxide films from acting as a barrier to the subsequent silicide process.

종래의 실리사이드 전-세정(pre-cleaning) 공정은 불산(HF)을 이용한 습식 공정과 아르곤 플라즈마(Ar plasma)를 이용한 세정 공정이 주로 이용되고 있다. 그런데 불산을 이용한 습식 공정은 게이트 폴리실리콘을 손상시킬 수 있고, 아르곤 플라즈마를 이용한 세정 공정은 기판 표면에 물리적 손상을 입힐 수 있다. 이러한 문제는 차후 누설 전류 특성을 저하시킬 뿐만 아니라 소자의 오동작을 야기할 수 있다. 특히, 이러한 문제는 반도체 소자의 미세화 경향에 따라 배선 폭이 130nm, 90nm 등으로 계속 축소되면서 더욱 민감하게 대두되고 있다.In the conventional silicide pre-cleaning process, a wet process using hydrofluoric acid (HF) and a cleaning process using argon plasma (Ar plasma) are mainly used. However, the wet process using hydrofluoric acid may damage the gate polysilicon, and the cleaning process using argon plasma may physically damage the substrate surface. This problem not only degrades the leakage current characteristic in the future, but may also cause malfunction of the device. In particular, such a problem is becoming more sensitive as the wiring width is continuously reduced to 130 nm, 90 nm, etc. according to the tendency of the semiconductor device to be miniaturized.

아울러, 종래에는 전-세정 공정이 실리사이드 형성 공정과 서로 다른 장비 내에서 이루어지기 때문에 장비 사이를 이동하는 과정에서 웨이퍼가 공기 중에 노 출되어 다시 자연 산화막이 형성될 수 있다.In addition, in the related art, since the pre-cleaning process is performed in a different device from the silicide forming process, the wafer may be exposed to air in the process of moving between the devices, thereby forming a natural oxide film.

따라서 본 발명의 목적은 실리사이드 전-세정 공정에 의한 게이트 폴리실리콘 손상, 기판 표면 손상 등을 최소화하여 반도체 소자의 특성 저하 및 오동작을 방지하고 신뢰성을 향상시킬 수 있는 실리사이드막 형성 방법을 제공하기 위한 것이다.Accordingly, an object of the present invention is to provide a silicide film formation method which can prevent deterioration of characteristics and malfunction of semiconductor devices and improve reliability by minimizing gate polysilicon damage and substrate surface damage caused by silicide pre-clean process. .

본 발명의 다른 목적은 전-세정 공정 후 장비 이동 과정에 의하여 웨이퍼에 자연 산화막이 형성되는 문제를 해결할 수 있는 실리사이드막 형성 방법을 제공하기 위한 것이다.Another object of the present invention is to provide a silicide film formation method capable of solving the problem of forming a natural oxide film on a wafer by a device movement process after a pre-clean process.

이러한 목적들을 달성하기 위하여, 본 발명은 다음과 같은 구성의 실리사이드막 형성 방법을 제공한다.In order to achieve these objects, the present invention provides a silicide film forming method having the following configuration.

본 발명에 따른 반도체 소자의 실리사이드막 형성 방법은, 웨이퍼 전면에 PAI 공정용 원소를 이온 주입하는 단계; 스퍼터링 장비에서 상기 웨이퍼의 불순물과 자연 산화막을 제거하기 위하여 200℃ 내지 300℃의 온도에서 10분 내지 60분간 수소와 암모니아 분위기에서 어닐링 공정을 진행하는 단계; 상기 스퍼터링 장비에서 실리사이드막 형성을 위한 코발트의 금속 박막을 상기 웨이퍼 전면에 증착하는 단계; 및 상기 스퍼터링 장비에서 상기 금속 박막 위 전면에 티타늄/티타늄질화물의 장벽 금속막을 증착하는 단계;를 포함하여 구성한다.A method of forming a silicide film of a semiconductor device according to the present invention includes the steps of ion implanting an element for a PAI process onto a wafer front surface; Performing an annealing process in a hydrogen and ammonia atmosphere at a temperature of 200 ° C. to 300 ° C. for 10 to 60 minutes to remove impurities and the native oxide film of the wafer in a sputtering equipment; Depositing a metal thin film of cobalt for forming a silicide film on the front surface of the wafer in the sputtering equipment; And depositing a barrier metal film of titanium / titanium nitride on the entire surface of the metal thin film in the sputtering equipment.

삭제delete

실시예Example

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

실시예를 설명함에 있어서 본 발명이 속하는 기술 분야에 익히 알려져 있고 본 발명과 직접적으로 관련이 없는 기술 내용에 대해서는 설명을 생략한다. 이는 불필요한 설명을 생략함으로써 본 발명의 요지를 흐리지 않고 더욱 명확히 전달하기 위함이다. 마찬가지의 이유로 첨부 도면에 있어서 일부 구성요소는 과장되거나 생략되거나 개략적으로 도시되었으며, 각 구성요소의 크기는 실제 크기를 전적으로 반영하는 것이 아니다.In describing the embodiments, descriptions of technical contents which are well known in the technical field to which the present invention belongs and are not directly related to the present invention will be omitted. This is to more clearly communicate without obscure the subject matter of the present invention by omitting unnecessary description. For the same reason, some components in the accompanying drawings are exaggerated, omitted, or schematically illustrated, and the size of each component does not entirely reflect the actual size.

도 1은 본 발명의 실시예에 따른 실리사이드막 형성 방법을 나타내는 흐름도이고, 도 2a 내지 도 2d는 도 1에 도시된 각 단계를 개략적으로 나타내는 단면도이다.1 is a flowchart illustrating a silicide film forming method according to an exemplary embodiment of the present invention, and FIGS. 2A to 2D are cross-sectional views schematically illustrating respective steps shown in FIG. 1.

도 1과 도 2a를 참조하면, 본격적인 실리사이드 공정을 진행하기에 앞서 먼저 PAI 공정을 진행한다. 웨이퍼의 실리콘 기판(10)에는 통상적인 MOSFET 구조의 일부인 소스/드레인(11), 게이트(12), 게이트 절연막(13), 측벽 스페이서(14) 등이 미리 형성되어 있고, PAI 공정을 통하여 웨이퍼 전면에 몰리브덴, 비소 등의 원소(15)를 이온 주입한다. PAI 공정은 통상적인 이온 주입 장비(16) 내에서 이루어진다.1 and 2A, the PAI process is first performed prior to the full-scale silicide process. On the silicon substrate 10 of the wafer, a source / drain 11, a gate 12, a gate insulating film 13, a sidewall spacer 14, and the like, which are part of a typical MOSFET structure, are formed in advance, and the wafer front surface is formed through a PAI process. Ions are implanted with elements 15 such as molybdenum and arsenic. The PAI process takes place in conventional ion implantation equipment 16.

이어서, 도 1과 도 2b에 도시된 바와 같이, 수소(H2)와 암모니아(NH3) 분위기에서 어닐링(annealing) 공정을 진행한다. 어닐링 공정은 불순물과 자연 산화막을 제거하기 위한 공정으로, 기존의 전-세정 공정을 대체한다. 어닐링 공정은 200℃ 내지 300℃의 온도에서 10분 내지 60분간 진행한다. 예컨대, 약 250℃의 온도에서 약 30분 동안 진행할 수 있다. 어닐링 공정은 후속 실리사이드 공정에서 금속막을 증착하기 위하여 사용되는 통상적인 스퍼터링(sputtering) 장비(17) 내에서 이루어진다.Subsequently, as shown in FIGS. 1 and 2B, the annealing process is performed in an atmosphere of hydrogen (H 2 ) and ammonia (NH 3 ). The annealing process is a process for removing impurities and natural oxide film, and replaces the existing pre-cleaning process. The annealing process is performed for 10 to 60 minutes at a temperature of 200 ℃ to 300 ℃. For example, it may proceed for about 30 minutes at a temperature of about 250 ℃. The annealing process takes place in conventional sputtering equipment 17 used to deposit metal films in subsequent silicide processes.

수소와 암모니아 분위기에서 진행되는 어닐링 공정은 종래의 전-세정 공정에서 야기되는 게이트 폴리실리콘 손상, 기판 표면 손상 등을 방지하면서 효과적으로 불순물과 자연 산화막을 제거할 수 있다. 또한, 동일한 장비 내에서 어닐링 공정을 진행하기 때문에 웨이퍼 노출에 따른 자연 산화막 형성을 방지할 수 있다.The annealing process performed in the hydrogen and ammonia atmosphere can effectively remove impurities and natural oxide layers while preventing gate polysilicon damage and substrate surface damage caused by the conventional pre-cleaning process. In addition, since the annealing process is performed in the same equipment, it is possible to prevent the formation of a natural oxide film due to the wafer exposure.

이어서, 도 1과 도 2c에 도시된 바와 같이, 실리사이드막 형성을 위한 금속 박막(18)을 웨이퍼 전면에 증착한다. 금속 박막(18)은 예컨대 코발트이지만, 그 밖의 다른 금속들도 사용가능하다. 금속 박막(18)의 증착 공정은 동일한 스퍼터링 장비(17) 내에서 이루어진다.Subsequently, as shown in FIGS. 1 and 2C, a metal thin film 18 for silicide film formation is deposited on the entire wafer surface. The metal thin film 18 is, for example, cobalt, but other metals may be used. The deposition process of the metal thin film 18 takes place in the same sputtering equipment 17.

이어서, 도 1과 도 2d에 도시된 바와 같이, 금속 박막(18) 위에 식각 정지막(19, etch stopper)을 전면 증착한다. 식각 정지막(19)은 후속 공정인 컨택(contact) 식각 공정에 필요한 막으로, 예컨대 티타늄/티타늄질화물(Ti/TiN)이 사용된다. 장벽 금속막(19)의 증착 공정 역시 동일한 스퍼터링 장비(17) 내에서 이루 어진다.1 and 2D, an etch stopper 19 is deposited on the metal thin film 18. The etch stop film 19 is a film required for a subsequent contact etching process, for example, titanium / titanium nitride (Ti / TiN) is used. The deposition process of the barrier metal film 19 is also performed in the same sputtering equipment 17.

이후, 도면에 도시되지는 않았지만, 통상적인 열처리 공정 등을 진행하여 실리콘/폴리실리콘과 금속 박막의 계면 반응을 통해 자기정렬 실리사이드막을 형성한다.Subsequently, although not shown in the drawings, a normal heat treatment process may be performed to form a self-aligned silicide film through an interfacial reaction between silicon / polysilicon and a metal thin film.

이상 설명한 바와 같이, 본 발명은 종래의 전-세정 공정 대신에 수소와 암모니아 분위기에서 어닐링 공정을 진행함으로써 게이트 폴리실리콘의 손상, 기판 표면의 손상 등을 방지하면서 효과적으로 불순물과 자연 산화막을 제거할 수 있다. 이에 따라 반도체 소자의 특성을 개선할 수 있고 신뢰성을 향상시킬 수 있다. 또한, 본 발명은 실리사이드용 금속 박막을 증착하는 장비와 동일한 장비 내에서 어닐링 공정을 진행하기 때문에 웨이퍼 노출에 따른 자연 산화막 형성을 방지할 수 있다.As described above, according to the present invention, the annealing process is performed in a hydrogen and ammonia atmosphere instead of the conventional pre-cleaning process, thereby effectively removing impurities and natural oxide films while preventing gate polysilicon damage and substrate surface damage. . Accordingly, the characteristics of the semiconductor device can be improved and reliability can be improved. In addition, since the annealing process is performed in the same equipment as the equipment for depositing the metal thin film for silicide, the present invention can prevent a natural oxide film from being exposed to the wafer.

본 명세서와 도면에는 본 발명의 바람직한 실시예에 대하여 개시하였으며, 비록 특정 용어들이 사용되었으나, 이는 단지 본 발명의 기술 내용을 쉽게 설명하고 발명의 이해를 돕기 위한 일반적인 의미에서 사용된 것이지, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예 외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 자명한 것이다.In the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help the understanding of the present invention. It is not intended to limit the scope. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

Claims (6)

웨이퍼 전면에 PAI 공정용 원소를 이온 주입하는 단계;Ion implanting an element for a PAI process onto the front surface of the wafer; 스퍼터링 장비에서 상기 웨이퍼의 불순물과 자연 산화막을 제거하기 위하여 200℃ 내지 300℃의 온도에서 10분 내지 60분간 수소와 암모니아 분위기에서 어닐링 공정을 진행하는 단계;Performing an annealing process in a hydrogen and ammonia atmosphere at a temperature of 200 ° C. to 300 ° C. for 10 to 60 minutes to remove impurities and the native oxide film of the wafer in a sputtering equipment; 상기 스퍼터링 장비에서 실리사이드막 형성을 위한 코발트의 금속 박막을 상기 웨이퍼 전면에 증착하는 단계; 및Depositing a metal thin film of cobalt for forming a silicide film on the front surface of the wafer in the sputtering equipment; And 상기 스퍼터링 장비에서 상기 금속 박막 위 전면에 티타늄/티타늄질화물의 장벽 금속막을 증착하는 단계;를 포함하는 반도체 소자의 실리사이드막 형성 방법.Depositing a barrier metal film of titanium / titanium nitride on the entire surface of the metal thin film in the sputtering equipment. 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete
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KR101334946B1 (en) * 2009-09-15 2013-11-29 도쿄엘렉트론가부시키가이샤 Method for formation of metal silicide film

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JPH07169713A (en) * 1993-12-16 1995-07-04 Nec Corp Manufacture of semiconductor device
JPH113872A (en) 1997-06-12 1999-01-06 Nec Corp Manufacture of semiconductor device
JPH1126397A (en) 1997-07-01 1999-01-29 Sony Corp Manufacture of semiconductor device
JPH11233455A (en) 1998-02-17 1999-08-27 Mitsubishi Electric Corp Metal silicide film forming method and semiconductor device

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JPH07169713A (en) * 1993-12-16 1995-07-04 Nec Corp Manufacture of semiconductor device
JPH113872A (en) 1997-06-12 1999-01-06 Nec Corp Manufacture of semiconductor device
JPH1126397A (en) 1997-07-01 1999-01-29 Sony Corp Manufacture of semiconductor device
JPH11233455A (en) 1998-02-17 1999-08-27 Mitsubishi Electric Corp Metal silicide film forming method and semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101334946B1 (en) * 2009-09-15 2013-11-29 도쿄엘렉트론가부시키가이샤 Method for formation of metal silicide film

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