KR100689692B1 - Method for fabricating semiconductor device - Google Patents

Abstract

During the two heat treatment processes performed during the salicide process, the first heat treatment process was performed in a deuterium (D ₂ ) gas atmosphere instead of nitrogen gas, and the alloy process which was performed to improve device characteristics in the subsequent process was omitted. Disclosed is a method for fabricating a semiconductor device.

To this end, in the present invention, forming a gate electrode on a semiconductor substrate, forming insulating spacers on both sidewalls of the gate electrode, and forming a source / drain region in the substrate on both sides of the spacer Forming a high melting point metal film on the resultant, performing a first heat treatment process using deuterium as a source gas, and selectively forming a silicide film only on an upper surface of the gate electrode and the source / drain region; A method of manufacturing a semiconductor device is provided, which comprises removing an unreacted high melting point metal film and performing a second heat treatment process using nitrogen as a source gas for stable phase transition of the silicide film.

As a result, despite the removal of the alloying process, the same effect as that of the alloying process is actually obtained. Therefore, 1) the process can be simplified compared to the existing process, and 2) the alloying process can be performed regardless of the number of layers. The maximum effect of the process can be obtained.

Description

Semiconductor device manufacturing method {Method for fabricating semiconductor device}             

1A to 1D are process flowcharts showing a method of manufacturing a normal semiconductor device to which a salicide process is applied;

Figure 2 is a process block diagram showing a conventional device manufacturing method corresponding to Figures 1a to 1d,

3 is a process block diagram showing a device manufacturing method according to the present invention corresponding to Figures 1a to 1d.

The present invention relates to a method of manufacturing a semiconductor device to which a salicide (self-aligned silicide) process is applied.

As the integration of semiconductor devices increases, the line width and contact size of the gate electrode become smaller, resulting in a problem in that the resistance and contact resistance of the active and gate electrodes become larger. Accordingly, in recent years, the salicide process has been adopted to reduce the resistance of the contact layout of device characteristics by lowering the resistance of the active region and the gate electrode to increase the current driving capability and the contact resistance.

1A to 1D show a process flowchart showing a general method of manufacturing a semiconductor device to which the salicide process is applied. Referring to the process block diagram shown in Figure 2 divided into the fifth step as follows. As an example, a device having a three-layer wiring structure will be described.

In the first step 100, a polysilicon gate electrode 16 is formed on the semiconductor substrate (silicon substrate) 10 having the field oxide film 12 via the gate oxide film 14. LDD is formed by ion implanting a low concentration of impurities onto the substrate using as a mask. Subsequently, spacers 18 of an insulating material (eg, an oxide film) are formed on both sidewalls of the gate electrode 16, and the gate electrode 16 and the spacer 18 are used as a mask to have a high concentration on the substrate 10. An impurity is implanted to form an active region 19 for the source / drain of the LDD structure in the substrate 10 on both edges of the gate electrode 16. The result is a process output of the type shown in FIG. 1A.

In the second step 110, the silicide film 20a is selectively formed only on the top surface of the gate electrode 16 and the source / drain regions 19.

In more detail, first, as shown in FIG. 1B, a high melting point metal 20 made of Co or Ti is deposited on the entire surface of the resultant product (110a), and nitrogen (N ₂ ) gas is deposited in a sheet type facility as shown in FIG. 1C. The primary heat treatment step is performed. (110b) As a result, the silicide film 20a is selectively formed only on the upper surface of the gate electrode 16 and on the source / drain regions 19. Subsequently, the unreacted high melting point metal 20 remaining on the spacer 18 or the field oxide film 12 is removed with sulfuric acid (110c), and nitrogen gas is again used in the sheet type facility for stable phase transition. A second heat treatment process is performed (110d). The temperature and time of the heat treatment process should be optimized in consideration of the characteristics of the active resistance and junction leakage (Table 1).

Table 1

   Temperature (℃)    Time in seconds    type   gas  Primary heat treatment  Ti: 600 ~ 700     30-100   Single leaf Nitrogen (N ₂ )  Co: 450 ~ 550  Secondary heat treatment    800-900    30-100   Single leaf Nitrogen (N ₂ )

In a third step 120, a first interlayer insulating film having a plurality of contact holes is formed such that the surface of the silicide film 20a on the source / drain region 19 and the gate electrode 16 is partially exposed on the resultant. 22, and a first metal wiring 24 which is individually connected to the source / drain regions and the gate electrode is formed on the first interlayer insulating film 22 including the contact hole. Subsequently, a second interlayer insulating layer 26 including a plurality of first via holes is formed to expose a portion of the surface of the first metal wiring 24, and on the second interlayer insulating layer 26 including the via holes. After forming the second metal wiring 28 connected to the first metal wiring 24, the third interlayer insulating film provided with the second via hole so that the surface of the second metal wiring 28 is partially exposed thereon. And forming a third metal wiring 32 connected to the second metal wiring 28 on the third interlayer insulating film 30 including the second via hole, thereby completing the three-layer wiring process. .                         

As a fourth step 130, an Alloy process is performed to heat-treat the substrate on which wiring formation is completed in a deuterium (D ₂ ) atmosphere. As such, further performing the alloying process prior to the subsequent process (eg, the protective film forming process) causes deuterium to couple to the unbonded structure present at the interface between the silicon substrate and the gate oxide film, so that charge and This is to prevent oxide tunneling and increase the reliability of the gate oxide film by blocking the adhesion of impurities of the same type in advance.

As the fifth step 140, the process of the present process is completed by forming the protective film 34 of insulating material on the third interlayer insulating film 30 provided with the third metal wiring 32. As a result, the device of the type shown in FIG. 1D is completed.

However, when the salicide process is applied to the above process, several problems occur when driving the device.

First, when the alloy process is performed in a state where the multilayer wiring process is completed, deuterium is difficult to diffuse so that deuterium supplied during the process does not diffuse to the gate oxide layer 14 and is absorbed into the interlayer insulating layers. The problem arises that the effect of the process cannot be maximized. This is deepened as the wiring is multiplied. As the number of wiring layers increases, as shown in FIG. 1D, the diffusion path (indicated by an arrow) becomes longer, so that the interlayer insulating films 22, This is because the amount of gas flowing out through (26) and (30) increases.

Second, since the silicide film forming process and the alloy process are performed separately, the process progress is complicated by an increase in heat treatment.

Accordingly, an object of the present invention, during the two heat treatment processes performed during the salicide process, the first heat treatment process was carried out in the deuterium (D ₂ ) gas atmosphere instead of nitrogen, to proceed to improve the device characteristics in the subsequent process The invention provides a method for fabricating a semiconductor device that can simplify the process by allowing the alloy process to be skipped.

Another object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain the maximum effect of the alloying process regardless of the number of layers of the wiring even if the alloying process performed after the metallization process is removed.

In order to achieve the above object, in the present invention, forming a gate electrode on a semiconductor substrate; Forming insulating spacers on both sidewalls of the gate electrode; Forming a source / drain region in the substrate on both edges of the spacer; Forming a high melting point metal film on the resultant product; Performing a first heat treatment process using deuterium as a source gas to selectively form a silicide film only on an upper surface of the gate electrode and the source / drain region; Removing the unreacted high melting point metal film; And a second heat treatment process using nitrogen as a source gas for stable phase transition of the silicide film.
At this time, the first heat treatment process is preferably carried out at a temperature of 400 ~ 700 ℃ in the sheet type equipment equipped with a separate gas supply system for injecting deuterium, the second heat treatment is a temperature of 800 ~ 900 ℃ It is preferable to carry out at. In the case of the source gas, it is also possible to further use diluted nitrogen in deuterium.

delete

When the device is manufactured by applying the salicide process, since the first heat treatment process for forming the silicide layer is also responsible for the alloy process performed after the metal wiring process is completed, subsequent manufacture of the device having the multilayer wiring is performed. Not only can the Roy process be eliminated, but the alloy process is skipped, the same effect is achieved with the alloy process.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 shows a process block diagram showing a method of manufacturing a semiconductor device proposed in the present invention, which is divided into a fourth step with reference to the process steps shown in FIGS. 1A to 1D. In this case, too, an element having a three-layer wiring structure will be described as an example.                     

First, as a first step 200, a polysilicon gate electrode 16 is formed on the semiconductor substrate (silicon substrate) 10 provided with the field oxide film 12 via the gate oxide film 14. Using this as a mask, a low concentration of impurities are ion implanted onto the substrate to form LDD. Subsequently, spacers 18 of an insulating material (eg, an oxide film) are formed on both sidewalls of the gate electrode 16, and the gate electrode 16 and the spacer 18 are used as a mask to have a high concentration on the substrate 10. An impurity is implanted to form an active region 19 for the source / drain of the LDD structure in the substrate 10 on both edges of the gate electrode 16. The result is a process output of the type shown in FIG. 1A.

In the second step 210, the silicide film 20a is selectively formed only on the top surface of the gate electrode 16 and the source / drain regions 19.

More specifically, first, as shown in FIG. 1B, a high-melting-point metal 20 made of Co / TiN or Ti is deposited on the entire surface of the resultant product (210a). The first heat treatment process is carried out at a temperature of 400 ~ 700 ℃ within (210b). In this case, a single type of equipment is equipped with a separate gas supply system for injecting deuterium, and the first heat treatment process may be performed by using a source gas further containing dilute nitrogen in deuterium as a source gas. .

As a result, the silicide film 20a is selectively formed only on the upper surface of the gate electrode 16 and the source / drain regions 19, and the effect of the alloy process performed after the completion of the metallization process can also be obtained.                     

This is because the source gas (e.g., deuterium) supplied during the first heat treatment process is coupled to an unbonded structure present at the interface between the silicon substrate and the gate oxide film, thereby preventing the impurities such as charges from adhering to this portion in advance. Because it is. In this case, unlike the conventional process in which the alloy process is performed after the multi-layer wiring process, the same effect as the alloy process is performed when the silicide film is formed can be obtained. The phenomenon does not occur.

Subsequently, the unreacted high melting point metal 20 remaining on the spacer 18 or the field oxide film 12 is removed with sulfuric acid (210c), and nitrogen gas is again used in the sheet type facility for stable phase transition. The second heat treatment process is performed at a temperature of 800 ~ 900 ℃ (210d).

In a fourth step 220, a first interlayer insulating film having a plurality of contact holes is formed such that the surface of the silicide film 20a on the source / drain region 19 and the gate electrode 16 is partially exposed on the resultant. 22, and a first metal wiring 24 which is individually connected to the source / drain regions and the gate electrode is formed on the first interlayer insulating film 22 including the contact hole. Subsequently, a second interlayer insulating layer 26 including a plurality of first via holes is formed to expose a portion of the surface of the first metal wiring 24, and on the second interlayer insulating layer 26 including the via holes. After forming the second metal wiring 28 connected to the first metal wiring 24, the third interlayer insulating film provided with the second via hole so that the surface of the second metal wiring 28 is partially exposed thereon. The third layer wiring process is completed by forming the 30 and forming the third metal wiring 32 connected to the second metal wiring 28 on the third interlayer insulating film 30 including the second via hole. do.

As the fourth step 230, the process of the process is completed by forming the protective film 34 of insulating material on the third interlayer insulating film 30 provided with the third metal wiring 32. As a result, the device of the type shown in FIG. 1D is completed.

In the case of performing the salicide process based on the above procedure, since the primary heat treatment process for forming the silicide film has a merging effect to the function of the alloy process performed after the completion of the metal wiring process, a semiconductor device having a multilayer wiring The subsequent alloy process can be skipped, resulting in process simplification.

In addition, in this case, although the alloy process is skipped, the same effect as that performed by the alloy process can be obtained. Therefore, even if the metal wiring is multi-layered, the diffusion path is not increased as in the prior art. Will not. Therefore, the effect of the alloy process can be maximized regardless of the number of layers of wiring.

As mentioned above, although this invention was demonstrated concretely through the Example, this invention is not limited to this, A deformation | transformation and improvement are possible by the common knowledge of the art within the technical idea of this invention.

As described above, according to the present invention, in the two heat treatment processes performed during the salicide process, by using deuterium instead of nitrogen as the source gas during the first heat treatment process, the primary heat treatment process functions as an alloy process. Since it has a merged effect, 1) it is possible to skip the alloying process, thereby simplifying the process, and 2) the effect of the alloying process can be maintained as it is, regardless of the number of layers.

Claims (9)

Forming a gate electrode on the semiconductor substrate; Forming insulating spacers on both sidewalls of the gate electrode; Forming a source / drain region in the substrate on both edges of the spacer; Forming a high melting point metal film on the resultant product; Performing a first heat treatment process using deuterium as a source gas to selectively form a silicide film only on the upper surfaces of the gate electrode and the source / drain regions; Removing the unreacted high melting point metal film; And In order to the stable phase transition of the silicide film, a semiconductor device manufacturing method comprising the step of performing a secondary heat treatment process using nitrogen as a source gas. The method of claim 1, wherein the first heat treatment process is performed in a sheet type facility equipped with a separate gas supply system for injecting deuterium. The method of claim 2, wherein the high melting point metal film is formed of Co / TiN or Ti. The method of claim 3, wherein the first heat treatment is performed in a temperature range of 400 ° C. to 700 ° C. 5. The method of claim 4, wherein the secondary heat treatment is performed within a temperature range of 800 ° C. to 900 ° C. 6. The method of claim 1, wherein diluted nitrogen is further added to the source gas when deuterium is used. The method of claim 1, wherein the unreacted metal film is removed with a sulfate of sulfur. According to claim 1, After the second heat treatment process step, Forming a metal wiring separately connected to said gate electrode and said source / drain region via an interlayer insulating film; And forming a protective film on the interlayer insulating film provided with the metal wiring. The method of claim 8, wherein the metal wiring is a multilayer wiring.

Images