KR100688816B1 - Scan Driver and Driving Method of Light Emitting Display Using the Same - Google Patents

Abstract

The present invention relates to a scan driver which can be driven stably.

According to an exemplary embodiment of the present invention, a scan driver sequentially outputs a signal, and a buffer for supplying voltages to any one of a first power source and a second power source in response to an output signal of the shift registers. And a control circuit for supplying a third power supply and a fourth power supply having a voltage value between the first power supply and the second power supply to the buffers at least once.

With this configuration, the scan driver can be stably driven because the characteristic curve is controlled to maintain a substantially constant voltage even when a high drain-source voltage is applied to at least one transistor included in the buffer of the scan driver.

Description

Scan driver and light emitting display using same and driving method thereof {Scan Driver and Driving Method of Light Emitting Display Using the Same}             

1 is a view schematically showing a conventional scan driver.

FIG. 2 is a circuit diagram showing in detail the buffer shown in FIG.

3 is a diagram showing an example of a characteristic curve of the transistor shown in FIG. 2;

4A and 4B are diagrams showing a defect generated in the image display unit by kink current and / or leakage current or the like.

5 is a view showing a light emitting display device according to an embodiment of the present invention;

FIG. 6 is a view showing a scan driver shown in FIG. 5; FIG.

7A to 7C are circuit diagrams illustrating a connection structure between a buffer and a control circuit illustrated in FIG. 5.

FIG. 8 is a waveform diagram showing a control signal supplied to the control circuit shown in FIGS. 7A to 7C.

9 is a view showing that a characteristic curve of a transistor included in a buffer is changed.

10 is a circuit diagram showing a connection structure according to another embodiment of a buffer and a control circuit.

11 is a circuit diagram showing a connection structure according to another embodiment of a buffer and a control circuit.

12 is a waveform diagram showing a control signal supplied to the control circuit shown in FIG.

<Explanation of symbols for the main parts of the drawings>

12: shift register block 14: NAND gate block

16: buffer block 110: scan driver

121,122,123,124,12n, 1121,1122,1123,1124,112n: Shift register

141,142,143,144,14n, 1141,1142,1143,1144,114n: NAND gate

161,162,163,164,16n, 1161,1162,1163,1164,116n: buffer

118: control circuit 120: data driver

130: image display unit 140: pixels

150: timing controller 200: control signal supply unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan driver, a light emitting display using the same, and a driving method thereof, and more particularly, to a scan driver capable of driving stably, a light emitting display using the same, and a driving method thereof.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among flat panel display devices, the light emitting display device includes a plurality of light emitting devices, and the light emitting devices generate predetermined light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption.

1 is a diagram illustrating a conventional scan driver used in a light emitting display device.

Referring to FIG. 1, a conventional scan driver 10 includes a shift register block 12, a nand gate block 14, and a buffer block 16. .

The shift register block 12 includes n (n is a natural number) shift registers 121, 122, ..., 12n. Each shift register 121, 122, ..., 12n is supplied with a clock signal CLK and a clock bar signal CLKb. Each of the shift registers 121, 122, ..., 12n supplied with the clock signal CLK and the clock bar signal CLKb sends an output signal to the lower shift register when an output signal is input from the upper shift register. To pass. In other words, the shift registers 121, 122, ..., 12n are connected such that the upper output signal is shifted to the lower shift register. Here, the upper and lower represent the order according to the flow of the signal.

The NAND gate block 14 includes n NAND gates 141, 142, ..., 14n provided for each output terminal of each of the shift registers 121, 122, ..., 12n. Each of the NAND gates 141, 142,..., And 14n NAND output signals of the shift registers 121, 122,..., And 12n and an enable signal EN (or an enable bar signal / EN). The operation is supplied to the buffer block 16. Here, since the output signals are sequentially supplied from the shift registers 121, 122,..., And 12n, the NAND gates 141, 142,..., 14n also sequentially output the output signals to the buffer block 16. Supply.

The buffer block 16 has n buffers 161, 162, ..., 16n provided for each output terminal of each of the NAND gates 141, 142, ..., 14n. Each of the buffers 161, 162, ..., 16n sequentially supplies the output signal supplied thereto to the first scan line S1 to the nth scan line Sn. Here, an output signal output from the buffers 161, 162, ..., 16n is used as a scan signal.

However, the conventional scan driver 10 driven as described above generates a predetermined kink current and / or leakage current when operating at a process deviation and / or a high temperature, thereby causing the scan driver 10 to malfunction. Problems arise. This is due to the leakage current and / or kink current of the N-type transistor and the P-type transistor used in the buffers 161, 162, ..., 16n. This will be described in detail with reference to FIG. 2.

FIG. 2 is a diagram illustrating in detail the buffer illustrated in FIG. 1. Here, since each of the buffers 161,..., 16n has the same structure, it is assumed that the buffer shown in FIG. 2 is the first buffer 161. The buffer 161 is connected to the plurality of pixels via the scan line S. FIG. Thus, the transistors included in the buffers 161, ..., 16n are included in the shift registers 121, ..., 12n and the NAND gates 141, ..., 14n to supply sufficient current. It is formed to have a channel / length (W / L) of a larger size than the transistors.

Referring to FIG. 2, the buffer 161 is composed of two stage circuits composed of the N-type transistors 16a and 16b and the P-type transistors 16c and 16d. When the first power supply voltage VVDD is supplied from the NAND gate 141, the first transistor 16a and the fourth transistor 16d are turned on to supply the first power supply voltage VVDD to the scan line S. FIG. . When the second power supply voltage VVSS is supplied from the NAND gate 141, the third transistor 16c and the second transistor 16b are turned on so that the second power supply voltage VVSS is turned to the scan line S. Supplied.

Here, since the first power supply voltage VVDD and the second power supply voltage VVSS have a predetermined voltage difference, the transistor may operate in the king region due to the variation of the process conditions. In this case, the scan driver 10 ) Is a problem that is stopped. It is assumed that the first transistor 16a has the characteristic curve as shown in FIG. 3 according to the process conditions, and it is described in detail by assuming that the first power supply voltage VVDD is 5V and the second power supply voltage VVSS is -7V. Let's do it.

First, when the first power supply voltage VVDD is supplied from the NAND gate 141, the third transistor 16c is turned on. When the third transistor 16c is turned on, the voltage at the first node point N1 is set to 5V, which is a voltage value of the first power supply voltage VVDD. Here, the VDS is set to 12V because the first terminal of the first transistor 16a is connected to the first node point N1 and the second terminal is connected to the second power supply voltage VVSS. In this case, as shown in FIG. 3, the first transistor 16a is driven in the kink region in which the current is rapidly increased. As such, when the first transistor 16a is driven in the kink region, the scan driver 10 may not be normally driven. In particular, when the scan driver 10 is driven at a high temperature, the self-current (or leakage current) of the transistors 16a to 16d increases due to the temperature, thereby causing the malfunction of the scan driver 10 to be more severe. In fact, when a malfunction occurs in the scan driver 10, as shown in FIGS. 4A and 4B, all screens below a specific horizontal line are displayed as defective.

Accordingly, an aspect of the present invention is to provide a scan driver, a light emitting display device using the same, and a driving method thereof, which can stably drive the same.

In order to achieve the above object, the first aspect of the present invention provides a shift register for sequentially outputting a signal and a voltage of any one of a first power supply and a second power supply in response to an output signal of the shift registers. A scan driver includes a buffer for supplying, and a control circuit for supplying a third power source and a fourth power source having a voltage value between the first power source and the second power source to the buffers at least once.

Preferably, the device further includes NAND gates disposed between the buffers and the shift registers. Each of the buffers is connected in series between the first power supply and the second power supply, and a first transistor and a third transistor having a gate terminal connected to one of the NAND gates, and between the first power supply and the second power supply. And a second transistor and a fourth transistor connected in series to each other and having a gate terminal connected to a first node point, which is a common terminal of the first and third transistors.

A second aspect of the present invention provides shift registers for sequentially outputting signals, buffers connected to each of the shift registers to supply output signals of the shift registers to scan lines, and electrically connected to the buffers. And a scan driver including a control circuit for controlling a characteristic curve of at least one transistor included in the buffers.

Preferably, the device further includes NAND gates disposed between the buffers and the shift registers. The control circuit supplies a threshold voltage to at least one transistor included in the buffers.

A third aspect of the present invention provides an image display unit including a plurality of pixels, a data driver for driving data lines connected to the pixels, and a scan line connected with the pixels. A light emitting display device comprising the scan driver according to claim 7 is provided.

A fourth aspect of the present invention is a method of driving a light emitting display device including a plurality of buffers in a scan driver, the method comprising: controlling a characteristic curve of at least one transistor included in the buffers; A second method of sequentially outputting a signal from a shift register, and a third step of sequentially supplying signals output to the shift register to scan lines through a buffer, are provided.

Hereinafter, preferred embodiments of the present invention may be easily implemented by those skilled in the art with reference to FIGS. 5 to 12 as follows.

5 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a light emitting display device according to an exemplary embodiment of the present invention includes an image display unit 130 including pixels 140 formed at intersections of scan lines S1 to Sn and data lines D1 to Dm. And the scan driver 110 for driving the scan lines S1 to Sn, the data driver 120 for driving the data lines D1 to Dm, the scan driver 110 and the data driver 120. A timing controller 150 for controlling is provided.

The image display unit 130 receives the first power source VDD and the second power source VSS from the outside. The first power source VDD and the second power source VSS supplied to the image display unit 130 are supplied to the respective pixels 140. The pixels 140 generate light corresponding to the data signals supplied from the data driver 120 when the scan signals are supplied from the scan driver 110.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm.

The scan driver 110 receives the scan driving control signal SCS from the timing controller 150. The scan driver 110 supplied with the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

6 is a block diagram illustrating in detail the scan driver illustrated in FIG. 5.

Referring to FIG. 6, the scan driver 110 of the present invention includes a shift register block 112, a NAND gate block 114, and a buffer block 116.

The shift register block 112 includes n (n is a natural number) shift registers 1121, 1122, ..., 112n. Each shift register 1121, 1122,..., 112n receives a clock signal CLK and a clock bar signal CLKb. The shift registers 1121, 1122, ..., 112n receiving the clock signal CLK and the clock bar signal CLKb transfer the output signal to the lower shift register when the output signal is input from the upper shift register. do.

In detail, first, the start pulse SP is supplied from the timing controller 150 to the first shift register 1121. The first shift register 1121 supplied with the start pulse SP generates an output signal and transfers the generated output signal to the first NAND gate 1141 and the second shift register 1122. The second shift register 1122 receiving the output signal generates an output signal and transfers the generated output signal to the second NAND gate 1142 and the third shift register 1123. In practice, the shift register block 112 sequentially transmits the output signal to the nth shift register 112n while repeating the above-described process.

The NAND gate block 114 includes n NAND gates 1141, 1142,..., 114n provided for each output terminal of each of the shift registers 1121, 1122,..., 112n. Each NAND gate 1141, 1142,..., And 114n has an output signal of the shift registers 1121, 1122,..., 112n and an enable signal EN (or an enable bar signal / EN). NAND is supplied to the buffer block 1161. Here, since the output signals are sequentially supplied from the shift registers 1121, 1122, and 112n, the NAND gates 1141, 1142,..., 114n also sequentially supply the output signals to the buffer block 116.

The buffer block 116 includes n buffers 1161, 1162,..., 116n installed at each output terminal of each of the NAND gates 1141, 1142,..., 114n. Each of the buffers 1161, 1162,..., 116n sequentially supplies an output signal supplied thereto to the first scan line S1 to the nth scan line Sn. Here, an output signal output from the buffers 1161, 1162, ..., 116n is used as a scan signal.

Meanwhile, the scan driver 110 of the present invention includes a control circuit 118 electrically connected to the buffers 1161, 1162,..., 116n included in the buffer block 116. The control circuit 118 controls the characteristic curve of at least one transistor included in each of the buffers 1161, 1162,..., 116n so that the scan driver 110 can be stably driven. Here, the control circuit 118 is not driven when the scan driver 110 supplies the scan signal. In practice, the control circuit 118 operates at least once before the light emitting display device is shipped to control the characteristic curves of the transistors included in the buffers 1161, 1162,..., 116n, and are not otherwise used. (Actually, the control circuit 118 drives at least one transistor included in the buffers 1161, 1162, ..., 116n to a threshold voltage.)

The light emitting display device further includes a control signal supply unit 200 installed inside or outside the scan driver 110. The control signal supply unit 200 supplies at least one control signal so that the control circuit 118 can be driven. The control signal supply unit 200 may be detachably installed in the light emitting display device. In addition, the control signal supply unit 200 may be installed to be mounted on the light emitting display device. For example, the control signal supply unit 200 may be installed to be included in the timing controller 150.

FIG. 7A is a circuit diagram illustrating in detail the control circuit and the buffer illustrated in FIG. 6. 8 is a diagram illustrating an embodiment of a control signal supplied from a control signal supply unit. Here, since the buffers 1161, 1162,..., 116n have the same structure, only the first buffer 1161 is shown in FIG. 7A.

The buffer included in the buffer 1161 is formed to have a channel / length (W / L) of a larger size than the transistors included in the shift register 1121 and the NAND gate 114 to supply sufficient current. The buffer 1161 is composed of two stage circuits composed of the N-type transistors M1 and M2 and the P-type transistors M3 and M4.

The first terminal (source terminal or drain terminal) of the first transistor M1 formed of the N-type is connected to the second power supply voltage VVSS, and the second terminal (drain terminal or source terminal) is connected to the first node point ( N1). The gate terminal of the first transistor M1 is connected to the output terminal of the NAND gate 1141. The first terminal of the third transistor M3 formed of the P-type is connected to the first power supply voltage VVDD, and the second terminal is connected to the first node point N1. The gate terminal of the third transistor M3 is connected to the output terminal of the NAND gate 1141. The first transistor M1 and the third transistor M3 supply the second power supply voltage VVSS to the first node point N1 when the first power supply voltage VVDD is supplied from the NAND gate 1141. When the second power supply voltage VVSS is supplied from the NAND gate 1141, the first power supply voltage VVDD is supplied to the first node point N1. That is, the first transistor M1 and the third transistor M3 play the role of the inverter 1161a (first inverter).

The first terminal of the second transistor M2 formed of the N-type is connected to the second power supply voltage VVSS, and the second terminal is connected to the scan line S. The gate terminal of the second transistor M2 is connected to the first node point N1. The first terminal of the fourth transistor M4 formed of the P-type is connected to the first power supply voltage VVDD, and the second terminal is connected to the scan line S. The gate terminal of the fourth transistor N4 is connected to the first node point N1. The second transistor M2 and the fourth transistor M4 supply the second power supply voltage VVSS to the scan line S when the first power supply voltage VVDD is supplied to the first node point N1. When the second power supply voltage VVSS is supplied, the first power supply voltage VVDD is supplied to the scan line S. That is, the second transistor M2 and the fourth transistor M4 serve as the inverter 1161b (second inverter).

 When the scan driver 100 is normally driven, the buffer 1161 receives the first power supply voltage VVDD or the second power supply voltage VVSS from the NAND gate 1141. When the first power supply voltage VVDD is supplied from the NAND gate 1141, the first transistor M1 and the fourth transistor M4 are turned on. Then, the first power supply voltage VVDD is supplied to the scan line S (pixel off voltage). When the second power supply voltage VVSS is supplied from the NAND gate 1141, the third transistor M3 and The second transistor M2 is turned on to supply the second power supply voltage VVSS (scanning signal) to the scan line S. (pixels on voltage)

On the other hand, the control circuit 118 is driven at least once before the light emitting display device is shipped to control the characteristic curve of the transistors included in the buffer 1161. That is, the control circuit 118 does not operate when the scan driver 110 is normally driven.

The control circuit 118 is provided between the third power source V3 and the input terminal of the buffer 1161 and is controlled by the first control signal CS1, the fifth transistor M5, the fourth power source V4 and the buffer. A sixth transistor M6 is provided between the input terminals of 1161 and controlled by the second control signal CS2. The third power source V3 has a voltage value corresponding to the threshold voltages of the N-type transistors M1 and M2 included in the buffer 1161. For example, the third power source V3 may be set to a voltage between 1V and 4V. The fourth power source V4 has a voltage value corresponding to the threshold voltages of the P-type transistors M3 and M4 included in the buffer 1161. For example, the fourth power source V4 may be set to a voltage between -1V and -4V.

The control signal supply unit 200 supplies the first control signal CS1 and the second control signal CS2 as shown in FIG. 8 before the light emitting display device is shipped. Here, the first control signal CS1 and the second control signal CS2 are supplied at different times. The first control signal CS1 and the second control signal CS2 are supplied at least once.

When the first control signal CS1 is supplied, the fifth transistor M5 is turned on. When the fifth transistor M5 is turned on, the voltage of the third power source V3 is supplied to the gate terminal of the first transistor M1 to turn on the first transistor M1. When the first transistor M1 is turned on, a predetermined current is increased by a voltage difference between the voltage value of the first node point N1 (for example, the first power supply voltage VVDD) and the second power supply voltage VVSS. Will flow. Here, since the first transistor M1 is driven at the threshold voltage, the first transistor M1 is subjected to a predetermined carrier stress, and thus the characteristic curve is changed to be substantially horizontal.

In detail, first, in the initial state, as shown in FIG. 9, when a voltage of VDS is applied to approximately -7.5V or more, the current rapidly increases (king current). If it flows, the scan driver 110 may not be driven normally. However, if the threshold voltage (assuming -4V in this case) is lowered to the transistor and then -20V is applied to VDS for about 10 ms, the transistor is changed to be substantially parallel to the characteristic curve of the transistor. Then, even though the voltage of the VDS of the transistor is set to approximately -18V, the flowing current remains almost constant. It is predicted that the characteristic curve is changed experimentally due to collision of carriers when the transistor is driven near the threshold voltage. In addition, even when the voltage of the VDS of the transistor is experimentally maintained at -30V, the characteristic curve is set substantially the same as when -20V is applied to the VDS. This means that the high low of the VDS of the transistor has little effect on the characteristic curve.

Therefore, when the third voltage V3 corresponding to the threshold voltage is supplied to the gate terminal of the first transistor M1 when the first control signal CS1 is supplied, a high VDS voltage is applied to the first transistor M1. Even though the characteristic curve is changed so that the current does not change suddenly. As such, when the characteristic curve of the first transistor M1 is changed, the scan driver 110 may be stably driven.

When the second control signal CS2 is supplied after the first control signal CS1 is supplied, the sixth transistor M6 is turned on. When the sixth transistor M6 is turned on, the voltage value of the fourth power source V4 corresponding to the threshold voltage is supplied to the gate terminal of the third transistor M3. Then, the third transistor M3 is turned on, and accordingly, the voltage difference between the voltage value of the first node point N1 (for example, the second power supply voltage VVSS) and the first power supply voltage VVSS is different. By this, a predetermined current flows. Here, since the third transistor M3 is supplied with the threshold voltage, the characteristic curve of the third transistor M3 is changed so that the current does not change rapidly even when a high VDS voltage is applied as shown in FIG. 9. do. As such, when the characteristic curve of the third transistor M3 is changed, the scan driver 110 may be stably driven.

Meanwhile, in the present invention, only the characteristic curves of the first transistor M1 and the third transistor M3 are changed. As such, even if only the characteristic curves of the first transistor M1 and the third transistor M3 are changed, a certain degree of reliability can be secured regardless of the characteristics of the second transistor M2 and the fourth transistor M4.

Meanwhile, although the fifth transistor M5 included in the control circuit 118 is illustrated as a P-type transistor, and the sixth transistor M6 is illustrated as an N-type transistor, the present invention is not limited thereto. In fact, in the present invention, as illustrated in FIG. 7B, the fifth transistor M5 and the sixth transistor M6 may be formed of an N-type transistor. In the present invention, as illustrated in FIG. 7C, the fifth transistor M5 and the sixth transistor M6 may be formed of a P-type transistor.

Meanwhile, in the present invention, the installation position and the structure of the control circuit 118 may be changed in various forms. This will be described in detail with reference to FIGS. 10 and 11.

10 is a view showing a connection structure according to another embodiment of a control circuit and a buffer.

Referring to FIG. 10, the control circuit 118 is electrically connected to the first node point N1 of the buffer 1161 (the output terminal of the first inverter 1161a and the input terminal of the second inverter 1161b). . The control circuit 118 is driven at least once before the light emitting display device is shipped to control the characteristic curves of the second transistor M2 and the fourth transistor M4 included in the buffer 1161.

The control circuit 118 is provided between the third power source V3 and the first node point N1 and is controlled by the first control signal CS1, the fifth transistor M5, and the fourth power source V4. The sixth transistor M6 is disposed between the first node point N1 and controlled by the second control signal CS2. The third power supply V3 has a voltage value corresponding to the threshold voltages of the N-type transistors M1 and M2 included in the buffer 1161. The fourth power source V4 has a voltage value corresponding to the threshold voltages of the P-type transistors M3 and M4 included in the buffer 1161.

The control signal supply unit 200 supplies the first control signal CS1 and the second control signal CS2 as shown in FIG. 8 before the light emitting display device is shipped. Here, the first control signal CS1 and the second control signal CS2 are supplied at least once for different times.

When the first control signal CS1 is supplied, the fifth transistor M5 is turned on. When the fifth transistor M5 is turned on, the voltage of the third power source V3 is supplied to the gate terminal of the second transistor M2 to turn on the second transistor M2. When the second transistor M2 is turned on, a predetermined current flows due to a voltage difference between the first terminal and the second terminal of the fourth transistor M4. Then, the second transistor M2 receives a predetermined carrier stress, and accordingly, the characteristic curve of the second transistor M2 is changed so that the current does not change rapidly even when a high VDS voltage is applied as shown in FIG. 9. do. As such, when the characteristic curve of the second transistor M2 is changed, the scan driver 110 may be stably driven.

When the second control signal CS2 is supplied after the first control signal CS1 is supplied, the sixth transistor M6 is turned on. When the sixth transistor M6 is turned on, the voltage value of the fourth power source V4 corresponding to the threshold voltage is supplied to the gate terminal of the fourth transistor M4. Then, the fourth transistor M4 is turned on, so that a predetermined current flows in the fourth transistor M4 due to a voltage difference between the first terminal and the second terminal. Here, since the fourth transistor M4 is supplied with the threshold voltage, the characteristic curve of the fourth transistor M4 is changed so that the current does not change rapidly even when a high VDS voltage is applied as shown in FIG. 9. . As such, when the characteristic curve of the fourth transistor M4 is changed, the scan driver 110 may be stably driven.

Meanwhile, in another embodiment of the present invention, only the characteristic curves of the second transistor M2 and the fourth transistor M4 are changed. As such, even if only the characteristic curves of the second transistor M2 and the fourth transistor M4 are changed, a certain degree of reliability can be secured regardless of the characteristics of the first transistor M1 and the third transistor M3.

11 is a view showing a connection structure according to another embodiment of a control circuit and a buffer. FIG. 12 is a diagram illustrating a control signal supplied to the control circuit shown in FIG. 11.

Referring to FIG. 11, the control circuit 118 is electrically connected to an input terminal of the buffer 1161 and the first node point N1. The control circuit 118 is driven at least once before the light emitting display device is shipped to control the characteristic curves of the first transistor M1 to the fourth transistor M4 included in the buffer 1161.

To this end, the control circuit 118 is connected to the input terminal of the buffer 1161 and the first control circuit 118a and the second transistor for controlling the characteristic curves of the first transistor M1 and the third transistor M3. A second control circuit 118b for controlling the characteristic curves of the M2 and the fourth transistor M4 is provided.

The first control circuit 118a includes a fifth transistor M5 provided between the third power source V3 and the input terminal, and a sixth transistor M6 provided between the fourth power source V4 and the input terminal. The second control circuit 118b is provided between the seventh transistor M7 provided between the third power source V3 and the first node point N1, and between the fourth power source V4 and the first node point N1. Eighth transistor M8 is provided.

The control signal supply unit 200 supplies the first control signal CS1 to the fourth control signal CS2 as shown in FIG. 12 before the light emitting display device is shipped. Here, the first control signal CS1 to the fourth control signal CS2 are supplied at least once during different times.

When the first control signal CS1 is supplied, the fifth transistor M5 is turned on. When the fifth transistor M5 is turned on, the voltage value of the third power supply V3 corresponding to the threshold voltage of the first transistor M1 is supplied to the gate terminal of the first transistor M1. Then, the first transistor M1 is turned on, so that a predetermined current flows due to the voltage difference between the first terminal and the second terminal of the first transistor M1. Here, since the first transistor M1 is supplied with a threshold voltage, the characteristic curve of the first transistor M1 is changed so that the current does not change rapidly even when a high VDS voltage is applied as shown in FIG. 9. .

When the second control signal CS2 is supplied, the sixth transistor M6 is turned on. When the sixth transistor M6 is turned on, the voltage value of the fourth power supply V4 corresponding to the threshold voltage of the third transistor M3 is supplied to the gate terminal of the third transistor M3. Then, the third transistor M3 is turned on, so that a predetermined current flows due to the voltage difference between the first terminal and the second terminal of the third transistor M3. Here, since the third transistor M3 is supplied with the threshold voltage, the characteristic curve of the third transistor M3 is changed in the characteristic curve so that the current does not change rapidly even when a high VDS voltage is applied as shown in FIG. 9. .

When the third control signal CS3 is supplied, the seventh transistor M7 is turned on. When the seventh transistor M7 is turned on, the voltage value of the third power supply V3 corresponding to the threshold voltage of the second transistor M2 is supplied to the gate terminal of the second transistor M2. Then, the second transistor M2 is turned on, so that a predetermined current flows due to the voltage difference between the first terminal and the second terminal of the second transistor M2. Here, since the second transistor M2 is supplied with the threshold voltage, the characteristic curve of the second transistor M2 is changed so that the current does not change rapidly even when a high VDS voltage as shown in FIG. 9 is applied.

When the fourth control signal CS4 is supplied, the eighth transistor M8 is turned on. When the eighth transistor M8 is turned on, the voltage value of the fourth power supply V4 corresponding to the threshold voltage of the fourth transistor M4 is supplied to the gate terminal of the fourth transistor M4. Then, the fourth transistor M4 is turned on, and a predetermined current flows due to the voltage difference between the first terminal and the second terminal of the fourth transistor M4. Here, since the fourth transistor M4 is supplied with the threshold voltage, the characteristic curve of the fourth transistor M4 is changed so that the current does not change rapidly even when a high VDS voltage is applied as shown in FIG. 9. .

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the scan driver, the light emitting display using the same, and a driving method thereof, the scan driver is substantially constant even if a high drain-source voltage is applied to at least one transistor included in the buffer of the scan driver. Since the characteristic curve is controlled to maintain the scan drive, the scan driver can be driven stably.

Claims (26)

Shift registers for sequentially outputting signals, Buffers for supplying a voltage to any one of a first power source and a second power source to scan lines in response to output signals of the shift registers And a control circuit for supplying a third power supply and a fourth power supply having a voltage value between the first power supply and the second power supply to the buffers at least once. The method of claim 1, And a NAND gate disposed between the buffers and the shift registers. The method of claim 2, Each of the buffers A first transistor and a third transistor connected in series between the first power supply and the second power supply and having a gate terminal connected to any one of the NAND gates; And a second transistor and a fourth transistor connected in series between the first power supply and the second power supply, and having a gate terminal connected to a first node point which is a common terminal of the first transistor and the third transistor. The method of claim 3, The control circuit A fifth transistor connected between the third power source corresponding to the threshold voltage of the first transistor and the gate terminal of the first transistor and turned on in response to a first control signal supplied from the outside; And a sixth transistor connected between the fourth power source corresponding to the threshold voltage of the third transistor and the gate terminal of the third transistor and turned on in response to a second control signal supplied from the outside. The method of claim 3, The control circuit A fifth transistor connected between the third power source corresponding to the threshold voltage of the second transistor and the gate terminal of the second transistor and turned on in response to a first control signal supplied from the outside; And a sixth transistor connected between the fourth power source corresponding to the threshold voltage of the fourth transistor and the gate terminal of the fourth transistor and turned on in response to a second control signal supplied from the outside. The method of claim 3, The control circuit A fifth transistor connected between the third power source corresponding to the threshold voltage of the first transistor and the gate terminal of the first transistor and turned on in response to a first control signal supplied from the outside; A sixth transistor connected between the fourth power source corresponding to the threshold voltage of the third transistor and the gate terminal of the third transistor and turned on in response to a second control signal supplied from the outside; A seventh transistor connected between the third power source corresponding to the threshold voltage of the second transistor and the gate terminal of the second transistor and turned on in response to a third control signal supplied from the outside; And an eighth transistor connected between the fourth power source corresponding to the threshold voltage of the fourth transistor and the gate terminal of the fourth transistor and turned on in response to a fourth control signal supplied from the outside. Shift registers for sequentially outputting signals, Buffers connected to each of the shift registers to supply output signals of the shift registers to scan lines; And a control circuit electrically connected to the buffers and configured to control a characteristic curve of at least one transistor included in the buffers. The method of claim 7, wherein And a NAND gate disposed between the buffers and the shift registers. The method of claim 7, wherein The control circuit is a scan driver for supplying a threshold voltage to at least one transistor included in the buffer. The method of claim 8, Each of the buffers A first transistor and a third transistor connected in series between a first power supply and a second power supply, the gate terminal of which is connected to one of the NAND gates; And a second transistor and a fourth transistor connected in series between the first power supply and the second power supply, and having a gate terminal connected to a first node point which is a common terminal of the first transistor and the third transistor. The method of claim 10, And the first and second transistors are set to an N-type, and the third and fourth transistors are set to a P-type. The method of claim 11, The control circuit is a scan driver for controlling the characteristic curve of the first transistor and the third transistor. The method of claim 12, The control circuit A fifth transistor connected between a third power source corresponding to the threshold voltage of the first transistor and a gate terminal of the first transistor and turned on in response to a first control signal supplied from the outside; And a sixth transistor connected between a fourth power source corresponding to the threshold voltage of the third transistor and a gate terminal of the third transistor and turned on in response to a second control signal supplied from the outside. The method of claim 11, The control circuit is a scan driver for controlling the characteristic curve of the second transistor and the fourth transistor. The method of claim 14, The control circuit A fifth transistor connected between a third power source corresponding to the threshold voltage of the second transistor and a gate terminal of the second transistor and turned on in response to a first control signal supplied from the outside; And a sixth transistor connected between a fourth power source corresponding to the threshold voltage of the fourth transistor and a gate terminal of the fourth transistor and turned on in response to a second control signal supplied from the outside. The method according to claim 13 or 15, And the first control signal and the second control signal are supplied at least once at different times to turn on the fifth transistor and the sixth transistor. The method according to claim 13 or 15, Each of the fifth transistor and the sixth transistor is formed of any one of an N-type and a P-type scan driver. The method of claim 11, The control circuit is a scan driver for controlling the characteristic curve of the first transistor to the fourth transistor. The method of claim 18, The control circuit A fifth transistor connected between a third power source corresponding to the threshold voltage of the first transistor and a gate terminal of the first transistor and turned on in response to a first control signal supplied from the outside; A sixth transistor connected between a fourth power source corresponding to the threshold voltage of the third transistor and a gate terminal of the third transistor and turned on in response to a second control signal supplied from the outside; A seventh transistor connected between the third power source corresponding to the threshold voltage of the second transistor and the gate terminal of the second transistor and turned on in response to a third control signal supplied from the outside; And an eighth transistor connected between the fourth power source corresponding to the threshold voltage of the fourth transistor and the gate terminal of the fourth transistor and turned on in response to a fourth control signal supplied from the outside. The method of claim 19, The first to fourth control signals are supplied at least once at different times to turn on the fifth to eighth transistors. The method of claim 19, Each of the fifth to eighth transistors is formed of any one of an N-type and a P-type. An image display unit including a plurality of pixels, A data driver for driving data lines connected to the pixels; A light emitting display device comprising the scan driver as claimed in claim 1 or 7 to drive scan lines connected to the pixels. A driving method of a light emitting display device including a plurality of buffers in a scan driver, A first step of controlling a characteristic curve of at least one transistor included in the buffers; A second step of sequentially outputting signals from the shift register of the scan driver; And a third step of sequentially supplying signals output to the shift register to scan lines through a buffer. The method of claim 23, wherein And driving the threshold voltage to the transistor in the first step. The method of claim 24, The first step of supplying the threshold voltage to the transistor is performed at least once before the light emitting display device is shipped. Otherwise, the second and third steps are repeated to drive the scan lines. . The method of claim 25, NAND operation of the enable signal supplied from the outside and the output signal of the shift register, and supplying the output signal generated by the NAND operation to the buffer.

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