KR100688688B1 - Apparatus for monitoring a guard-ring in a semiconductor device - Google Patents

Apparatus for monitoring a guard-ring in a semiconductor device Download PDF

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KR100688688B1
KR100688688B1 KR1020020021249A KR20020021249A KR100688688B1 KR 100688688 B1 KR100688688 B1 KR 100688688B1 KR 1020020021249 A KR1020020021249 A KR 1020020021249A KR 20020021249 A KR20020021249 A KR 20020021249A KR 100688688 B1 KR100688688 B1 KR 100688688B1
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guard ring
chip
monitoring
semiconductor chip
guard
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KR1020020021249A
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Korean (ko)
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KR20030082773A (en
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나유석
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동부일렉트로닉스 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

반도체 칩 가드 링의 모니터링 장치를 개시한다.Disclosed is a monitoring device for a semiconductor chip guard ring.

본 발명은, 반도체 소자의 칩 외곽의 가드 링에 있어서, 칩의 가드 링에 대한 전기적 데이터를 얻기 위한 가드 링 단자가 구비되는 반도체 칩 가드 링의 모니터링 장치를 제공한다.The present invention provides a monitoring device for a semiconductor chip guard ring in which a guard ring terminal for obtaining electrical data for a guard ring of a chip is provided in a guard ring outside the chip of the semiconductor element.

즉, 본 발명은 가드 링 소정 위치에 테스트용 단자를 설치하여 공정 또는 장비의 전기적 모니터링을 구현함으로써, 추가적인 장치나 실험 없이 모든 칩에 대한 모니터링을 구현할 수 있다.That is, the present invention implements electrical monitoring of a process or equipment by installing a test terminal at a predetermined position on the guard ring, so that monitoring of all chips can be implemented without additional devices or experiments.

가드 링Guard ring

Description

반도체 칩 가드 링의 모니터링 장치{APPARATUS FOR MONITORING A GUARD-RING IN A SEMICONDUCTOR DEVICE}Monitoring device for semiconductor chip guard ring {APPARATUS FOR MONITORING A GUARD-RING IN A SEMICONDUCTOR DEVICE}

도 1은 일반적인 가드 링이 형성된 반도체 칩의 평면도,1 is a plan view of a semiconductor chip in which a general guard ring is formed;

도 2는 도 1의 단면도로서, 가드 링과 상하부 금속을 연결하는 접속 홀을 도시한 도면,FIG. 2 is a cross-sectional view of FIG. 1 illustrating a connection hole connecting a guard ring and upper and lower metals;

도 3은 도 1의 단면도로서, 가드 링과 상하부 금속을 연결하는 트렌치 형태의 접속 라인을 도시한 도면,FIG. 3 is a cross-sectional view of FIG. 1 showing a trench connection line connecting a guard ring and upper and lower metals;

도 4는 본 발명에 따른 테스트용 단자가 구비된 가드 링이 형성된 반도체 칩의 평면도.4 is a plan view of a semiconductor chip with a guard ring provided with a test terminal according to the present invention.

본 발명은 반도체 칩 외곽에 형성되는 가드 링(guard-ring)에 관한 것으로, 특히, 가드 링에 테스트용 단자를 설치하여 공정 또는 장비의 전기적 모니터링을 구현한 반도체 칩 가드 링의 모니터링 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a guard ring formed on the outside of a semiconductor chip. More particularly, the present invention relates to a monitoring device for a semiconductor chip guard ring in which test terminals are provided on the guard ring to implement electrical monitoring of a process or equipment. .

일반적인 반도체 칩 제조 공정에서는, 반도체 칩을 제조한 후 여러 가지 신뢰도 평가 항목에서 고온 가압 상태에서의 습도에 대한 내구성을 테스트하는 항목 이 포함되는데, 이때, 습도에 대한 반도체 칩의 내부를 보호하기 위해 반도체 칩의 둘레 또는 스크라이브 라인(scribe line)에 칩 제조 공정에 따라 가드 링을 형성한다.In the general semiconductor chip manufacturing process, after the semiconductor chip is manufactured, various reliability evaluation items include a test for durability against humidity under high temperature and pressurization, in which the semiconductor chip is protected to protect the interior of the semiconductor chip against humidity. Guard rings are formed around the chip or on a scribe line according to the chip manufacturing process.

즉, 가드 링이란, 반도체 칩의 평가시 압력이나 온도 또는 습도 등으로부터 반도체 칩의 내부 회로를 보호하기 위한 목적으로 활용된다.That is, a guard ring is utilized for the purpose of protecting the internal circuit of a semiconductor chip from the pressure, temperature, or humidity at the time of evaluation of a semiconductor chip.

도 1은 이러한 가드 링이 형성된 반도체 칩의 평면도로서, 칩(12) 외곽에 형성되어 그라운드 역할을 수행하는 가드 링(10)과, 패드, 입출력 단자, 메인 셀 등으로 구성되는 칩(12)을 포함한다.FIG. 1 is a plan view of a semiconductor chip having such a guard ring, and includes a guard ring 10 formed outside the chip 12 and serving as a ground, and a chip 12 including pads, input / output terminals, and a main cell. Include.

도 2는 도 1의 단면도로서, 가드 링(10a)과 상하부 금속을 연결하는 접속 홀(14)을 도시한 도면이며, 도 3은 가드 링(10a)과 상하부 금속을 연결하는 트렌치 형태의 접속 라인(16)을 도시한 도면이다.FIG. 2 is a cross-sectional view of FIG. 1 and illustrates a connection hole 14 connecting the guard ring 10a and the upper and lower metals, and FIG. 3 is a trench connection line connecting the guard ring 10a and the upper and lower metals. Fig. 16 shows the drawing.

그런데, 이러한 종래의 가드 링(10)으로는 가드 링(10)에 대한 이상 상태를 모니터링할 수 있는 방안이 마련되지 못하였다.However, the conventional guard ring 10 has not been provided with a method for monitoring the abnormal state of the guard ring 10.

따라서, 웨이퍼내 각 위치별 그라운드 상태를 확인할 수 있는 기술이 요망된다.Therefore, a technique for confirming the ground state for each position in the wafer is desired.

본 발명은 상술한 요망에 의해 안출한 것으로, 가드 링 소정 위치에 테스트용 단자를 설치하여 공정 또는 장비의 전기적 모니터링을 구현함으로써, 추가적인 장치나 실험 없이 모든 칩에 대한 모니터링을 구현한 반도체 칩 가드 링의 모니터링 장치를 제공하는데 그 목적이 있다. The present invention has been made in accordance with the above-described requirements, by installing a test terminal at a predetermined position of the guard ring to implement the electrical monitoring of the process or equipment, semiconductor chip guard ring that implements monitoring for all chips without additional devices or experiments Its purpose is to provide a monitoring device.                         

이러한 목적을 달성하기 위하여 본 발명은, 반도체 소자의 칩 외곽의 가드 링에 있어서, 칩의 가드 링에 대한 전기적 데이터를 얻기 위한 가드 링 단자가 구비되는 것을 특징으로 하는 반도체 칩 가드 링의 모니터링 장치를 제공한다.In order to achieve the above object, the present invention provides a monitoring device for a semiconductor chip guard ring, characterized in that a guard ring terminal for obtaining electrical data for the guard ring of the chip is provided in the guard ring on the outer edge of the semiconductor element. to provide.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 4는 본 발명에 따른 테스트용 단자가 구비된 가드 링이 형성된 반도체 칩의 평면도로서, 칩(22), 가드 링(20), 가드 링 단자(24)를 포함한다.4 is a plan view of a semiconductor chip having a guard ring with a test terminal according to the present invention, and includes a chip 22, a guard ring 20, and a guard ring terminal 24.

도시한 바와 같이, 본 발명은, 칩(22)의 외곽을 둘러싸고 있는 가드 링(20)의 일정 부분을 단락시키고, 그 각각의 끝에 테스트용 단자(24)를 설치한 것을 특징으로 한다.As shown in the drawing, the present invention is characterized in that a portion of the guard ring 20 surrounding the outer edge of the chip 22 is short-circuited and a test terminal 24 is provided at each end thereof.

이러한 테스트용 단자(24)는 이후의 칩(22) 테스트시 가드 링(20)에 대한 전기적인 데이터(electrical data)를 얻는데 활용된다. 즉, 도 4에 도시한 2개의 단자(24)에 대한 전류/전압 측정으로 칩(22)의 그라운드 상태를 점검할 수 있다.This test terminal 24 is used to obtain electrical data for the guard ring 20 during subsequent chip 22 testing. That is, the ground state of the chip 22 can be checked by measuring the current / voltage of the two terminals 24 shown in FIG.

이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 그 요지를 벗어나지 않는 범위내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was concretely demonstrated based on the Example, this invention is not limited to this Example, Of course, various changes are possible within the range which does not deviate from the summary.

이상 설명한 바와 같이, 본 발명은 각 칩의 그라운드 상태를 수치화하여 웨이퍼내 각 위치별 그라운드 상태를 확인할 수 있으며, 이를 통해 테스트 신뢰도 및 소자/배선 공정의 문제점들을 용이하게 모니터할 수 있는 효과가 있다.As described above, the present invention can quantify the ground state of each chip to confirm the ground state for each position in the wafer, and thus, it is possible to easily monitor the test reliability and device / wiring problems.

Claims (3)

반도체 소자의 칩 외곽의 가드 링에 있어서,In a guard ring outside the chip of the semiconductor device, 상기 칩의 가드 링에 대한 전기적 데이터를 얻기 위한 가드 링 단자가 구비되는 것을 특징으로 하는 반도체 칩 가드 링의 모니터링 장치.Device for monitoring a semiconductor chip guard ring, characterized in that the guard ring terminal for obtaining electrical data for the guard ring of the chip is provided. 제 1 항에 있어서,The method of claim 1, 상기 가드 링 단자는 일정 부분이 단락된 상기 가드 링의 말단에 형성되는 것을 특징으로 하는 반도체 칩 가드 링의 모니터링 장치.And the guard ring terminal is formed at an end of the guard ring in which a predetermined portion is shorted. 제 1 항에 있어서,The method of claim 1, 상기 장치는,The device, 상기 가드 링 단자에 대한 전류/전압 측정으로 상기 칩의 그라운드 상태를 점검하는 것을 특징으로 하는 반도체 칩 가드 링의 모니터링 장치.And monitoring the ground state of the chip by measuring a current / voltage of the guard ring terminal.
KR1020020021249A 2002-04-18 2002-04-18 Apparatus for monitoring a guard-ring in a semiconductor device KR100688688B1 (en)

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KR100688722B1 (en) * 2002-04-18 2007-02-28 동부일렉트로닉스 주식회사 Apparatus for monitoring a guard-ring in a semiconductor device
KR100889175B1 (en) * 2003-08-12 2009-03-17 주식회사 티이에스 Device and method for rotating flat panel display in vacuum chamber
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KR20030082772A (en) * 2002-04-18 2003-10-23 아남반도체 주식회사 Apparatus for monitoring a guard-ring in a semiconductor device

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