KR100685815B1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device capable of improving image quality by using two or more dither mask patterns in one frame is disclosed. The data signals supplied to the pixel cells or data lines are divided into an odd block and an even block, and the dither mask pattern has the same number of dither values and different dither mask patterns. A scaler capable of dithering signals is provided to reduce dithering noise such as grid noise in an image implementation.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed view of the scaler shown in FIG. 1.

3 is a detailed view of the dithering unit shown in FIG. 2.

FIG. 4 is a diagram illustrating a dither mask pattern stored in the dither mask table shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

102: liquid crystal panel 104: scan driving device

106: data driving device 108: timing control unit

110: scaler 122: analog to digital converter

124: frame memory 126: RGB separator

128: dithering unit 132: data determination unit

134: dither mask selection unit 136: dither mask table

138: adder

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality.

A liquid crystal display (hereinafter referred to as "LCD") displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. When the analog video signal is input from the outside, the LCD converts the digital video signal through the analog / digital converter, and then processes the signal to match the resolution of the liquid crystal display. To this end, in conventional LCDs, digital video signals are processed using a dithering method that adds suitable noise so that the contour noise is inconspicuous.

However, in the conventional LCD, since one dither mask pattern is used in one frame, regular patterning is easily observed, which causes a problem of deterioration in image quality due to grid noise. That is, since dithering is performed for one frame, which is a unit of image data, one dither mask pattern is used. Therefore, when perfect dithering is not performed and the same pattern is displayed at different frames, generation of grid noise is a serious problem. Soybeans.

Accordingly, a liquid crystal display for dithering by dividing a dither mask pattern in one frame will be required.

Accordingly, an object of the present invention is to provide a liquid crystal display device using two or more dither mask patterns in one frame.

In order to achieve the above object, the present invention is a liquid crystal panel for displaying an image; A scan driver for driving gate lines of the liquid crystal panel; A data driver for driving data lines of the liquid crystal panel; A timing controller for controlling the scan driver and the data driver, and supplying red, green, and blue data signals to the data driver; And a scaler which converts each of the red, green, and blue data signals according to the resolution of the liquid crystal panel using a dither mask pattern divided into an odd block and an even block, and supplies them to the timing controller. .

According to the present invention, a dithering noise such as lattice noise generated when one dither mask pattern is used can be removed to obtain a liquid crystal display device having an image quality in which interference in a field of view is removed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

1 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 102 for displaying an image and a scan driver for driving gate lines GL1 to GLn of the liquid crystal panel 102. Timing for controlling the data driver 106, the data driver 106, and the scan driver 104 to drive the data lines DL1 to DLm of the liquid crystal panel 102. The controller 108 has a scaler 110 for converting an analog image signal input from the outside into a data signal suitable for the resolution of the liquid crystal panel 102.

The liquid crystal panel 102 has pixels formed in regions defined by intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm. Each of the pixels includes a liquid crystal cell Clc for adjusting the light transmittance according to a pixel signal, and a thin film transistor (“TFT”) for driving the liquid crystal cell Clc.

The TFT is turned on when a scan signal from the gate lines GL1 to GLn, that is, a gate high voltage VGH is supplied, to convert the data signal from the data lines DL1 to DLm into the liquid crystal cell. Clc). The TFT is turned off when the gate low voltage VGL is supplied from the gate lines GL1 to GLn to maintain the data signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the TFT. The liquid crystal cell Clc further includes a storage capacitor Cst for stably maintaining the charged data signal until the next data signal is charged. The liquid crystal cell Clc realizes gradation by varying an arrangement state of liquid crystals having dielectric anisotropy according to a data signal charged through the TFT and adjusting light transmittance.

The scan driver 104 sequentially applies the gate high voltage VGH to the gate lines GL1 to GLn in response to gate control signals GSP, GSC, and GOE supplied from the timing controller 108. Supply. That is, the scan driver 104 shifts the gate start pulse GSP according to the gate shift clock GSC to generate the shift pulse. In addition, the scan driver 104 supplies the gate high voltage VGH to the corresponding gate lines GL1 to GLn every one horizontal period 1H in response to the shift pulse. At this time, the shift pulse is shifted by one line every 1H period, and the scan driver 104 supplies the gate high voltage VGH to the corresponding gate lines GL1 to GLn in correspondence with the shift pulse. Here, the width of the shift pulse is controlled according to a gate output enable signal (GOE) supplied from the timing controller 108. Here, the scan driver 104 supplies the gate low voltage VGL to the gate lines GL1 to GLn in the remaining period during which the gate high voltage VGH is not supplied. The scan driver 104 includes a plurality of gate drive ICs (Integrated Circuit) for dividing and driving the gate lines GL1 to GLn.

The data driver 106 receives the data signals supplied from the timing controller 108 in response to the data control signals SSP, SSC, SOE, and POL supplied from the timing controller 108. DL1 to DLm). In this case, the data driver 106 supplies data signals to the data lines DL1 to DLm in different ways according to the type of the liquid crystal display. That is, in the liquid crystal display device in which the color filter is formed, data signals of red (R '), green (G'), and blue (B ') supplied from the timing controller 108 are transmitted to the data line during one horizontal period (1H). To DL1 to DLm at the same time. However, in a liquid crystal display device in which no color filter is formed, that is, a field sequential drive type liquid crystal display device, the red (R '), green (G') and The blue B 'data signals are sequentially supplied to each of the data lines DL1 to DLm. At this time, the data driver 106 converts the data signal from the timing controller 108 into an analog pixel signal using a gamma voltage from a gamma voltage generator (not shown) and outputs the analog signal. That is, the data driver 106 generates a sampling signal by shifting the source start pulse SSP supplied from the timing controller 108 according to the source shift clock SSC. Subsequently, the data driver 106 sequentially latches the data signal by a predetermined unit in response to the sampling signal. Thereafter, the latched data signal for one line is converted into an analog pixel signal and supplied to the data lines DL1 to DLm in an enable period of a source output enable signal (SOE). In this case, the data driving device 106 converts the data signal into an analog pixel signal having a positive polarity (+) or a negative polarity (−) in response to the polarity control signal POL supplied from the timing controller 108. Supply to the data lines DL1 to DLm. The data driver 106 includes a plurality of data drive ICs for dividing and driving the data lines DL1 to DLm.

The timing controller 108 uses gate control signals GSP, GSC, and GOE and data control signals SSP, SSC, and SOE using the vertical and horizontal synchronization signals V and H supplied from the scaler 110. , POL). The timing controller 108 controls the driving of the scan driver 104 using the gate control signals GSP, GSC, and GOE supplied to the scan driver 104, and the data driver 106. ) To control the driving of the data driver 106 by using the data control signals SSP, SSC, SOE, and POL. In addition, the timing controller 108 controls the red (R), green (G), and blue (B) data signals supplied from the scaler 110 to red (R '), green (G'), and blue (B ') signals. And rearranges the data signals according to the data signals. In this case, the timing controller 108 may convert the red (R), green (G), and blue (B) data signals supplied from the scaler 110 in different ways according to the type of the liquid crystal display device. The data signals are rearranged to data signals '', 'G' and 'B'. That is, in the liquid crystal display device using the color filter, the timing controller 108 has the red (R), green (G), and blue (B) data signals supplied from the scaler 110 in one horizontal period. Rearrange the data signals of red (R), green (G) and blue (B) to be supplied to one pixel cell, i.e., each of the subpixels of red (R), green (G) and blue (B) during 1H. do. However, in a liquid crystal display device that does not use a color filter, that is, a field sequential drive type liquid crystal display device, the timing controller 108 may supply the red (R), green (G), and blue (B) supplied from the scaler 110. The data signals of red (R), green (G), and blue (B) are rearranged so that the data signals of?) Are sequentially supplied to one pixel cell during one horizontal period (1H).

The scaler 110 converts an analog video signal input from the outside into a digital video signal RGB and converts the converted digital video signal RGB into red (R), green (G), and blue (B), respectively. After separating into a data signal of the liquid crystal panel 102 is converted to match the resolution. At this time, the scaler 110 divides each of the red (R), green (G), and blue (B) data signals into an odd block and an even block, and each dither mask pattern is different for each block. After dithering and converting to match the resolution of the liquid crystal panel 102, the converted red (R), green (G), and blue (B) data signals are supplied to the timing controller 108.

2 is a block diagram illustrating the scaler shown in FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 2, the scaler 110 includes an analog-to-digital converter 122, a frame memory 124, an RGB separator 126, and a dithering unit 128.

The analog / digital converter 122 converts an analog video signal input from the outside into a digital video signal RGB.

The frame memory 124 stores the digital video signal RGB converted by the analog / digital converter 122 in units of one frame.

The RGB separator 126 separates the video signal RGB stored in the frame memory 124 into data signals of red (R), green (G), and blue (B), respectively.

The dithering unit 128 determines whether the red (R), green (G) and blue (B) data signals input from the RGB separator 126 are odd data or even data. Determine whether or not. The odd data refers to data supplied to odd-numbered pixel cells or odd-numbered data lines DL1, DL3,..., DLm-1, and the even data refers to even-numbered pixel cells or even-numbered data lines. It refers to the data supplied to the fields DL2, DL4, ..., DLm.

In addition, the dithering unit 128 uses the dithering method using a dither mask pattern having the same number of dither values in the odd data and even data and having different dither values. ), Green (G) and blue (B) data signals are converted to match the resolution of the liquid crystal panel 102 and supplied to the timing controller 108.

3 is a block diagram illustrating a dithering unit illustrated in FIG. 2 according to an embodiment of the present invention.

Referring to FIG. 3, the dithering unit 128 includes a data determining unit 132, a dither mask selecting unit 134, a dither mask table 136, and an adder 138.

The data determination unit 132 determines whether the data input from the RGB separator 126 is odd data or even data, and supplies a control signal according to the determination result to the dither mask selection unit 134. That is, the data determining unit 132 supplies an odd signal OS to the dither mask selector 134 when the pixel data input from the RGB separator 126 is odd data, and if the pixel data input from the RGB separator 126 is odd data, ES) is supplied to the dither mask selector 134. The data determination unit 132 alternately supplies the odd signal OS and the even signal ES to the dither mask selection unit 134.

The dither mask selecting unit 134 selects a plurality of dither mask patterns stored in the dither mask table 136 according to the control signals OS and ES supplied from the data determining unit 132. That is, when the odd signal OS is supplied from the data determination unit 132, the dither mask selecting unit 134 selects one of the dither mask patterns stored in the odd block of the dither mask table 136. When the even signal ES is supplied, one of the dither mask patterns stored in the even block of the dither mask table 136 is selected. In this case, the dither mask patterns stored in the odd block and the even block are alternately selected. That is, when the odd signal OS and the even signal ES are inputted alternately, the dither mask selector 134 alternately selects the dither mask pattern stored in the odd block and the dither mask pattern stored in the even block. The dither mask patterns stored in the odd block and the even block are sequentially selected from left to right or right to left.

The dither mask table 136 detects horizontal and vertical lines, i.e., positions of cells, from the data signals of red (R), green (G), and blue (B) supplied from the RGB separator 126. The dither value D present at the position of the cell detected in the dither mask pattern selected by the dither mask selection unit 134 is supplied to the adder 138. The dither mask table 136 is divided into an odd block and an even block as shown in FIG. 4, and in each block, the number of cells in which the dither value is set to "1" is the same, and the positions of the dither values are different from each other. Another dither mask pattern is stored. At this time, the dither mask pattern has a cell (subpixel) size of 4 × 4. Here, the positions of the cells in which the dither value is set to "1" may be variously changed according to the needs of the designer. The number of cells for which the dither value is set to "1" depends on the gray level of the data signals of red (R), green (G), and blue (B). That is, when the red (R), green (G), and blue (B) data signals are high gray, the number of cells in which the dither value is set to "1" increases, and in the low gray level, the dither value is set to "1". The number of cells decreases. In the dither mask table 136 of the present invention, only the dither mask pattern having four dither values of "1" is disclosed, but the dither mask pattern having different dither values of "1" also has the dither mask table ( It will be appreciated that it is stored at 136). According to the dither mask pattern, the position of the on cell whose dither value corresponds to "1" is spatially controlled.

The adder 138 is connected between the RGB separator 126, the timing controller 108, and the dither mask table 136 to convert the dither value D supplied from the dither mask table 136 to the RGB separator. The timing controller controls 7-bit pixel data corrected by adding a carry signal to the remaining data signals except the lower 1 bit of the red (R), green (G), and blue (B) data signals supplied from 126. To 108.

As described above, the liquid crystal display according to the present invention divides data signals supplied to pixel cells or data lines into an odd block and an even block, and the number of cells having a dither value of "1" in each block is equal and The positions of the further values can be prevented from repeating the constant dither mask pattern in the odd block and even block for one frame by dithering the data signals using different dither mask patterns. For this reason, the liquid crystal display according to the present invention can improve image quality by reducing dithering noise such as lattice noise.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (5)

A liquid crystal panel for displaying an image; A scan driver for driving gate lines of the liquid crystal panel; A data driver for driving data lines of the liquid crystal panel; A timing controller for controlling the scan driver and the data driver, and supplying red, green, and blue data signals to the data driver; And And a scaler which converts each of the red, green, and blue data signals according to the resolution of the liquid crystal panel using the dither mask pattern divided into an odd block and an even block, and supplies them to the timing controller. The method of claim 1, The scaler is, An analog / digital converter for converting an analog video signal input from the outside into a digital video signal; A frame memory for storing the digital video signal supplied from the analog / digital converter in units of frames; An RGB separator for separating the digital video signal stored in the frame memory into red, green, and blue data signals, respectively; And a dithering unit configured to dither the red, green, and blue data signals separated by the RGB separator using dither mask patterns divided into the odd block and even block. Device. The method of claim 2, The dithering unit, A data determination unit for determining whether the red, green, and blue data signals are odd data or even data; A dither mask table in which the number of cells having a dither value of "1" is the same and the dither values have different dither mask patterns divided into an odd block and an even block; A dither mask selecting unit for selecting the dither mask patterns present in the odd block and the even block according to the determination result of the data discriminating unit; And an adder for adding the red, green, and blue data signals and the dither value supplied from the dither mask table. The method of claim 3, wherein And the number of cells having the dither value "1" varies according to the gradation of the red, green, and blue data signals. The method of claim 4, wherein The number of cells having the dither value of "1" increases as the gray level of the red, green, and blue data signals increases.

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