KR100685091B1 - Trench Type Transistor and The Method for Manufacturing the Same - Google Patents

Abstract

 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench type transistor and a method of manufacturing the same, and more particularly, electrically connected to a source electrode through an opening in which a body of the termination region is formed in the bus line in the termination region around the active region. This reduces the resistance component in the body of the termination region, and minimizes the generation of heat caused by the resistance component of the body in the termination region when an avalanche current flows in the parasitic diode region of the body junction. The present invention relates to a trench type transistor capable of preventing thermal breakdown from occurring in a region and increasing the reliability of the transistor.

Trench MOSFET, avalanche breakdown, termination area, body resistor

Description

Trench Type Transistor and The Method for Manufacturing the Same

1 is a partial schematic plan view showing a conventional trench transistor.

FIG. 2 is a cross-sectional view taken along the line a-a of FIG. 1.

3 is a cross-sectional view taken along the line b-b of FIG.

4 is a partial schematic plan view of a trench transistor according to an embodiment of the present invention.

5 is a cross-sectional view taken along the line AA of FIG. 4.

FIG. 6 is a sectional view taken along the line BB of FIG. 4.

7 is a cross-sectional view taken along the line C-C in FIG.

8A to 8M are sequential explanatory diagrams showing a method of manufacturing a trench transistor according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

10-drain electrode 20-semiconductor substrate

30-Drain Area 40-Body

50-Source Area 60-Trench

70-gate oxide 80-polysilicon gate

90-oxide 100-source electrode

110-gate electrode 120-termination region

130-Busline

 The present invention relates to a transistor and a method of manufacturing the same. More particularly, in a termination region around an active region, the body of the termination region is electrically connected to a source electrode through an opening formed in a bus line. The resistance component in the body of the termination region is reduced, and when the avalanche current flows in the parasitic diode region of the body junction, the generation of heat by the resistance component of the body of the termination region is minimized. The present invention relates to a trench type transistor capable of preventing breakdown due to heat and increasing the reliability of the transistor.

In general, trench type field effect transistors are high-current power devices, and instead of conventional horizontal gates, trenches are formed vertically on the substrate and oxide films are formed on the sides of the trenches to form vertical gates, which is very advantageous for large currents and high integration. Say. Such trench type field effect transistors have a maximum operating voltage and driving current of several tens of V / s and several tens of class A, which can minimize power loss, which is the maximum requirement of a mobile communication device, and has a merit of significantly lowering the production cost through fixed simplicity.

Referring to FIG. 1, a partial schematic plan view of a conventional trench transistor is shown, and referring to FIG. 2, a cross-sectional view of the line aa of FIG. 1 is illustrated, and FIG. 3 is a cross-sectional view of the bb line of FIG. 1. It is.

The trench transistor is, as shown, a drain electrode 10 ', an N + type substrate 20' formed on the drain electrode 10 ', and an N- type formed on the N + type substrate 20'. A drain region 30 ', a P-type body 40' formed over the N-type drain region 30 ', an N + -type source region 50' partially formed over the P-type body 40 ', A trench 60 'formed at a predetermined depth in the source region 50', the P-type body 40 ', and the drain region 30', and a gate oxide film formed on an inner surface of the trench 60 '. 70 '), a polysilicon gate 80' filled inside the gate oxide film 70 'of the trench 60', an oxide film 90 'formed on the polysilicon gate 80', and the plurality of The source electrode 100 'connecting the source region 50' of the transistor, the common gate electrode 110 'formed in the termination region 120' so that the polysilicon gate 80 'is connected, and the common gate electrode. It consists including 110 'and the polysilicon gate (80' bus line (130 ') for electrically connecting a).

Such conventional trench transistors can be roughly classified into an equilibrium state, an off state without a drain-source voltage applied, and an on state with a drain-source voltage applied. E.g. It turns on when the gate-source voltage is greater than the transistor threshold voltage and the drain-source voltage is greater than 0V. That is, the trench transistor is an N-type channel connecting the source region 50 'and the drain region 30' to the P-type body 40 'adjacent to the gate oxide film 70' when a predetermined voltage is applied to the gate. It is formed and operated while being challenged.

In particular, when the trench-type transistor is used in a circuit including an inductive load, the energy accumulated in the inductive load when converted from the on state to the off state is in the form of an avalanche current. Flow is from the drain electrode to the source electrode through the parasitic diode region of the body junction of the transistor. At this time, such a current increases the flow of current by operating the parasitic diode by increasing the voltage according to the resistance component of the body region to generate heat due to energy consumption.

On the other hand, in the conventional trench-type transistor, the source electrode is formed only in the active region to be in electrical contact with each other at a distance from the body of the active region. However, as shown in FIG. 3, the source electrode is not formed in the termination region, and the body formed in the termination region is electrically connected to the source electrode through a relatively long path so that a current flows. Therefore, since the path of the avalanche current becomes longer in the body formed in the termination region during avalanche breakdown, heat is generated by the resistance component of the body which increases relatively. There is a problem.

 The present invention to solve the above problems in the termination region around the active area (termination) in the body of the termination region so that the body of the termination region is electrically connected to the source electrode through an opening formed in the bus line When the avalanche current flows in the parasitic diode region of the body junction, heat destruction occurs in the termination region by minimizing the generation of heat by the resistance component of the body of the termination region. SUMMARY OF THE INVENTION An object of the present invention is to provide a trench type transistor and a method of manufacturing the same, which can prevent the transistor from being increased and improve the reliability of the transistor.

The trench-type transistor of the present invention for solving the above problems is a drain electrode, a semiconductor substrate positioned on the drain electrode, a drain region formed on the semiconductor substrate, a body formed on the drain region, and partially on the body A plurality of source regions formed in the plurality of source regions, trenches having a predetermined depth in the plurality of source regions, the body and the drain region, a gate oxide film formed to cover the trench and a portion of the outer surface thereof, and a surface of the gate oxide film in the trench. A polysilicon gate formed on the substrate, a bus line formed on the drain region and the body in a termination region and connected to the polysilicon gate, an oxide film formed on the body of the polysilicon gate, the bus line and the termination region; A source electrode connecting the plurality of sources, and the burr A trench transistor comprising a gate electrode electrically connected to the polysilicon gate by a line, wherein the body of the termination region is electrically connected to the source electrode through an opening formed in the bus line. .

In this case, a source electrode through hole penetrating into the body of the termination region may be formed in an inner region of the opening.

The source electrode may be insulated by an oxide film and extend to an upper region of the opening to be directly connected to the body through the source electrode through hole.

The openings may be formed at predetermined intervals along the direction in which the gate electrode is formed on the body of the termination region, and may be formed in a substantially rectangular shape. In addition, the opening may be formed to open in the polysilicon gate direction.

In addition, the polysilicon gate is formed in a horizontal direction and at least one first gate extending in parallel with a predetermined distance from the front and rear sides of the opening and at least one second gate extending to a predetermined distance on one side of the opening and the It may be formed including a connection gate connecting the first gate and the second gate.

In addition, the method of manufacturing a trench transistor of the present invention includes the steps of forming a trench in a drain region on a semiconductor substrate with a predetermined depth, forming a gate oxide film in a predetermined thickness on the trench and the entire outside thereof, Forming a polysilicon gate having a predetermined thickness on the outside thereof, etching and removing the polysilicon gate outside the trench, forming a body at a predetermined depth in the drain region outside the trench, and Forming a bus line having a predetermined thickness on the drain region, the body and the polysilicon, and including a opening in a predetermined region of the upper body of the termination region; Source electrode through-holes are formed on the predetermined area of the body and have a predetermined thickness. And forming a source electrode connected to the body of the termination region, a drain electrode formed on the bottom surface of the semiconductor substrate, and a gate electrode connected to the polysilicon gate.

In addition, the forming of the bus line may be performed such that the opening is formed at predetermined intervals along the direction in which the gate electrode is formed between the gate electrode and the side end of the polysilicon gate. In this case, the opening may have a substantially rectangular shape, and may be formed to be open in the polysilicon gate direction.

The forming of the source electrode may be performed so that the source electrode is insulated by an oxide film and extends to an upper region of the opening to be directly connected to the body through the source electrode through hole.

Hereinafter, a trench transistor according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a partial schematic plan view illustrating a trench transistor according to an embodiment of the present invention, FIG. 5 is a sectional view taken along the line A-A of FIG. 4, FIG. 6 is a sectional view taken along the line B-B of FIG. Shows C sectional drawing of FIG.

4 through 7, the trench transistor according to the embodiment of the present invention includes a drain electrode 10, a semiconductor substrate 20 positioned on the drain electrode 10, and the semiconductor substrate 20. ), A drain region 30 formed on the top surface, a body 40 formed on the drain region 30, a plurality of source regions 50 partially formed on the body 40, and the plurality of source regions 50. A trench 60 formed to a predetermined depth in the body 40 and the drain region 30, a gate oxide film 70 covering the trench 60 and a portion of an outer surface thereof, and a gate in the trench 60. The polysilicon gate 80 formed on the surface of the oxide film 70 and the drain region 30 and the body 40a in the termination region 120 are formed on the polysilicon gate 80 and connected to the polysilicon gate 80. A bus line 130 including an opening 132 formed in the gate and the polysilicon gate An oxide film 90 formed on the bus line 130 and the body 40a of the termination region, and the body 40a which connects the plurality of source regions 50 and is formed in the termination region 120. And a source electrode 100 electrically connected through the opening of the bus line 130, and a gate electrode 110 connected to the polysilicon gate 80 by the bus line 130. .

The trench transistor has an active body in which current flows from the drain electrode 10 to the source electrode 100 by forming the body 40, the source region 50, and the polysilicon gate 80 on a horizontal plane. An active region and the bus line 130 are formed to be divided into a termination region 120 where voltage is applied to the polysilicon gate 80 from the gate electrode 110 through the bus line 130. Can be. Thus, the termination region 120 is formed around the active region.

The drain electrode 10 may be formed of ordinary aluminum (Al), gold (Au), silver (Ag), palladium (Pd), and the like, but the material is not limited thereto.

The semiconductor substrate 20 may be a conventional N + type (or P + type, which will be described based on an N-channel FET in the following description). As is well known, an N + type semiconductor substrate is made of N type impurities in the process of forming a single crystal ingot.

The drain region 30 is formed by an epitaxial process on the semiconductor substrate 20, and may be formed of an N-type epitaxial layer. As is well known, the N-type drain region 30 is grown by injecting an N-type impurity gas and a silicon gas together on the semiconductor substrate 20.

The body 40 is formed by implanting P-type impurities on the drain region 30. In addition, the body 40 is formed to include a body 40a of the termination region formed in the termination region 120. Of course, the P-type body 40 is formed after the trench 60 is formed as described below, but will be described in the stacking order for the understanding of the structure. The body 40a of the termination region is electrically connected to the source electrode 100 through the opening 132 of the bus electrode 130.

The source region 50 is formed by partially implanting N-type impurities into a portion of the body 40. The concentration of N-type impurities in the source region 50 is N +.

The trench 60 is formed at a predetermined depth in the plurality of source regions 50, the bodies 40, 40a, and the drain region 30. That is, the trench 60 penetrates through the bodies 40 and 40a to a predetermined depth of the drain region 30. The trench 60 may be formed in a stripe shape and may also be formed in a cell shape.

The gate oxide layer 70 is formed to cover the trench 60 and a part of the outer surface thereof.

The polysilicon gate 80 includes N-type impurities and is formed on the surface of the gate oxide layer 70 in the trench 60. That is, the polysilicon gate 80 is formed at a predetermined height inside the gate oxide film 70 formed in the trench 60. In this case, the polysilicon gate 80 may be insulated from the source region 50 and the body 40 by the gate oxide layer 70. The polysilicon gate 80 may be formed in a stripe shape according to the shape of the trench 60, and may be formed in a cell shape according to the shape of the trench.

In addition, the polysilicon gate 80 extends in a horizontal direction in a stripe shape, and is spaced apart from the front and rear sides 132a and 132b of the opening 132 formed in the bus line 130 by a predetermined distance in a vertical direction. At least one first gate 82 extending to a predetermined region and at least one second gate 84 extending to a predetermined distance on one side of the opening 132, and the first gate 82 and the second gate 84. It may be formed including a connecting gate 86 for connecting. The first gate 82 extends to a predetermined area of the front and rear sides 132a and 132b of each of the openings 132 to contact the bus line 130 with a larger area. In addition, the second gate 84 is formed by extending a predetermined length into the opening 132 from one side of the opening 132. Therefore, the side end of the second gate 84 is located in the region of the opening 132. In addition, the connection gate 86 is connected to the second gate 84 inside the opening 132.

In the polysilicon gate, the first gate 82 and the second gate 84 have the same length, and side ends of the first gate 82 and the second gate 84 are connected to the connection gate ( Of course, it can be formed to be connected by 86).

The bus line 130 is formed to be electrically connected to the polysilicon gate 80 in the termination region 120. That is, the bus line 130 is insulated from the drain region 30 and the body 40a of the termination region by the gate oxide layer 70, and the body 40a and the termination of the drain region 30 and the termination region are terminated. It is formed over the polysilicon gate 80 in the region.

In addition, the bus line 130 is formed to include an opening 132 formed in the upper portion of the body 40a of the termination region. The bus line 130 is insulated from the drain region 30 and the body 40a of the termination region by the gate oxide layer 70 in the region where the opening 132 is formed, and the upper portion of the drain region 30. And a portion of the upper portion of the body 40a of the termination region.

The opening 132 is formed between the gate electrode 110 and the side end of the polysilicon gate 80, and an inner surface thereof is covered with a predetermined thickness by the oxide film 90. The openings 132 are formed at predetermined intervals along the direction in which the gate electrodes 110 are formed in the termination region 120, and are formed in a substantially rectangular shape. However, the shape of the opening 132 is not limited thereto, but may be formed in various shapes such as a circle, a triangle, and a hexagon. In addition, the opening 132 may be formed to be open toward the polysilicon gate 80. In this case, the bus line 130 may be more easily formed in a region where the opening 132 is formed. Can be formed.

The oxide layer 90 is formed by depositing a predetermined thickness on the polysilicon gate 80, which insulates the polysilicon gate 80 and the source electrode 100 from each other. In addition, the oxide film 90 is formed on the bus line 130 and the body 40a of the termination region in the termination region 120. The oxide layer 90 has a source electrode through hole 92 penetrating the body 40a of the termination region from the inner region of the opening 132, that is, a portion of the body 40a of the termination region. Is formed. That is, the opening 132 is coated with an oxide film 90 having a predetermined thickness between inner surfaces thereof to form the source electrode through hole 92 in an inner region. The source electrode through hole 92 is formed by extending the source electrode 100 therein, and the body 40a of the termination region is directly and electrically connected to the source electrode 100. The source electrode through hole 92 is preferably formed in a shape corresponding to the shape of the opening 130, but is not limited thereto.

In addition, the oxide layer 90 may further include a gate electrode through hole 94 positioned above the bus line 130 to electrically connect the bus line 130 and the gate electrode 110. do. Therefore, the gate electrode 110 is electrically connected to the bus line 130 through the gate electrode through hole 94.

The source electrode 100 electrically connects the plurality of source regions 50 by, for example, a metal such as aluminum, and the upper portion of the body 40 and the oxide layer to be insulated from the polysilicon gate 80. It is formed to a predetermined thickness over the top of 90.

In addition, the source electrode 100 extends to an upper portion of the termination region 120, in particular, an area in which the opening 132 of the bus line is formed. In addition, the source electrode 100 is formed to extend into the source electrode through hole 92 of the oxide film 90 formed in the inner region of the opening 132 to be directly connected to the body 40a of the termination region. do. Accordingly, when the avalanche current flows, the body 40a of the terminal region flows current through a short path to the source electrode 100 formed to extend to the terminal region, thereby generating heat in the body 40a of the terminal region. Can be minimized.

Meanwhile, the source electrode 100 does not extend to the body 40a of the termination region, and the body 40a of the termination region is the source electrode 100 by a separate electrode formed through the opening 132. Of course, it can be electrically connected to).

The gate electrode 110 is connected to the bus line 130 through the gate electrode through hole 94 and is electrically connected to the polysilicon gate 80. The gate electrode 110 may be generally formed of ordinary aluminum, and the material of the gate electrode 110 is not limited thereto.

Next, a method of manufacturing a trench transistor according to an embodiment of the present invention will be described. 8A to 8H sequentially illustrate a method of manufacturing a trench transistor according to an embodiment of the present invention. Hereinafter, a description will be given focusing on the termination region 120 in which the bus line 130 is formed. In addition, since the termination region and its shape change are similar to those of the active region, descriptions and drawings of the active region will be omitted. In addition, since the method of forming the semiconductor substrate 20 and the drain region 30 is similar to the conventional method, description thereof is omitted.

As illustrated, the method of manufacturing a trench transistor according to the present invention includes forming a trench 60, forming a gate oxide layer 70, forming a polysilicon gate 80, and etching a polysilicon gate 80. And forming the body 40, forming the bus line 130, forming the oxide film 90, and forming the source electrode 100, the drain electrode 10, and the gate electrode 100.

In the trench 60 forming step, as shown in FIG. 8A, first, a mask is formed on an area except the region where the trench 60 is formed on the drain region 30 on the semiconductor substrate 20, and then drained. The region 30 is etched to a certain depth.

As illustrated in FIG. 8B, the gate oxide layer 70 may be formed by forming a gate oxide layer 70 having a predetermined thickness on the trench 60 and the entire outside thereof.

As shown in FIG. 8C, the polysilicon gate 80 may be formed by forming the trench 60 and the polysilicon gate 80 containing N-type impurities having a predetermined thickness on the outside thereof.

The etching of the polysilicon gate 80 may be performed by etching all of the polysilicon gates outside the trench 60 except for the polysilicon gate 80 inside the trench 60, as shown in FIG. 8D. Is done.

As illustrated in FIG. 8E, the body 40 may be formed by ion implanting P-type impurities into the drain region 30 to a predetermined depth. The body 40 is formed in an outer region of the trench 60. Although not shown, the body 40 is ion-implanted with N-type impurities to a predetermined region to form a source region 50.

As illustrated in FIG. 8F, the bus line 130 may be formed to have a predetermined thickness on the drain region 30, the body 40a, and the polysilicon gate 80 in the termination region. In this case, the bus line 130 is insulated from the drain region 30 and the body 40a of the termination region by the oxide film 90. In addition, the bus line 130 may include the opening 130 formed in a predetermined region above the body 40a of the termination region.

As illustrated in FIG. 8G, the oxide film 90 may be formed by depositing a silicon oxide film having a predetermined thickness on the polysilicon gate 80, the body 40a of the termination region, and the bus line 130. The oxide film 90 insulates the polysilicon gate 80 from the source electrode 100. In addition, the oxide layer 90 may include a source electrode through hole 92 in which the source electrode 100 is connected to the body 40a of the termination region, and a gate electrode 110 in connection with the bus line 130. A gate electrode through-hole 94 is formed. The source electrode through hole 92 is formed in an inner region of the opening 132, and the gate electrode through hole 94 is formed on the bus line 130. The source electrode through hole 92 and the gate electrode through hole 94 may be formed through a separate etching process or may be formed through masking during the formation of an oxide film.

In the forming of the electrode, as shown in FIG. 8H, the source electrode 100 is formed by connecting the plurality of source regions 50 to an aluminum metal, and an aluminum material is formed on the bottom surface of the semiconductor substrate 20. A drain electrode 10 is formed by depositing a metal, and a gate electrode 110 is formed by depositing a metal of an aluminum material at an end of the polysilicon gate 80. In this case, as described above, the source electrode 100 is formed to extend above the body 40a of the termination region. In particular, the source electrode 100 extends into the source electrode through hole 92 to directly contact the body 40a of the termination region. It is formed to be electrically connected.

As described above, the present invention is not limited to the specific preferred embodiments described above, and any person having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention claimed in the claims. Various modifications are possible, of course, and such changes are within the scope of the claims.

 According to the trench transistor according to the present invention and a method of manufacturing the same, in the trench transistor, the body of the termination region is electrically connected to the source electrode directly through an opening formed in the bus line, thereby reducing the resistance component of the body of the termination region. When the avalanche current flows in the parasitic diode region of the coupling, heat generated in the body of the termination region is minimized, thereby preventing thermal destruction in the termination region and increasing the reliability of the transistor.

Claims (12)

A drain electrode, a semiconductor substrate positioned on the drain electrode, a drain region formed on the semiconductor substrate, a body formed on the drain region, a plurality of source regions partially formed on the body, the plurality of source regions and a body A trench formed at a predetermined depth in the drain region, a gate oxide film formed to cover the trench and a portion of the outer surface of the trench, a poly silicon gate formed on a surface of the gate oxide film in the trench, and a drain region at the termination region; A bus line formed on the body and connected to the poly silicon gate, an oxide film formed on the poly silicon gate, the bus line, and an upper body of the termination region, a source electrode connecting the plurality of sources, and the bus line Is electrically connected to the polysilicon gate by In the trench transistor including a bit electrode, And a body of the termination region is electrically connected to the source electrode through an opening formed in the bus line. The method of claim 1, And a source electrode through hole formed through the oxide film in the inner region of the opening. The method according to claim 1 or 2, And the source electrode is insulated by an oxide film and extended to an upper region of the opening to be directly connected to the body through the source electrode through hole. The method of claim 3, wherein And the openings are formed at predetermined intervals along the direction in which the gate electrode is formed on the body of the termination region. The method of claim 3, wherein And the opening is formed in a rectangular shape. The method of claim 3, wherein And the opening is formed in the polysilicon gate direction. The method of claim 3, wherein And the polysilicon gate is formed in a stripe shape. The method of claim 7, wherein The polysilicon gate is formed in a horizontal direction and at least one first gate extending in parallel with a predetermined distance from the front and rear sides of the opening, at least one second gate extending to a predetermined distance on one side of the opening, And a connection gate connecting the first gate and the second gate. Forming a trench at a predetermined depth in the drain region over the semiconductor substrate; Forming a gate oxide layer on the trench and the entire outside thereof to a predetermined thickness; Forming a polysilicon gate of a predetermined thickness on the trench and the outside thereof; Etching away the polysilicon gate outside the trench; Forming a body to a predetermined depth in the drain region outside the trench; Forming a bus line having a predetermined thickness on the drain region, the body and the polysilicon in a termination region, and including an opening in a predetermined region above the body of the termination region; Forming an oxide film having a predetermined thickness on a predetermined region of the body of the polysilicon gate, the bus line, and the termination region, and including an source electrode through hole in an inner region of the opening; Forming a source electrode connected to the body of the termination region, a drain electrode formed on the bottom surface of the semiconductor substrate, and a gate electrode connected to the polysilicon gate. The method of claim 9, The forming of the bus line may include the openings being formed at predetermined intervals along the direction in which the gate electrode is formed between the gate electrode and the side ends of the polysilicon gate. The method of claim 9, The opening is formed in a rectangular shape, the method of manufacturing a trench transistor, characterized in that the opening is formed in the polysilicon gate direction. The method of claim 9, The forming of the source electrode is a method of manufacturing a trench transistor, characterized in that the source electrode is insulated by an oxide film and extending to the upper region of the opening to be directly connected to the body through the source electrode through hole.

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