KR100682830B1 - Lock detector and delay locked loop including the same - Google Patents

Abstract

A lock detector and a delay locked loop having the same are provided to reduce influence of a noise and detect a stable lock state by detecting a lock state when an output signal is sufficiently stable through delay signals outputted from each unit delayer of a voltage control delay line. A lock detector includes a lock detection unit(220), and a bias unit(210). The lock detection unit(220) has a charging unit(224). The lock detection unit(220) controls charge and discharge of the charging unit(224) by using control signals generated based on a plurality of delay signals inputted from an external voltage control delay line and a reference signal inputted from the outside. The lock detection unit(220) detects a lock state based on an electric potential of the charging unit(224). The lock detection unit(220) has the bias unit(210) which provides a bias source to control the charge and discharge of the charging unit(224).

Description

LOCK DETECTOR AND DELAY LOCKED LOOP INCLUDING THE SAME}

1 is a block diagram showing the configuration of a typical delay lock loop.

FIG. 2 is a graph showing a change in the control voltage signal of the delay lock loop shown in FIG.

3 is a timing diagram showing the flow of the main signal in the slow region of the delay lock loop.

4 is a timing diagram showing the flow of the main signal in the fast region of the delay lock loop.

5 is a timing diagram showing the flow of the main signal in the lock region of the delay lock loop.

6 is a block diagram showing the configuration of a delayed synchronization loop provided with a lock detector according to a preferred embodiment of the present invention.

FIG. 7 is a circuit diagram showing the circuit configuration of the lock detector according to the preferred embodiment of the present invention shown in FIG.

FIG. 8 is a detailed circuit diagram showing the circuit configuration of the lock signal output unit shown in FIG.

FIG. 9 is a timing diagram for describing an operation in a lock section of the lock detector illustrated in FIG. 7.

Fig. 10 is a chart showing the output values of the exclusive Noa operation and the exclusive Noa operation.

FIG. 11 is a timing diagram for describing an operation in a slow section of the lock detection unit illustrated in FIG. 7.

12 is a timing diagram for describing an operation of a lock signal output unit when a normal reference signal is input.

13 is a timing diagram for describing an operation of a lock signal output unit when an abnormal reference signal is input.

14 is a timing diagram for describing an operation of a lock signal output unit when an abnormal reference signal is input.

<Description of the symbols for the main parts of the drawings>

200: lock detector

210: bias part

220: lock detection unit

221: charging control unit

222: discharge control

223 unlock control

224: charging unit

225: lock ready signal output unit

227: charge control signal generator

228: unlock signal generation unit

240: lock signal output unit

The present invention relates to a lock detector and a delay locked loop (DLL) having the same. More specifically, a stable lock using analog charge and discharge operations using a plurality of delay signals. The present invention relates to a lock detector for detecting a state and a delay lock loop having the same.

Generally, a delay lock loop is a device for generating an internal clock signal synchronized with an external clock signal using an external clock signal input from the outside.

These delay locked loops, as well as phase locked loops (PLLs), are single-phase and multi-phase clock generators, and are widely used in communication systems and control systems that require clock recovery, frequency synthesis, signal modulation or demodulation, and the like. .

For example, a cache memory device ('SRAM' or the like is used) for improving data processing speed between the CPU and the dynamic random access memory (DRAM), various logic circuits, and synchronous DRAM. (Synchronous DRAM) and Rambus DRAM.

Typically, such a delay synchronization loop includes a delay block capable of changing a signal, and compares a feedback signal of an input signal with a feedback signal of an output signal and controls the delay unit in a direction in which two signals can be synchronized. It has a structure that changes.

At this time, the reference signal and the feedback signal do not match at the initial stage of the operation of the delay synchronization loop and when the unstable state is reached, the feedback signal is stably synchronized with the reference signal. This state is called lock. In other words, the locked state means that the output is stabilized with respect to the input signal.

In the delay lock loop, it is very important to accurately determine the lock state. This is because, if the lock state is not correctly determined, the reliability of the delayed synchronization loop itself is not only degraded, but also has a great effect on a device using the output of the delayed synchronization loop as a clock signal.

Therefore, in the delay lock loop, a lock detector capable of accurately determining the lock state is required.

In the conventional lock detector, a lock detector in the form of digital logic having a plurality of logic elements is mainly used, similar to a lock detector of a phase locked loop. This is disclosed in Korean Patent Laid-Open Publication No. 2003-27507 and Korean Patent Laid-Open Publication No. 005-41730.

Such a digital lock detector includes a plurality of logic elements such as an AND gate, a Nand gate, an inverter, or the like to configure digital logic for detecting a lock state. do.

However, since the digital logic is greatly influenced by the environment, especially PVT (Process, Voltage, Temperature) due to its characteristics, a number of logic elements provided in the delay synchronization circuit may cause noise. Can generate an action.

For example, it may be determined that the output signal is locked even when it is not sufficiently stabilized, or the case where the state of the output signal is changed due to an abnormal input signal may occur. This results in a problem of degrading the reliability of the delay synchronization circuit requiring precise operation.

In addition, the excessive use of logic elements may increase the size of the circuit itself, resulting in a decrease in the density of the chip, and there is also a problem that consumes a lot of power to drive the circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and a first object of the present invention is to provide a lock detector of a delay lock loop capable of detecting a stable lock state in an analog manner by using delay signals output from a plurality of unit delayers. There is.

It is also a second object of the present invention to provide a delay locked loop having the lock detector.

The lock detector of the delay lock loop according to the present invention for achieving the first object of the present invention is controlled by using a reference current input from the outside and a plurality of delay signals input from the external voltage control delay line (VCDL). A lock detector configured to generate signals, control a charging current of a charging unit provided therein using the generated control signals, and detect a locked state using a potential charged in the charging unit; And a bias unit for providing the charging current to the charging unit of the lock detection unit.

In this case, the input delay signals may include a first delay signal, a second delay signal, a third delay signal, a fourth delay signal, a fifth delay signal, a sixth delay signal, and a seventh delay. Contains a signal. Each delay signal is sequentially output from the seven unit delay units provided in the voltage control delay line.

The lock detection unit, the charging unit; A charge control signal generator configured to generate a charge control signal using the reference signal and the third delay signal; A charging controller configured to charge a current equal to a first current for a unit time in the charging unit in response to the charging control signal generated by the charging control signal generator; A discharge controller configured to discharge a current equal to a second current during the unit time to the charger in response to the charge control signal generated by the charge control signal generator; And a lock ready signal output unit configured to output a lock ready signal when the lock state is detected by a current charged in the charging unit.

Preferably, the charge control signal generator is an exclusive NOR gate that receives the reference signal and the third delay signal. Therefore, the charging control signal has a high level when the reference signal and the third delay signal have the same level, and has a low level when the reference signal and the third delay signal have different levels.

The charge control unit and the discharge control unit are connected in series between a power supply voltage and a ground terminal, a lock determination node is formed at the connection point, and the charging unit is connected in parallel to the lock determination node.

The charging control unit may include: a charge control MOS transistor connected to the power supply voltage and turned on by an inverted signal of the charge control signal; And a first bias MOS transistor connected in series between the charge control MOS transistor and the lock decision node, the first bias MOS transistor configured to form the first current to be provided to the charging unit by using the bias unit as a bias source.

The discharge control unit may include: a discharge control MOS transistor connected to the ground terminal and turned on by the charge control signal; And a second bias MOS transistor connected in series between the discharge control MOS transistor and the lock decision node, the second bias MOS transistor configured to form the second current to be discharged from the charging unit using the bias unit as a bias source. In this case, the first current and the second current are currents of the same magnitude.

The unit time means a time interval between the delay signals. That is, the unit time is 1/7 hours of the period of the reference signal.

The lock ready signal output unit outputs the lock ready signal when the potential of the lock determination node rises by the lock potential by the current charged in the charging unit. Preferably, the lock ready signal output unit uses a Schmitt Trigger that is insensitive to noise.

The lock detector may include: an unlock signal generator configured to receive the reference signal and the seventh order delay signal and generate an unlock signal; And an unlock control unit connected in parallel to the lock determination node and discharging a current equal to a third current per unit time from the charging unit in response to the unlock signal generated by the unlock signal generation unit. .

At this time, the unlock signal has a low level when the reference signal and the seventh order delay signal have the same level, and has a high level when the reference signal and the seventh order delay signal have different levels. That is, the unlock signal generator is an exclusive OR gate that receives the reference signal and the seventh order delay signal. The third current has a magnitude seven times the first current.

The unlock control unit may include: an unlock control MOS transistor connected to the ground terminal and turned on by the unlock signal; And a third bias MOS transistor connected in series between the lock decision node and the unlock control MOS transistor, the third bias MOS transistor forming the third current to be discharged from the charging section using the bias section as a bias source.

It operates by the lock ready signal output through the lock detection unit, and checks whether the reference signal is abnormal using any one of the reference signal and the plurality of delay signals, and if there is no error, the lock state The notification may further include a lock signal output unit for outputting a lock signal. In this case, the one signal means the fifth order delay signal.

The lock signal output unit includes: a first inverter for inverting the fifth order delay signal; A first deflip-flop which is activated by the lock ready signal output from the lock detector and outputs the input reference signal using a fifth order delay signal inverted by the first inverter as a clock signal; A second deflip-flop for which an operation is activated by the lock ready signal and outputting the input reference signal using the fifth order delay signal as a clock signal; A second inverter for inverting the signal output from the second flip-flop; A NAND gate configured to perform a NAND operation by receiving the output signal of the first flip-flop and the output signal of the second inverter; And a third inverter outputting the lock signal by inverting the output signal of the NAND gate.

On the other hand, the delay synchronization loop according to the present invention for achieving the second object of the present invention includes a phase detector for generating an up / down signal by comparing a reference signal as an external input signal and a feedback signal as an output signal; A charge pump generating a current signal that changes in response to an up / down signal output from the phase detector; A loop filter receiving a current signal output by the charge pump and generating a control voltage signal; A voltage control delay line comprising a plurality of unit delay units connected in series and delaying the reference signal in response to a control voltage signal applied from the loop filter; And a lock detector that detects a lock state of an output signal output from the voltage control delay line by using the reference voltage and the plurality of delay signals inputted to the voltage control delay.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a block diagram showing the configuration of a typical delay lock loop.

Referring to FIG. 1, the delay lock loop 100 includes a phase detector (PD) 110, a charge pump 120, a loop filter 130, and a voltage control delay line (VCDL). Controlled Delay Line (140).

The phase detector 110 generates an up signal UP or a down signal DN by comparing the reference signal FREF and the feedback signal FEED input from the outside. At this time, the generated up signal UP or down signal DN is input to the charge pump 120.

The charge pump 120 receives the up signal UP or the down signal DN output from the phase detector 110 and generates a current signal that changes according to these signals UP / DN to the loop filter 130. Offer.

The loop filter 130 receives the current signal output by the charge pump 120, performs low pass filtering, generates a control voltage signal VCTRL, and applies it to the voltage control delay line 140.

The voltage control delay line 140 receives the reference signal FREF, which is the input signal FIN, and receives the reference signal FREF for a predetermined time in response to the control voltage signal VCTRL applied from the loop filter 130. Delay by. At this time, the signal delayed by the voltage control delay line 140 becomes the output signal FOUT and again becomes the feedback signal FEED.

The voltage control delay line 140 includes a plurality of unit delay units 141 to 147 connected in series. In this case, the number of unit delays provided is variously determined, but in FIG. 1, seven unit delayers 141 to 147, that is, a first unit delayer 141, a second unit delayer 142, and a third unit It can be seen that the delay unit 143, the fourth unit delay unit 144, the fifth unit delay unit 145, the sixth unit delay unit 146, and the seventh unit delay unit 147 are provided.

In this case, the signal output from the first unit delayer 141 is converted into a first order delay signal D1, and the signal output from the second unit delayer 142 is converted into a second order delay signal D2 and a third unit. The signal output from the delay unit 143 is transferred from the third order delay signal D3 and the fourth unit delay unit 144 by the fourth order delay signal D4 and the fifth unit delay unit 145. The signal output from the fifth order delay signal D5 and the sixth unit delay unit 146 is output from the sixth order delay signal D6, and the signal output from the seventh unit delay unit 147 is seventh. It is defined as the difference delay signal D7.

FIG. 2 is a graph showing a change in the control voltage signal VCTRL of the delay lock loop 100 shown in FIG.

Referring to FIG. 2, the control voltage signal VCTRL is largely changed into three regions, namely, a slow region at an initial stage of operation, a fast region, which is an intermediate region, and a lock region in which an output signal is stabilized. .

3 to 5 are timing diagrams showing signal flow in each region shown in FIG. 2, FIG. 3 shows signal flow in a slow region, FIG. 4 shows signal flow in a fast region, and FIG. Denotes the signal flow in the lock region.

Referring to FIG. 3, since the seventh order delay signal D7, which is the output of the voltage control delay line 140, is slower than the reference signal FREF in the slow region, the phase detector 110 may use the up signal UP. )

Referring to FIG. 4, in the fast region, since the seventh order delay signal D7, which is the output of the voltage control delay line 140, is faster than the reference signal FREF, the phase detector 110 may have the down signal DN. )

Meanwhile, referring to FIG. 5, since the reference signal FREF and the seventh order delay signal D7, which are outputs of the voltage control delay line 140, are synchronized with each other in the lock region, the lock signal is locked and the up signal UP is increased. ) And the down signal DN both have a low level.

Fig. 6 is a block diagram showing the configuration of a delay locked loop provided with a lock detector according to a preferred embodiment of the present invention.

Referring to FIG. 6, the lock detector 200 includes a reference signal FREF, which is an input signal FIN, and a delay output from each unit delay 141,..., 147 of the voltage control delay line 140. The signals D1, ..., D7, that is, the first order delay signal D1, the second order delay signal D2, the third order delay signal D3, the fourth order delay signal D4, The fifth order delay signal D5, the sixth order delay signal D6, and the seventh order delay signal D7 are received. In addition, a lock signal LOCK indicating a lock state is output.

FIG. 7 is a circuit diagram showing the circuit configuration of the lock detector 200 according to the preferred embodiment of the present invention shown in FIG.

Referring to FIG. 7, the lock detector 100 according to an exemplary embodiment of the present invention includes a bias unit 210, a lock detector 220, and a lock signal output unit 240.

The bias unit 210 receives a current IBIAS insensitive to the power supply voltage VDD applied from the outside and the PVT generated by the reference bias circuit, and the charge detection unit Iup and the discharge current Idn in the lock detection unit 220. ) And a bias source that enables the generation of an unlock current.

The lock detector 220 outputs a charge control signal generator 227, a charge controller 221, a discharge controller 222, an unlock signal generator 228, an unlock controller 223, a charger 224, and a lock ready signal output. It consists of a part 225.

The charging control signal generator 227 receives the reference signal FREF and the third delay signal D3 to generate the charging control signal FILTER_IN. The charging control signal generator 227 includes an exclusive NOR gate that receives a reference signal FREF and a third delay signal D3 as an input.

Accordingly, the charge control signal FILTER_IN output by the charge control signal generator 227 has a high level when the reference signal FREF and the third delay signal D3 have the same level. When the reference signal FREF and the third delay signal D3 have different levels, the reference signal FREF has a low level.

Meanwhile, the charge controller 221 and the discharge controller 222 are connected in series between the power supply voltage VDD and the ground terminal, and a lock decision node LD is formed between the two controllers 221 and 222. . In addition, a charging unit 224 and an unlocking control unit 223 are connected to the lock determination node LD in parallel, respectively.

The charging controller 221 charges the charging unit 224 with a current equal to the first current Iup for a unit time (TD) in response to the charging control signal FILTER_IN generated by the charging control signal generator 227. Perform the function.

In this case, the unit time TD means a time interval between the delay signals D1, ..., D7. In the present embodiment, since the seven delay signals D1, ..., D7 exist by the voltage control delay line 140, the unit time TD is one seventh of a period of the reference signal FREF. . That is, the unit time TD is 1/7 cycles.

The charge control unit 221 is connected to the power supply voltage VDD and is turned on by the inversion signal of the charge control signal FILTER_IN. The charge control MOS transistor M1 and the charge control MOS transistor M1 are locked. The first bias MOS transistor M2 is connected in series between the decision nodes LD and forms a first current Iup to be provided to the charging unit 224 using the bias unit 210 as a bias source.

The discharge controller 222 controls the current charged in the charger 224 by the second current Idn during the unit time TD in response to the charge control signal FILTER_IN generated by the charge control signal generator 227. Discharge function. In this case, the second current Idn is a current equal in magnitude to the first current Iup.

The discharge controller 222 is connected to a ground terminal and is discharged between a discharge control MOS transistor M4 and a turn control node F4 which is turned on by a charge control signal FILTER_IN, and the discharge control MOS transistor M4 and the lock decision node LD. The second bias MOS transistor M3 is connected in series to form a second current Idn to be discharged from the charging unit 224 using the bias unit 210 as a bias source.

The unlock signal generator 228 receives the reference signal FREF and the seventh order delay signal D7 to generate an unlock signal UNLOCK. The unlock signal generator 228 includes an exclusive OR gate that receives a reference signal FREF and a seventh order delay signal D7.

Therefore, the unlock signal UNLOCK output by the unlock signal generator 228 has a low level when the reference signal FREF and the seventh order delay signal D7 have the same level, and the reference signal FREF When the seventh order delay signal D7 has another level, it has a high level.

The unlock control unit 223 is connected in parallel to the lock determination node LD, and in response to the unlock signal UNLOCK generated by the unlock signal generation unit 228, the unlock control unit 223 applies a current of Iunlock per unit time. Discharge from the charging unit. In this case, the third current Iunlock has a magnitude seven times the first current Iup or the second current Idn.

The unlock control unit 223 is connected to the ground terminal and is connected in series between the unlock control MOS transistor M6 and the lock decision node LD and the unlock control MOS transistor M6 that are turned on by the unlock signal UNLOCK. The third bias MOS transistor M5 is configured to form a third current Iunlock to be discharged from the charging unit 224 by using the unit 210 as a bias source.

Meanwhile, the charging unit 224 is connected in parallel to the lock determination node LD and performs a function of charging the first current Iup supplied from the charging unit 224 in unit time. At this time, the currents stored in the charging unit 224 may be discharged by the discharge control unit 222 by the second current (Idn). In addition, the currents stored in the charging unit 224 may be discharged by the unlock current control unit 223 by the third current (Iunlock). The charging unit 224 may be configured as a charging capacitor C1 connected in parallel to the lock determination node LD.

The lock ready signal output unit 225 outputs a lock ready signal LOCK READY when the potential of the lock determination node LD rises by a lock potential (HIV) due to a current charged in the charging unit 224. . The lock potential is about 2.5V. Preferably, the lock ready signal output unit 225 uses a Schmitt Trigger that is insensitive to noise.

As described above, the lock detection unit 220 generates a lock ready signal LOCK READY when the output of the delay lock loop 1000 enters the locked state. However, since the voltage control delay line 140 only plays a role of delaying the input signal FIN, that is, the reference signal FREF, due to the characteristics of the delay lock loop 1000, the input of the signal in the control circuit of the previous stage is performed. If the input signal (FIN) is cut off due to a stop or an abnormal circuit, a circuit for detecting such abnormal input and making the output of the lock detector 200 low is required. That is, a block for determining an abnormality of the input signal FIN is required. For this purpose, the lock signal output unit 240 is provided.

The lock signal output unit 240 operates by a lock ready signal LOCK READY output by the lock ready signal output unit 225 and receives a reference signal FREF and a fifth delay signal D5. After determining whether there is an error, the lock signal (LOCK) is output only when there is no error.

FIG. 8 is a detailed circuit diagram showing the circuit configuration of the lock signal output unit 240 shown in FIG.

Referring to FIG. 8, the lock signal output unit 240 may include a first inverter 241, a first flip flop 242, a second flip flop 243, and a second inverter 244. ), A NAND gate 245, and a third inverter 246.

The first inverter 241 inverts the fifth delay signal D5 and provides the clock signal of the first deflip-flop 242.

The first deflip-flop 242 is activated such that reset is released by the lock ready signal LOCK READY output from the lock detector 220, and is inverted by the first inverter 241. The difference delay signal D5 is clocked and the input reference signal FREF is output in synchronization with the clock signal.

The second deflip-flop 243 is activated to be reset and operated by the lock ready signal LOCK READY output from the lock detector 220, and is input by using the fifth delay signal D5 as a clock signal. The reference signal is output in synchronization with the clock signal.

The second inverter 244 inverts the signal output from the second flip-flop 243 and provides the inverted signal to the NAND gate 245.

The NAND gate 245 receives an output signal of the first deflip-flop 242 and an output signal of the second inverter 244, that is, an inverted output signal of the second deflip-flop 243 and performs a NAND operation. The output is then output to the third inverter 246.

The third inverter 246 inverts the output signal of the NAND gate 245 and outputs a final lock signal LOCK.

Through the structure of the lock detector 200 as described above, it is possible to detect a stable lock state of the delay synchronization loop 1000 and to determine a malfunction of the input signal. This will become clearer in the operation description below.

FIG. 9 is a timing diagram illustrating the operation of the lock detection unit 200 shown in FIG. 7 and illustrates the operation in the lock section.

First, the charge control signal generator 227 generates the charge control signal FILTER_IN through an exclusive NOR operation of the reference signal FREF and the third delay signal D3. In addition, the unlock signal generator 228 generates an unlock control signal UNLOCK through an exclusive ord operation of the reference signal FREF and the seventh order delay signal D7.

Fig. 10 is a chart showing the output values of the exclusive Noa operation and the exclusive Noa operation.

Referring to FIG. 10, an exclusive NOR operation outputs '1' when two input values X and Y are the same, and a '0' output when the two input values X and Y are the same. If it is equal to, it can be seen that '1' is output.

Referring to FIG. 9, it can be seen that in the lock period, the charging current is generated six times more predominantly than the discharge current by the generated charge control signal FILTER_IN. Because, as mentioned above, in the lock detector 220, when the charge control signal FILTER_IN is '0', the charging operation is performed by the charge controller 221, and when the charge control signal FILTER_IN is '1', the discharge is performed. This is because the discharge operation is performed by the controller 222.

Therefore, the current charged in one cycle is shown in Equation 1.

6 × Iup × TD-1 × Idn × TD = 5 × Iup × TD

(TD means unit time, that is, time interval between delayed signals)

In addition, the current discharged per cycle is determined by the reference signal FREF and the seventh order delay signal D7.

0 × Iunlock × TD = 0

(Iunlock is 7 × Iup)

Accordingly, the current charged per cycle in the locked state becomes 5 × Iup × TD, which is a value obtained by subtracting Equation 2 from Equation 1. Therefore, the charging unit 224 is charged with current and the potential of the lock determination node LD is increased.

On the other hand, in the non-locked state, the current charged by the generated charge control signal FILTER_IN is 5 × Iup × TD, whereas the current discharged by the unlock signal UNLOCK is at least 7 × Iup × TD. . Therefore, the potential of the lock determination node LD cannot rise in a state where the lock state is not completely entered. This is explained through FIGS. 12 to 13.

FIG. 11 is a timing diagram illustrating the operation of the lock detection unit 220 shown in FIG. 7 and illustrates an example of the operation in the slow section.

Referring to FIG. 11, a current charged per cycle in a slow period is expressed by Equation 3 below.

6 × Iup × TD-1 × Idn × TD = 5 × Iup × TD

In addition, the current discharged per cycle in the slow section is shown in Equation 4.

1 × Iunlock × TD = 1 × 7 × Iup × TD

Accordingly, the current charged per cycle in the slow state becomes -2 x Iup x TD, which is a value obtained by subtracting Equation 4 from Equation 3. Therefore, the electric current of the charging section is discharged, and the potential of the lock determination node LD is lowered.

9 and 11, when the potential of the lock determination node LD rises by the lock potential HIV, the lock ready signal output unit 225 outputs the lock ready signal LOCK READY. This means that the requirement to lock is satisfied.

However, if the input signal, i.e., the reference signal is cut off due to an abnormal input of the signal or a circuit abnormality, the abnormal input check process detects such an abnormal input and makes the output of the lock detector 200 low. This is performed by the lock signal output unit 240 mentioned above.

12 to 14 are timing diagrams for describing an operation of the lock signal output unit 240 of the lock detector 200 shown in FIG. 8, and FIG. 12 illustrates an operation when a normal reference signal is input. 13 to 14 show an operation when an abnormal reference signal is input.

8 and 12, when the lock ready signal LOCK READY is input in response to the requirement of the locked state, the reset of the first deflip-flop 242 and the second deflip-flop 243 is released and operable. Becomes

When there is no abnormality in the reference signal FREF, the position of the fifth order delay signal D5 and the inverted signal D5B of the fifth order delay signal are as shown in FIG. 12, and thus, the fifth order delay signal D5 is represented. The second deflip-flop 243, which is input as a clock signal, receives a '0' and the first deflip-flop 242, which receives an inverted signal D5B of a fifth delay signal, has a rising edge. When sampling through Edge, the high level lock signal LOCK is outputted.

However, the reference signal FREF, which is the input signal FIN, normally enters and is fixed to a high level signal as shown in FIG. 13 due to a signal abnormality, or fixed to a low level signal as shown in FIG. When the lock signal output from the lock signal output unit 240 does not satisfy the condition of making the lock signal high, the lock signal LOCK transitions to the low level so that the delay lock loop 1000 does not maintain the lock state. It is not shown.

Although the present invention has been described above with reference to its preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And can be practiced with modification. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, according to the lock detector according to the present invention, a lock state is detected in a state where the output signal is sufficiently stable using analog charge and discharge operations using delay signals output from the unit delays of the voltage controlled delay line. do. Therefore, it is possible to reduce the influence of noise and to detect a stable lock state. In addition, even when an abnormality occurs in the input signal, it can be detected and reflected in the lock signal.

Claims (46)

And a charging unit, and controls charging and discharging of the charging unit by using control signals generated based on a reference signal input from an external device and a plurality of delay signals input from an external voltage control delay line (VCDL). A lock detector for detecting a locked state based on the potential of the lock detector; And And a bias section for providing a bias source for controlling charging and discharging of the charging section. The method of claim 1, wherein the plurality of input delay signals include a first order delay signal, a second order delay signal, a third order delay signal, a fourth order delay signal, a fifth order delay signal, a sixth order delay signal, A seventh order delay signal, And the delay signals are sequentially output from the seven unit delay units provided in the voltage controlled delay line. The method of claim 2, wherein the lock detection unit, A charge control signal generator configured to generate a charge control signal using the reference signal and the third delay signal; A charging control unit charging the current as much as a first current for a unit time in a case where the charging control signal has a first logic level; A discharge controller configured to discharge a current equal to a second current during the unit time to the charging unit when the charge control signal has a second logic level; And And a lock ready signal output unit configured to output a lock ready signal when the lock state is detected by a current charged in the charging unit. 4. The lock detector of claim 3, wherein the charge control signal generator is an exclusive NOR gate receiving the reference signal and the third delay signal. The method of claim 3, wherein the charge control signal has a high level when the reference signal and the third delay signal have the same level, and a low level when the reference signal and the third delay signal have different levels. And a lock detector of a delay locked loop.  4. The method of claim 3, wherein the charge control unit and the discharge control unit is connected in series between a power supply voltage and a ground terminal, a lock determination node is formed at the connection point and the charging unit is connected in parallel to the lock determination node. Lock detector for a delay lock loop. The method of claim 6, wherein the charging control unit, A charge control MOS transistor connected to the power supply voltage and turned on by an inversion signal of the charge control signal; And And a first bias MOS transistor connected in series between the charge control MOS transistor and the lock decision node, the first bias MOS transistor configured to form the first current to be provided to the charging unit using the bias unit as a bias source. Lock detector. The method of claim 6, wherein the discharge control unit, A discharge control MOS transistor connected to the ground terminal and turned on by the charge control signal; And And a second bias MOS transistor connected in series between the discharge control MOS transistor and the lock decision node, the second bias MOS transistor configured to form the second current to be discharged from the charging section using the bias section as a bias source. Lock detector. 4. The lock detector of claim 3, wherein the first current and the second current are equal in magnitude. 4. The lock detector of claim 3, wherein the unit time is a time interval between the delay signals. 11. The lock detector of claim 10, wherein the unit time is one seventh of a period of the reference signal. 4. The lock detector of claim 3, wherein the charging unit is a capacitor. 4. The lock detector of claim 3, wherein the lock ready signal output unit outputs the lock ready signal when the potential of the lock determination node rises by the lock potential due to a current charged in the charging unit. 4. The lock detector of claim 3, wherein the lock ready signal output unit is a Schmitt trigger insensitive to noise. The method of claim 3, wherein the lock detection unit, An unlock signal generator configured to receive the reference signal and the seventh order delay signal and generate an unlock signal; And And an unlock control unit connected in parallel to the lock determination node and discharging a current equal to a third current per unit time from the charging unit in response to the unlock signal generated by the unlock signal generation unit. Lock detector for delayed-lock loops. The method of claim 15, wherein the unlock signal has a low level when the reference signal and the seventh order delay signal have the same level, and a high level when the reference signal and the seventh order delay signal have different levels. And a lock detector of a delay lock loop. 16. The lock detector of claim 15, wherein the unlock signal generator is an exclusive OR gate which receives the reference signal and the seventh order delay signal. 16. The lock detector of claim 15 wherein the third current is a current having a magnitude seven times the first current. The method of claim 15, wherein the unlock control unit, An unlock control MOS transistor connected to the ground terminal and turned on by the unlock signal; And A third bias MOS transistor connected in series between the lock decision node and the unlock control MOS transistor, the third bias MOS transistor being configured to form the third current to be discharged from the charging section using the bias section as a bias source. Lock detector in synchronous loop. The method of claim 2, wherein the operation is performed by a lock ready signal output through the lock detection unit, and after checking whether the reference signal is abnormal using any one of the reference signal and the plurality of delay signals, the abnormality is detected. And a lock signal output unit for outputting a lock signal informing of the lock state if there is no lock signal. 21. The lock detector of claim 20, wherein the one signal is the fifth order delay signal. The method of claim 21, wherein the lock signal output unit, A first inverter for inverting the fifth order delay signal; A first deflip-flop which is activated by the lock ready signal output from the lock detector and outputs the input reference signal using a fifth order delay signal inverted by the first inverter as a clock signal; A second flip-flop that is activated by the lock ready signal and outputs the input reference signal using the fifth order delay signal as a clock signal; A second inverter for inverting the signal output from the second flip-flop; A NAND gate configured to perform a NAND operation by receiving the output signal of the first flip-flop and the output signal of the second inverter; And And a third inverter for inverting the output signal of the NAND gate and outputting the lock signal. A phase detector for generating an up / down signal by comparing a reference signal as an external input signal and a feedback signal as an output signal; A charge pump generating a current signal that changes in response to an up / down signal output from the phase detector; A loop filter receiving a current signal output by the charge pump and generating a control voltage signal; A voltage control delay line including a plurality of unit delayers connected in series and delaying the reference signal in response to a control voltage signal applied from the loop filter to generate a plurality of delay signals; And A lock detector and a lock detector configured to control charging and discharging of the charger by using control signals generated based on the reference signal and the plurality of delay signals and to detect a lock state based on a potential of the charger. And a lock detector including a bias portion for providing a bias source for controlling charging and discharging of the charging portion. delete The method of claim 23, wherein the voltage control delay line comprises: a first unit delay unit, a second unit delay unit, a third unit delay unit, a fourth unit delay unit, a fifth unit delay unit, a sixth unit delay unit, and a fifth unit delay unit; A delay lock loop, characterized in that the seven unit delays are connected in series. The method of claim 25, wherein the lock detection unit, A first order delay signal output from the first unit delay unit; A second order delay signal output from the second unit delay unit; A third order delay signal output from the third unit delay unit; A fourth order delay signal output from the fourth unit delay unit; A fifth order delay signal output from the fifth unit delay unit; A sixth order delay signal output from the sixth unit delay unit; And And a seventh order delay signal output from the seventh unit delay unit. The method of claim 26, wherein the lock detection unit, The charging unit; A charge control signal generator configured to generate a charge control signal using the reference signal and the third delay signal; A charging controller configured to charge a current equal to a first current in the charging unit for a unit time in response to the charging control signal generated by the charging control signal generator; A discharge controller configured to discharge a current equal to a second current during the unit time to the charger in response to the charge control signal generated by the charge control signal generator; And And a lock ready signal output unit configured to output a lock ready signal when the lock state is detected by a current charged in the charging unit. 28. The delay lock loop as recited in claim 27, wherein the charge control signal generator is an exclusive NOR gate receiving the reference signal and the third delay signal. 28. The method of claim 27, wherein the charge control signal has a high level when the reference signal and the third order delay signal have the same level, and a low level when the reference signal and the third order delay signal have different levels. And a delay lock loop comprising:  28. The method of claim 27, wherein the charge control unit and the discharge control unit is connected in series between a power supply voltage and a ground terminal, a lock determination node is formed at the connection point and the charge determination unit is connected in parallel to the lock determination node. Delayed synchronization loop. The method of claim 30, wherein the charging control unit, A charge control MOS transistor connected to the power supply voltage and turned on by an inversion signal of the charge control signal; And And a first bias MOS transistor connected in series between the charge control MOS transistor and the lock decision node, the first bias MOS transistor configured to form the first current to be provided to the charging unit using the bias unit as a bias source. . The method of claim 30, wherein the discharge control unit, A discharge control MOS transistor connected to the ground terminal and turned on by the charge control signal; And And a second bias MOS transistor connected in series between the discharge control MOS transistor and the lock decision node, the second bias MOS transistor configured to form the second current to be discharged from the charging section using the bias section as a bias source. . 28. The delay lock loop as recited in claim 27, wherein the first current and the second current are equal in magnitude. 28. The delay lock loop as recited in claim 27, wherein the unit time is a time interval between the delay signals. 35. The delay lock loop as recited in claim 34, wherein the unit time is one seventh of a period of the reference signal. 28. The delay lock loop as recited in claim 27, wherein the charging unit is a capacitor. 28. The delay lock loop as recited in claim 27, wherein the lock ready signal output unit outputs the lock ready signal when the potential of the lock determination node rises by the lock potential due to a current charged in the charging unit. 28. The delay lock loop as recited in claim 27, wherein the lock ready signal output unit is a Schmitt trigger insensitive to noise. The method of claim 27, wherein the lock detection unit, An unlock signal generator configured to receive the reference signal and the seventh order delay signal and generate an unlock signal; And And an unlock control unit connected in parallel to the lock determination node and discharging a current equal to a third current per unit time from the charging unit in response to the unlock signal generated by the unlock signal generation unit. Delayed synchronization loop. 40. The method of claim 39, wherein the unlock signal has a low level when the reference signal and the seventh order delay signal have the same level, and a high level when the reference signal and the seventh order delay signal have different levels. Delay synchronous loop. 40. The delay lock loop as recited in claim 39, wherein the unlock signal generator is an exclusive OR gate which receives the reference signal and the seventh order delay signal. 40. The delay lock loop as recited in claim 39, wherein the third current is a current having a magnitude seven times the first current. The method of claim 39, wherein the unlock control unit, An unlock control MOS transistor connected to the ground terminal and turned on by the unlock signal; And And a third bias MOS transistor connected in series between the lock determination node and the unlock control MOS transistor, the third bias MOS transistor being configured to form the third current to be discharged from the charging section using the bias section as a bias source. Loop. The lock detector of claim 25, wherein the lock detector operates by a lock ready signal output through the lock detector, and checks whether the reference signal is abnormal using any one of the reference signal and the plurality of delay signals. And a lock signal output unit for outputting a lock signal informing of the lock state when there is no abnormality. 45. The delay lock loop as recited in claim 44, wherein the one signal is the fifth order delay signal. The method of claim 45, wherein the lock signal output unit, A first inverter for inverting the fifth order delay signal; A first deflip-flop which is activated by the lock ready signal output from the lock detector and outputs the input reference signal using a fifth order delay signal inverted by the first inverter as a clock signal; A second flip-flop that is activated by the lock ready signal and outputs the input reference signal using the fifth order delay signal as a clock signal; A second inverter for inverting the signal output from the second flip-flop; A NAND gate configured to perform a NAND operation by receiving the output signal of the first flip-flop and the output signal of the second inverter; And And a third inverter for inverting the output signal of the NAND gate and outputting the lock signal.

Images