KR100682361B1 - Organic Light Emitting Diode Display and Driving Apparatus thereof - Google Patents

Abstract

The present invention relates to a driving device capable of improving the reliability of an operation of a driving circuit and an organic light emitting diode display device using the same.

The driving device of the organic light emitting diode display includes a first pull-up transistor that supplies a first control signal to a first signal line in response to a voltage on a first Q node, and the first in response to a voltage on a first QB node. A first pull-down transistor for discharging a signal line, a first control unit for controlling the first Q and first QB nodes, and a first for discharging the first Q node in response to a second control signal from a second signal line A gate driving circuit including one transistor, a second pull-up transistor for supplying the second control signal to the second signal line in response to a voltage on a second Q node, and in response to a voltage on a second QB node; A second pull-down transistor configured to discharge a second signal line, a second controller configured to control the second Q and second QB nodes, and a second transistor configured to discharge the second Q node in response to the first control signal; Including And a reset signal to the driver circuit.

Description

Organic Light Emitting Diode Display and Driving Apparatus

1 is a view showing a conventional organic light emitting diode display.

FIG. 2 is a diagram illustrating a gate driving circuit and a reset signal driving circuit of FIG. 1. FIG.

3 is a diagram illustrating a scan signal and a reset signal generated in the gate driving circuit and the reset signal driving circuit of FIG.

4 is a view illustrating in detail the gate driving circuit and the reset signal driving circuit of FIG.

5 illustrates an organic light emitting diode display according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating an organic light emitting diode display device having an organic light emitting diode driving circuit different from the organic light emitting diode display device of FIG. 5. FIG.

7 is a diagram illustrating a gate driving circuit and a reset signal driving circuit of FIG. 5.

FIG. 8 illustrates the gate driving circuit and the reset signal driving circuit of FIG. 7 in detail.

FIG. 9 is another diagram illustrating the gate driving circuit and the reset signal driving circuit of FIG. 7 in detail.

FIG. 10 is another diagram illustrating the gate driving circuit and the reset signal driving circuit of FIG. 7 in detail.

FIG. 11 is another diagram illustrating the gate driving circuit and the reset signal driving circuit of FIG. 5. FIG.

FIG. 12 illustrates the gate driving circuit and the reset signal driving circuit of FIG. 11 in detail.

FIG. 13 is another diagram illustrating the gate driving circuit and the reset signal driving circuit of FIG. 12 in detail.

FIG. 14 is a still another view showing the gate driving circuit and the reset signal driving circuit of FIG.

<Explanation of symbols for the main parts of the drawings>

11, 101: data driving circuit 12, 102, 202: gate driving circuit

16, 106, 206: reset line driving circuit 13, 103: OLED panel

D1, D2,... Dm: data lines G1, G2,... Gn: gate line

S1, S2,... Sm: power voltage supply lines R1, R2,... Rn: reset line

15, 105, 107: OLED driving circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display, and more particularly, to a driving device capable of improving the reliability of an operation of a pixel driving circuit of an organic light emitting diode display and an organic light emitting diode display using the same.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such a flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting diode (LED) display, and the like. There is this.

Among them, the LED display device uses LEDs that emit phosphors by recombination of electrons and holes, and these LEDs are inorganic LED (Inorganic Light Emitting Diode) displays using inorganic compounds as phosphors and organic LEDs using organic compounds ( Organic Light Emitting Diode (hereinafter referred to as OLED). Such OLED displays have many advantages such as low voltage driving, self-luminous, thin film type, wide viewing angle, fast response speed and high contrast, and are expected to be the next generation display devices.

The OLED is usually composed of an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer stacked between a cathode and an anode. In the OLED, when a predetermined voltage is applied between the anode and the cathode, electrons generated from the cathode move toward the light emitting layer through the electron injection layer and the electron transport layer, and holes generated from the anode move toward the light emitting layer through the hole injection layer and the hole transport layer. Move. Accordingly, the light emitting layer emits light by recombination of electrons and holes supplied from the electron transporting layer and the hole transporting layer.

As shown in FIG. 1, an active matrix type OLED display using such an OLED has n gate lines (G1 to Gn, where n is a positive integer) and m data lines (D1 to Dm: m). An OLED panel 13 having n × m pixels P [i, j] arranged in an n × m matrix in a region defined by the intersection of the positive integers, and each pixel P [i, j Power supply voltage supply lines S1 to Sm for supplying a high potential power voltage to the power supply circuit; reset lines R1 to Rn for supplying a reset signal to each pixel P [i, j], and a gate line; And a reset signal driver circuit 16 for driving the reset lines R1 to Rn. However, P [i, j] is a pixel located in row i, column j, i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m.

The gate driving circuit 12 sequentially supplies scan signals for selecting a horizontal line to the gate lines G1 to Gn.

The reset signal driving circuit 16 has the same structure as the gate driving circuit 12 and operates independently of the gate driving circuit 12 to sequentially supply reset signals to the reset lines G1 to Gn.

The data driving circuit 11 converts the digital data voltage input from the outside into an analog data voltage. The data driving circuit 12 supplies the analog data voltage to the data lines D1 to Dm whenever the scan signal is supplied.

Each of the pixels P [i, j] receives a data voltage from the j-th data line Dj when the scan signal is supplied to the i-th gate line Gi to generate light corresponding to the data voltage. do.

To this end, each of the pixels P [i, j] is connected to an OLED having an anode connected to a j-th power supply voltage supply line Sj, and an i-th gate line Gi connected to a cathode of the OLED to drive the OLED. And an OLED driving circuit 15 connected to the j-th data line Dj and the i-th reset line Ri and supplied with a low potential power voltage Vss.

The OLED driving circuit 15 included in the pixels P [i, j] in the i th row j th column may receive data voltages from the j th data line Dj in response to a scan signal from the i th gate line Gi. Transistor T1 for supplying to the first node N1, the second transistor T2 for controlling the amount of current flowing through the OLED in response to the voltage on the first node N1, and the i-th reset line Ri. A third transistor T3 for discharging the first node N1 in response to a reset signal.

When the scan signal is supplied through the i-th gate line Gi, the first transistor T1 of the OLED driving circuit 15 is turned on to receive the data voltage supplied from the j-th data line Dj. Supplies). The data voltage supplied to the first node N1 is supplied to the gate terminal of the second transistor T2. When the second transistor T2 is turned on by the data voltage supplied in this way, current flows through the OLED. At this time, the current flowing through the OLED is generated by the high potential power voltage Vdd, and the amount of current is proportional to the magnitude of the data voltage applied to the gate electrode of the second transistor T2. In addition, even when the first transistor T1 is turned off, the second transistor T2 remains turned on by the data voltage floated on the first node N1, and the i-th reset line The second transistor T2 remains turned on until the third transistor T3 is turned on by the reset signal supplied from (Ri) and the first node N1 is discharged. At this time, the reset signal from the i-th reset line Ri is supplied with a delay of 1/2 frame period from the scan signal from the i-th gate line.

In order to generate the scan signal supplied to the i-th gate line Gi and the reset signal supplied to the i-th reset line Ri in this manner, the gate driving circuit 12 and the reset signal driving circuit 16 are illustrated in FIG. As shown in 2, each consists of n stages.

Referring to FIG. 2, the gate driving circuit 12 and the reset signal driving circuit 16 each include n stages (first to nth stages) that are connected in a dependent manner.

In the gate driving circuit 12, the first start signal Vst1 is input to the first stage and the previous stage scan signal Vg_i is input to the second to nth stages as the start signal. The previous stage scan signal Vg_i + 1 is input as the stage reset signal to the first to n-th stages, and the stage reset signal is input to the n-th stage from a dummy stage (not shown). In addition, each stage has the same circuit configuration and shifts the first start signal Vst1 or the previous stage scan signal Vg_i in response to any one of the four clock signals C1 to C4, thereby providing one horizontal period. Generates a scan signal with a pulse width.

The second start signal Vst2 supplied to the reset signal driving circuit 16 having the same configuration as that of the gate driving circuit 12 is supplied at a time interval between the first start signal Vst1 and a half frame period. . As such, the reset signal supplied to the i-th reset line by the second start signal Vst2 delayed from the first start signal Vst1 is 1/2 of the scan signal supplied to the i-th gate line Gi. The frame period is delayed and supplied.

3 illustrates a scan signal Vg_i supplied to the gate lines G1 to Gn by the gate driving circuit 12 and reset lines R1 to Rn by the reset path driving circuit 16. The waveform of the reset signal Vr_i is shown. In FIG. 3, "Vg_i" refers to a scan signal supplied to an i th gate line Gi, and "Vr_i" refers to a reset signal supplied to an i th reset line Ri. Meanwhile, although the scan signal Vg_i and the reset line Vr_i are shown in the same phase in FIG. 3, this is to indicate that there is a time interval of 1/2 frame period between the two signals, and the two signals are on different lines. This signal is generated.

4 illustrates the configuration of the gate driving circuit 12 and the reset line driving circuit 16 of FIG. 2 in detail. Since the stage configurations of the gate driving circuit 12 and the reset line driving circuit 16 are the same, the operation of the gate driving circuit 12 and the reset line driving circuit 16 is similar to those of the first and second gate driving circuits 12. A description will be given based on the second stage.

Referring to FIG. 4, when the start signal Vst1 is input to the first stage of the gate driving circuit 12, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having a high voltage is supplied to the first gate line G1 as the first scan signal Vg_1 through the pull-up transistor T-up and simultaneously supplied to the second stage. The Q node of two stages is charged and the QB node is discharged.

Subsequently, the second scan signal Vg_2 generated in the second stage by the second clock signal C2 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. G1 is discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are made by the scan signal Vg_3 supplied from the third stage. In such an operation, the gate driving circuit 12 and the reset line driving circuit 16 sequentially supply scan signals and reset signals to the gate lines and the reset lines.

On the other hand, when a certain amount of charge is charged to the Q node, gate line, or reset line of each stage by application of various signals, an unnecessary output is generated when the clock signal is applied to the circuit. Decreases reliability. Therefore, there is a need for a method capable of reliably discharging unnecessary charges of the Q node, gate line, and scan line of each stage to prevent unnecessary output, thereby improving the reliability of the operation of the driving circuit.

Accordingly, it is an object of the present invention to provide an organic light emitting diode display and a composition thereof which can improve the reliability of the operation.

In order to achieve the above object, the driving device of the organic light emitting diode display according to the embodiment of the present invention is configured to supply the first control signal Vg_1 to the first signal line G1 in response to a voltage on the first Q node. A first pull-up transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, a first control unit that controls the first Q and the first QB node, and a first controller A gate driving circuit including a first transistor configured to discharge the first Q node in response to a second control signal Vr_1 from the second signal line R1, and the second control in response to a voltage on a second Q node A second pull-up transistor that supplies a signal Vr_1 to the second signal line R1, a second pull-down transistor that discharges the second signal line R1 in response to a voltage on a second QB node; A second controller for controlling the second Q and the second QB node and the And a reset signal driving circuit including a second transistor T2 for discharging the second Q node in response to a first control signal Vg_1.

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In another exemplary embodiment, a driving device of an organic light emitting diode display device includes a first pull-up supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node. A transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, a first controller and a second signal line that control the first Q and first QB nodes ( A gate driving circuit including a first transistor configured to discharge the first Q node in response to a second control signal Vr_1 from R1, and the second control signal Vr_1 in response to a voltage on a second Q node. Pull-up transistor for supplying to the second signal line R1, a second pull-down transistor for discharging the second signal line R1 in response to a voltage on a second QB node, and the second Q And a second controller for controlling a second QB node and the first control signal Vg_1. In response, a reset signal driving circuit including a second transistor T2 for discharging the second Q node, and the first signal line in response to the second control signal Vr_1 from the second signal line R1. A third transistor T3 for discharging (G1), and a fourth transistor for discharging the second signal line (R1) in response to the first control signal (Vg_1) from the first signal line (G1) ( T4).

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In another exemplary embodiment, a driving device of an organic light emitting diode display device includes a first pull-up supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node. A transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, a first control unit that controls the first Q and first QB nodes, on a second Q node A second pull-up transistor for supplying a second control signal Vg_2 to a second signal line G2 in response to a voltage, and a second discharge line in response to a voltage on a second QB node; A second pull-down transistor, a second controller for controlling the second Q and the second QB node, and a third for discharging the first Q node in response to a third control signal Vr_1 from a third signal line R1. In response to the third control signal Vr_1 from one transistor T1 and the third signal line R1 A gate driving circuit including a second transistor T2 for discharging the second Q node, and the third control signal Vr_1 in response to a voltage on a third Q node; A third pull-up transistor for supplying a fourth signal line R2, a third pull-down transistor for discharging the third and fourth signal lines R1 and R2 in response to a voltage on a third QB node; A third control unit controlling a 3 Q and a third QB node, and a third transistor T3 discharging the third Q node in response to a first control signal Vg_1 from the first signal line G1. And a fourth transistor T4 for discharging the third and fourth signal lines R1 and R2 in response to the reset signal driving circuit and the first control signal Vg_1 from the first signal line G1. It is provided.

In another exemplary embodiment, a driving device of an organic light emitting diode display device includes a first pull-up supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node. A transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, a first control unit that controls the first Q and first QB nodes, on a second Q node A second pull-up transistor for supplying a second control signal Vg_2 to a second signal line G2 in response to a voltage, and a second discharge line in response to a voltage on a second QB node; A gate driving circuit including a second pull-down transistor and a second control unit controlling the second Q and second QB nodes; and a third control signal Vr_1 in response to a voltage on a third Q node. A third pull-up transistor for supplying the line R1 and the fourth signal line R2, on the third QB node A third pull-down transistor for discharging the third and fourth signal lines R1 and R2 in response to a voltage, a third controller for controlling the third Q and third QB nodes, and the first signal line G1; A reset signal driving circuit including a first transistor T3 for discharging the third Q node in response to a first control signal Vg_1 from the first control signal Vg_1 and the first control from the first signal line G1. The second transistor T4 for discharging the third and fourth signal lines R1 and R2 in response to the signal Vg_1 and the third control signal Vr_1 from the third signal line R1. A third transistor T5 that discharges the first signal line G1 in response, and the second signal line G2 in response to the third control signal Vr_1 from the third signal line R1. And a fourth transistor T6 for discharging.
In yet another exemplary embodiment of the present invention, a driving device of an organic light emitting diode display device includes: a first pull- supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node; An up transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, a first control unit that controls the first Q and first QB nodes, a second Q node A second pull-up transistor supplying a second control signal Vg_2 to a second signal line G2 in response to a voltage on a phase, and discharging the second signal line G2 in response to a voltage on a second QB node. A second pull-down transistor, a second controller for controlling the second Q and second QB nodes, and a discharge of the first Q node in response to a third control signal Vr_1 from a third signal line R1. In response to the third control signal Vr_1 from the first transistor T1 and the third signal line R1 A gate driving circuit including a second transistor T2 for discharging the second Q node, and the third control signal Vr_1 in response to a voltage on a third Q node; A third pull-up transistor for supplying a fourth signal line R2, a third pull-down transistor for discharging the third and fourth signal lines R1 and R2 in response to a voltage on a third QB node; A third control unit controlling a 3 Q and a third QB node, and a third transistor T3 discharging the third Q node in response to a first control signal Vg_1 from the first signal line G1. A reset signal driving circuit and a fourth transistor T4 for discharging the third and fourth signal lines R1 and R2 in response to the first control signal Vg_1 from the first signal line G1. And discharge the first signal line G1 in response to the third control signal Vr_1 from the third signal line R1. The key has a fifth transistor T5 and a sixth transistor T6 for discharging the second signal line G2 in response to the third control signal Vr_1 from the third signal line R1. do.

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According to an exemplary embodiment of the present invention, an organic light emitting diode display having a built-in driving circuit includes a first signal line G1 and a data line crossing each other, and a power voltage supply line supplied with a high potential power voltage and disposed in parallel to the data line. And a second signal line R1 disposed in parallel with the first signal line G1, an organic light emitting diode emitting light with a current generated by a high potential power voltage from the power supply line, and the first signal. In response to the first control signal Vg_1 from the line G1, the organic light emitting diode is driven with the data voltage from the data line, and in response to the second control signal Vr_2 from the second signal line R1. And a first pull-up supplying the first control signal Vg_1 to the first signal line G1 in response to a voltage on an organic light emitting diode driving circuit initialized by A transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, a first controller and a second signal line that control the first Q and first QB nodes ( A gate driving circuit including a first transistor configured to discharge the first Q node in response to a second control signal Vr_1 from R1, and a second control signal Vr_1 in response to a voltage on a second Q node. A second pull-up transistor for supplying the second signal line R1, a second pull-down transistor for discharging the second signal line R1 in response to a voltage on a second QB node, the second Q and An organic light emitting diode display comprising a reset signal driving circuit including a second control unit for controlling a second QB node and a second transistor T2 for discharging the second Q node in response to the first control signal Vg_1. The drive of the device and the data line And a data driving circuit for supplying a data voltage, wherein the driving device of the organic light emitting diode display device includes the first signal line G1, the second signal line R1, the data line, the power voltage supply line, and the pixel. It is formed on the same substrate as the substrate to be formed.

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According to another exemplary embodiment of the present invention, an organic light emitting diode display having a built-in driving circuit includes a first signal line G1 and a data line crossing each other, a power supply voltage that is supplied with a high potential power voltage and is disposed in parallel to the data line. A line, a second signal line R1 disposed in parallel to the first signal line G1, an organic light emitting diode emitting light with a current generated by a high potential power voltage from the power supply line, and the first light emitting diode; In response to the first control signal Vg_1 from the signal line G1, the organic light emitting diode is driven with the data voltage from the data line, and the second control signal Vr_2 from the second signal line R1 is driven. A pixel including an organic light emitting diode driving circuit initialized in response, and a first supplying the first control signal Vg_1 to the first signal line G1 in response to a voltage on the first Q node. A gate comprising a up-transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, and a first controller that controls the first Q and first QB nodes A second pull-up transistor that supplies the second control signal Vr_1 to the second signal line R1 in response to a voltage on a second Q node, the second in response to a voltage on a second QB node A reset signal driving circuit comprising a second pull-down transistor for discharging a second signal line R1 and a second controller for controlling the second Q and second QB nodes, the reset signal driving circuit from the second signal line R1; The first transistor T3 discharges the first signal line G1 in response to a second control signal Vr_1 and the first control signal Vg_1 from the first signal line G1. An organic material including a second transistor T4 for discharging the second signal line R1 And a data driving circuit for supplying the data voltage to the data line, wherein the driving device of the organic light emitting diode display includes the first signal line G1 and the second signal line. R1), a data line, a power supply voltage supply line, and the pixel on which the pixel is formed.

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According to another exemplary embodiment of the present invention, an organic light emitting diode display having a built-in driving circuit includes a first signal line G1 and a data line crossing each other, a power supply voltage supplied with a high potential power voltage and disposed in parallel to the data line. An organic light emitting diode and the first light emitting diode which emit light at a current generated by a supply line, a second signal line R1 disposed in parallel with the first signal line G1, and a high potential power voltage from the power supply line. In response to the first control signal Vg_1 from the first signal line G1, the organic light emitting diode is driven with the data voltage from the data line and the second control signal Vr_2 from the second signal line R1. Supplying the first control signal Vg_1 to the first signal line G1 in response to a voltage on the pixel including an organic light emitting diode driving circuit initialized in response to the first Q node. A first pull-up transistor, a first pull-down transistor that discharges the first signal line G1 in response to a voltage on a first QB node, a first controller that controls the first Q and the first QB node, and the A gate driving circuit including a first transistor configured to discharge the first Q node in response to the second control signal Vr_1 from a second signal line R1, the second in response to a voltage on a second Q node A second pull-up transistor that supplies a control signal Vr_1 to the second signal line R1, and a second pull-down transistor that discharges the second signal line R1 in response to a voltage on a second QB node. A reset signal driving circuit including a second control unit controlling the second Q and second QB nodes and a second transistor T2 discharging the second Q node in response to the first control signal Vg_1; Responding to the second control signal Vr_1 from the second signal line R1 Discharges the second signal line R1 in response to a third transistor T3 for discharging the first signal line G1 and the first control signal Vg_1 from the first signal line G1. The driving device of the organic light emitting diode display device including the fourth transistor T4 and the driving device of the organic light emitting diode display device may include the first signal line G1, the second signal line R1, a data line, It is formed on the same substrate as the substrate on which the power voltage supply line and the pixel are formed.

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According to another exemplary embodiment of the present invention, an organic light emitting diode display having a built-in driving circuit includes a data line supplied with a data voltage, first and second signal lines G1 and G2 intersecting the data line, and a high potential power supply. A power supply voltage supply line supplied with a voltage and disposed in parallel to the data line, third and fourth signal lines R1 and R2 disposed in parallel to the first and second signal lines G1 and G2; A first pull-up transistor for supplying a first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, and the first signal line in response to a voltage on a first QB node. A first pull-down transistor for discharging G1), a first controller for controlling the first Q and first QB nodes, and a second control signal Vg_2 in response to a voltage on a second Q node; A second pull-up transistor, supplying to G2, the phase in response to the voltage on the second QB node A second pull-down transistor for discharging the second signal line G2, a second controller for controlling the second Q and second QB nodes, and a third control signal Vr_1 from the third signal line R1. A second transistor discharging the second Q node in response to the third control signal Vr_1 from the first transistor T1 and the third signal line R1 discharging the first Q node in response to A third pull-up supplying the third control signal Vr_1 to the third and fourth signal lines R1 and R2 in response to a gate driving circuit including a transistor T2 and a voltage on a third Q node. A transistor, a third pull-down transistor that discharges the third and fourth signal lines R1 and R2 in response to a voltage on a third QB node, a third controller that controls the third Q and third QB nodes; Discharging the third Q node in response to the first control signal Vg_1 from the first signal line G1. A reset signal driving circuit including three transistors T3, and discharging the third and fourth signal lines R1 and R2 in response to the first control signal Vg_1 from the first signal line G1. A driving device of an organic light emitting diode display device having a fourth transistor T4, a first organic light emitting diode emitting light with a current generated by a high potential power voltage from the power supply line, and the first signal line G1. Drive the first organic light emitting diode with the data voltage from the data line and in response to the third control signal Vr_1 from the third signal line R1 in response to the first control signal Vg_1 A first pixel including a first organic light emitting diode driving circuit initialized by the second pixel, a second organic light emitting diode emitting light with a current generated by a high potential power voltage from the power supply line, and the second pixel; In response to the second control signal Vg_1 from the call line G2, the second organic light emitting diode is driven with the data voltage from the data line and the third control signal from the fourth signal line R2 ( And a second pixel including a second organic light emitting diode driving circuit initialized in response to Vr_1), and a data driving circuit for supplying the data voltage to the data line, wherein the driving device of the organic light emitting diode display device includes: The first to fourth signal lines G1, G2, R1, and R2, the data line, the power voltage supply line, and the first and second pixels are formed on the same substrate.

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According to another exemplary embodiment of the present invention, an organic light emitting diode display having a built-in driving circuit includes a data line supplied with a data voltage, first and second signal lines G1 and G2 intersecting the data line, and a high potential power supply. A power supply voltage supply line supplied with a voltage and disposed in parallel to the data line, third and fourth signal lines R1 and R2 disposed in parallel to the first and second signal lines G1 and G2; A first pull-up transistor for supplying a first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, and the first signal line in response to a voltage on a first QB node. A first pull-down transistor for discharging G1), a first controller for controlling the first Q and first QB nodes, and a second control signal Vg_2 in response to a voltage on a second Q node; A second pull-up transistor, supplying to G2, the phase in response to the voltage on the second QB node A gate driving circuit including a second pull-down transistor for discharging the second signal line G2 and a second controller for controlling the second Q and second QB nodes, the second driving line in response to a voltage on the third Q node; A third pull-up transistor for supplying a third control signal Vr_1 to the third and fourth signal lines R1 and R2, and the third and fourth signal lines R1, in response to a voltage on a third QB node; A third pull-down transistor for discharging R2), a third controller for controlling the third Q and third QB nodes, and the first control signal Vg_1 from the first signal line G1; A reset signal driving circuit including a first transistor T3 for discharging a third Q node, and the third and fourth signal lines in response to the first control signal Vg_1 from the first signal line G1. A second transistor T4 for discharging (R1, R2), the third control signal Vr_ from the third signal line R1; In response to 1), the third transistor T5 discharges the first signal line G1 and the second signal line in response to the third control signal Vr_1 from the third signal line R1. A driving device of an organic light emitting diode display device having a fourth transistor T6 for discharging G2), a first organic light emitting diode emitting light with a current generated by a high potential power voltage from the power supply line, and the first organic light emitting diode; In response to the first control signal Vg_1 from the first signal line G1, the first organic light emitting diode is driven with the data voltage from the data line and the third control signal from the third signal line R1. A first pixel including a first organic light emitting diode driving circuit initialized in response to Vr_1, a second organic light emitting diode emitting light with a current generated by a high potential power voltage from the power supply line, and The second organic light emitting diode is driven with the data voltage from the data line in response to the second control signal Vg_1 from the second signal line G2 and the third from the fourth signal line R2. A second pixel including a second organic light emitting diode driving circuit initialized in response to a control signal Vr_1, and a data driving circuit for supplying the data voltage to the data line, wherein the organic light emitting diode display is driven. The device is formed on the same substrate as the first to fourth signal lines G1, G2, R1, and R2, the data line, the power voltage supply line, and the substrate on which the first and second pixels are formed.

According to another exemplary embodiment of the present invention, an organic light emitting diode display having a built-in driving circuit includes a data line supplied with a data voltage, first and second signal lines G1 and G2 intersecting the data line, and a high potential power supply. A power supply voltage supply line supplied with a voltage and disposed in parallel to the data line, third and fourth signal lines R1 and R2 disposed in parallel to the first and second signal lines G1 and G2; A first pull-up transistor for supplying a first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, and the first signal line in response to a voltage on a first QB node. A first pull-down transistor for discharging G1, a first controller for controlling the first Q and first QB nodes, and a second control signal Vg_2 in response to a voltage on the second Q node; A second pull-up transistor for supplying G2), in response to a voltage on a second QB node A second pull-down transistor for discharging the two signal lines G2, a second controller for controlling the second Q and second QB nodes, and a response to the third control signal Vr_1 from the third signal line R1. And a second transistor T2 for discharging the second Q node in response to the third control signal Vr_1 from the first transistor T1 and the third signal line R1 for discharging the first Q node. A third pull-up transistor configured to supply the third control signal Vr_1 to the third and fourth signal lines R1 and R2 in response to a voltage on a third Q node; A third pull-down transistor for discharging the third and fourth signal lines R1 and R2 in response to a voltage on a third QB node, a third controller for controlling the third Q and third QB nodes and the first The third transistor T3 discharges the third Q node in response to the first control signal Vg_1 from the signal line G1. A reset signal driving circuit including a fourth transistor T4 for discharging the third and fourth signal lines R1 and R2 in response to the first control signal Vg_1 from the first signal line G1. A fifth transistor T5 for discharging the first signal line G1 in response to the third control signal Vr_1 from the third signal line R1, and from the third signal line R1. A driving device of the organic light emitting diode display device having a sixth transistor T6 for discharging the second signal line G2 in response to the third control signal Vr_1, and a high potential power supply from the power supply line. The first organic light emitting diode is connected to the first organic light emitting diode and the data voltage from the data line in response to the first control signal Vg_1 from the first signal line G1. Drive to the third signal line R1. A first pixel including a first organic light emitting diode driving circuit initialized in response to the third control signal Vr_1 and a second light emitted by a current generated by a high potential power voltage from the power supply line. In response to the second control signal Vg_1 from the organic light emitting diode and the second signal line G2, the second organic light emitting diode is driven from the data voltage from the data line and is driven from the fourth signal line R2. A second pixel including a second organic light emitting diode driving circuit initialized in response to the third control signal Vr_1 of the second pixel; and a data driving circuit configured to supply the data voltage to the data line, the organic light emitting diode The driving device of the display device is the same as the substrate on which the first to fourth signal lines G1, G2, R1, and R2, data lines, power voltage supply lines, and the first and second pixels are formed. It is formed on a substrate.

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Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 14.

Referring to FIG. 5, an OLED display device with a built-in driving circuit according to an exemplary embodiment of the present invention includes n gate lines (G1 to Gn, where n is a positive integer) and m data lines (D1 to Dm: , m is a positive integer and arranged in parallel with n × m pixels P [i, j] and data lines D1 to Dm arranged in an n × m matrix in a region defined by the intersection of a positive integer. The power supply voltage Vdd is arranged in parallel with the m power supply voltage supply lines S1 to Sm and the gate lines G1 to Gn for supplying the power supply voltage Vdd to each pixel P [i, j]. Reset signals R1 through Rn supplied to P [i, j], gate driving circuits 102 driving gate lines G1 through Gn, and reset signals driving reset lines R1 through Rn. OLED panel 103 including a driving circuit 106 including a driving circuit 106 and a data driving circuit 101 for driving the data lines D1 to Dm. However, P [i, j] is a pixel located in row i, column j, i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m.

The gate driving circuit 102 sequentially supplies scan signals for selecting horizontal lines to the gate lines G1 to Gn. The gate driving circuit 102 is composed of a plurality of transistors using amorphous silicon (a-Si) and is formed on one side of the substrate of the OLED panel 103.

The reset signal driver circuit 106 has the same structure as the gate driver circuit 102 and operates independently of the gate driver circuit 102 to sequentially supply reset signals to the reset lines G1 to Gn. The reset signal driving circuit 106 is formed on one side of the opposite side of the gate driving circuit 102 with the pixel region 108 composed of pixels P [i, j] interposed therebetween.

The data driving circuit 101 converts the digital data voltage input from the outside into an analog data voltage. The data driving circuit 102 supplies the analog data voltage to the data lines D1 to Dm whenever the scan signal is supplied.

Each of the pixels P [i, j] receives a data voltage from the j-th data line Dj when the scan signal is supplied to the i-th gate line Gi to generate light corresponding to the data voltage. do.

To this end, each of the pixels P [i, j] is connected to an OLED having an anode connected to a j-th power supply voltage supply line Sj, and an i-th gate line Gi connected to a cathode of the OLED to drive the OLED. And an OLED driving circuit 105 connected to the j-th data line Dj and the i-th reset line Ri and supplied with a low potential power voltage Vss. On the other hand, the circuit configuration in each pixel P [i, j] can also have a structure in which the OLED driving circuit 107 is connected to the anode of the OLED as shown in FIG. The connection structure between the OLED and the OLED driving circuit is optional in the circuit configuration of the pixel P [i, j].

The OLED driving circuit 105 included in the pixels P [i, j] in the ith row jth column is the data voltage from the jth data line Dj in response to the scan signal from the ith gate line Gi. Transistor T1 for supplying to the first node N1, the second transistor T2 for controlling the amount of current flowing through the OLED in response to the voltage on the first node N1, and the i-th reset line Ri. A third transistor T3 for discharging the first node N1 in response to a reset signal.

When the scan signal is supplied through the i-th gate line Gi, the first transistor T1 of the OLED driving circuit 105 is turned on and receives the data voltage supplied from the j-th data line Dj. Supplies). The data voltage supplied to the first node N1 is supplied to the gate terminal of the second transistor T2. When the second transistor T2 is turned on by the data voltage supplied in this way, current flows through the OLED. At this time, the current flowing through the OLED is generated by the high potential power voltage Vdd, and the amount of current is proportional to the magnitude of the data voltage applied to the gate electrode of the second transistor T2. In addition, even when the first transistor T1 is turned off, the second transistor T2 remains turned on by the data voltage floated on the first node N1, and the i-th reset line The second transistor T2 remains turned on until the third transistor T3 is turned on by the reset signal supplied from (Ri) and the first node N1 is discharged. In this case, the reset signal is supplied to prevent the characteristic change caused by the deterioration of the second transistor T2, and the reset signal from the i-th reset line Ri is smaller than the scan signal from the i-th gate line. Supplied at timed intervals. This time interval is about half the frame period of the second transistor, but this can be adjusted as needed.

As such, the gate driving circuit 102 and the reset signal driving circuit 106 are generated to generate a scan signal supplied to the i-th gate line Gi and a reset signal supplied to the i-th reset line Ri after being delayed by the scan signal. ) Is composed of n stages as shown in FIG. 7.

Referring to FIG. 7, the gate driving circuit 102 and the reset signal driving circuit 106 include n stages (first to nth stages) that are cascaded to each other.

In the gate driving circuit 12, the first start signal Vst1 is input to the first stage, and the previous stage scan signal Vg_i-1 is input to the second to nth stages as the start signal. The next stage scan signal Vg_i + 1 is input as the stage reset signal to the first to n-th stages, and the stage reset signal is input to a n-th stage from a dummy stage (not shown). In addition, each stage has the same circuit configuration and shifts the first start signal Vst1 or the previous stage scan signal Vg_i in response to any one of the four clock signals C1 to C4, thereby providing one horizontal period. A scan signal having a pulse width is generated.

The second start signal Vst2 supplied to the reset signal driver circuit 16 having the same configuration as that of the gate driver circuit 12 is supplied at a predetermined time interval from the first start signal Vst1. As described above, the reset signal supplied to the i-th reset line by the second start signal Vst2 supplied delayed than the first start signal Vst1 is delayed for a predetermined period of time than the scan signal supplied to the i-th gate line Gi. It is supplied.

FIG. 8 illustrates a driving device of the OLED display device including the gate driving circuit 102 and the reset line driving circuit 106 together with the specific configuration of the gate driving circuit 102 and the reset line driving circuit 106 of FIG. 7. will be. The driving device of the OLED display illustrated in FIG. 7 includes a first transistor T1 that discharges the i-stage Q node of the gate driving circuit 102 in response to the reset signal Vr_i from the i-th reset line Ri. And a second transistor T2 for discharging the i-th stage Q node of the reset line driving circuit 106 in response to the scan signal Vg_i from the i-th gate line Gi.

Referring to FIG. 8, when the start signal Vst1 is input to the first stage of the gate driving circuit 102, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having the high voltage is supplied to the first gate line G1 as the first scan signal Vg_1 through the pull-up transistor T-up and simultaneously supplied to the second stage. The Q node of two stages is charged and the QB node is discharged.

Subsequently, the second scan signal Vg_2 generated in the second stage by the second clock signal C2 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. G1 is discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are made by the scan signal Vg_3 supplied from the third stage. In such an operation, the gate driving circuit 102 and the reset line driving circuit 106 sequentially supply scan signals and reset signals to the gate lines and the reset lines.

On the other hand, if the time interval between the first start signal Vst1 and the second start signal Vst2 is 1/2 frame period, the first reset signal (1) generated after 1/2 frame period after the first scan signal Vg_1 ( The third transistor T1 is turned on by Vr_1 to discharge the first stage Q node of the gate driving circuit 102. Thereafter, the first stage Q node of the reset signal driving circuit 106 is discharged through the second transistor T2 that is turned on to the first scan signal Vg_1 generated after 1/2 frame period. Similarly, such operations occur sequentially in the second to nth stages of the gate driving circuit 102 and the reset signal driving circuit 106.

As described above, the Q node is discharged once more by using the outputs of the different driving circuits, thereby overcoming the reliability deterioration of the circuit due to the partial charging occurring during the driving.

FIG. 9 illustrates a driving device of an OLED display device including the gate driving circuit 102 and the reset line driving circuit 106 together with other specific configurations of the gate driving circuit 102 and the reset line driving circuit 106 of FIG. 7. It is shown. The driving device of the OLED display illustrated in FIG. 9 includes the third transistor T3 and the i-th gate line which discharge the i-th gate line Gi in response to the reset signal Vr_i from the i-th reset line Ri. The fourth transistor T4 discharges the i-th reset line Ri in response to the scan signal Vg_i from (Gi).

Referring to FIG. 9, when the start signal Vst1 is input to the first stage of the gate driving circuit 102, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having the high voltage is supplied to the first gate line G1 as the first scan signal Vg_1 through the pull-up transistor T-up and simultaneously supplied to the second stage. The Q node of two stages is charged and the QB node is discharged.

Subsequently, the second scan signal Vg_2 generated in the second stage by the second clock signal C2 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. G1 is discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are made by the scan signal Vg_3 supplied from the third stage. In such an operation, the gate driving circuit 102 and the reset line driving circuit 106 sequentially supply the scan signal and the reset signal to the gate lines and the reset lines.

On the other hand, if the time interval between the first start signal Vst1 and the second start signal Vst2 is 1/2 frame period, the first reset signal (1) generated after 1/2 frame period after the first scan signal Vg_1 ( The third transistor T1 is turned on by Vr_1 to discharge the first gate line G1. Thereafter, the first reset line R1 is discharged through the fourth transistor T2 that is turned on to the first scan signal Vg_1 generated after the half frame period. Similarly, such operations occur sequentially in the second to nth stages of the gate driving circuit 102 and the reset signal driving circuit 106.

As described above, the gate lines and the reset lines are discharged once again by using the outputs of different driving circuits, thereby reducing the reliability of the circuit due to partial charging occurring during driving.

FIG. 10 illustrates a driving device of an OLED display device including the gate driving circuit 102 and the reset line driving circuit 106 together with another specific configuration of the gate driving circuit 102 and the reset line driving circuit 106 of FIG. 7. It is shown. The driving device of the OLED display shown in FIG. 10 is a first transistor T1 for discharging the i-stage Q node of the gate driving circuit 102 in response to the reset signal Vr_i from the i-th reset line Ri. And a second transistor T2 for discharging the i-th stage Q node of the reset line driver circuit 106 in response to the scan signal Vg_i from the i-th gate line Gi, and the i-th reset line Ri. The i-th reset line Ri in response to the scan signal Vg_i from the third transistor T3 and the i-th gate line Gi which discharge the i-th gate line Gi in response to the reset signal Vr_i ) Is provided with a fourth transistor.

Referring to FIG. 10, when the start scene Vst1 is input to the first stage of the gate driving circuit 102, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having the high voltage is supplied to the first gate line G1 as the first scan signal Vg_1 through the pull-up transistor T-up and simultaneously supplied to the second stage. The Q node of two stages is charged and the QB node is discharged.

Subsequently, the second scan signal Vg_2 generated in the second stage by the second clock signal C2 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. G1 is discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are made by the scan signal Vg_3 supplied from the third stage. In such an operation, the gate driving circuit 102 and the reset line driving circuit 106 sequentially supply scan signals and reset signals to the gate lines and the reset lines.

On the other hand, if the time interval between the first start signal Vst1 and the second start signal Vst2 is 1/2 frame period, the first reset signal (1) generated after 1/2 frame period after the first scan signal Vg_1 ( The first and third transistors T1 and T3 are turned on by Vr_1 to discharge the first stage Q node and the first gate line G1 of the gate driving circuit 102. Thereafter, the first stage Q node and the first stage of the reset signal driving circuit 106 through the second and fourth transistors T2 turned on to the first scan signal Vg_1 generated after the half frame period. The reset line R1 is discharged. Similarly, such operations occur sequentially in the second to nth stages of the gate driving circuit 102 and the reset signal driving circuit 106.

As described above, the Q node, the gate lines, and the reset lines are discharged once more by using the outputs of the different driving circuits, thereby overcoming the reliability deterioration of the circuit due to the partial charging occurring during the driving.

FIG. 11 shows a gate driving circuit 202 and a reset signal driving circuit 207 having a different configuration from the gate driving circuit 102 and the reset signal driving circuit 106 in FIG.

The gate driving circuit 202 in FIG. 11 has the same configuration as the gate driving circuit in FIG. 7, but the reset signal driving circuit 206 has a configuration different from that of the reset signal driving circuit 106 in FIG. 7. That is, the gate driving circuit 202 in FIG. 11 includes n stages, while the reset signal driving circuit 206 includes only n / 2 stages.

Referring to FIG. 11, a first start signal Vst1 is input to a first stage of the gate driving circuit 202 and a previous scan signal Vg_i-1 is input to the second to nth stages as a start signal. . The next stage scan signal Vg_i + 1 is input as the stage reset signal to the first to n-th stages, and the stage reset signal is input to a n-th stage from a dummy stage (not shown). In addition, each stage has the same circuit configuration and shifts the first start signal Vst1 or the previous stage scan signal Vg_i in response to any one of the four clock signals C1 to C4, thereby providing one horizontal period. A scan signal having a pulse width is generated.

Meanwhile, the second start signal Vst2 is input to the first stage of the reset signal driving circuit 206 having n / 2 stages and the previous stage reset signal as the start signal to the second to n / 2 stages. (Vr_k-1, where k is a positive integer less than or equal to n / 2) is input. The next stage reset signal Vr_k + 1 is input as the stage reset signal to the first to (n / 2) -1 stages, and the stage reset signal is input from a dummy stage (not shown) to the n / 2 stage. Is entered. The clock signal supplied to the reset signal driving circuit 206 has a 1/2 clock frequency of the clock signal supplied to the gate driving circuit 202. In addition, the k-th stage of the reset signal driving circuit 206 simultaneously supplies the reset signal to the second k-1 reset line R2k and the second k reset line R2k-1. The second start signal Vst2 is supplied at a predetermined time interval from the first start signal Vst1. Such a time interval is suitable such that the reset signal supplied to the k-th reset line may be delayed than the scan signal supplied to the second k-gate line G2k.

FIG. 12 illustrates a driving device of the OLED display device including the gate driving circuit 202 and the reset line driving circuit 206 together with the specific configurations of the gate driving circuit 202 and the reset line driving circuit 206 of FIG. 11. will be. The driving device of the OLED display illustrated in FIG. 12 includes a first transistor configured to discharge the second k-1 stage Q node of the gate driving circuit 202 in response to the reset signal Vr_k from the k-th reset line Rk. T1, a second transistor T2 for discharging the second k stage Q node of the gate driving circuit 202 in response to the reset signal Vr_k from the k-th reset line Rk, and a second k-1 gate line. The third transistor T3 and the second k-1 gate line G2k-1 which discharge the k-th stage Q node of the reset signal driving circuit 206 in response to the scan signal Vg_2k-1 from the G2k-1. The fourth transistor T4 discharges the second k-1 and the second k reset lines R2k-1 and R2k in response to the scan signal Vg_2k-1 from FIG.

Referring to FIG. 12, when the start signal Vst1 is input to the first stage of the gate driving circuit 202, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having the high voltage is supplied to the first gate line G1 as the first scan signal Vg_1 through the pull-up transistor T-up and simultaneously supplied to the second stage. The Q node of two stages is charged and the QB node is discharged.

Subsequently, the second scan signal Vg_2 generated in the second stage by the second clock signal C2 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. G1 is discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are made by the scan signal Vg_3 supplied from the third stage. In this manner, the gate driving circuit 202 sequentially supplies scan signals to the gate lines.

When the start signal Vst1 is input to the first stage of the reset line driving circuit 206, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having a high voltage is supplied to the first and second reset lines R1 and R2 as the first reset signal Vr_1 through the pull-up transistor T-up and at the same time, the second clock signal is supplied to the first and second reset lines R1 and R2. It is supplied to the stage to charge the Q node of the second stage and discharge the QB node.

Subsequently, the second reset signal Vg_2 generated in the second stage by the third clock signal C3 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. The two reset lines R1 and R2 are discharged through the pull-down transistor T_dn of the first stage. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are performed by the reset signal Vg_3 supplied from the third stage. In this manner, the reset line driver circuit 206 sequentially supplies reset signals to the reset lines.

On the other hand, if the time interval between the first start signal Vst1 and the second start signal Vst2 is 1/2 frame period, the first reset signal (1) generated after 1/2 frame period after the first scan signal Vg_1 ( The first and second transistors T1 are turned on by Vr_1 to discharge the first stage Q node and the second stage Q node of the gate driving circuit 202, which occur after 1/2 frame period. The first stage Q node and the first and second reset lines R1 and R2 of the reset signal driving circuit 206 through the third and fourth transistors T3 turned on by the first scan signal Vg_1. Is discharged. Similarly, the same operation occurs sequentially in the second through nth stages of the gate driving circuit 202 and the second through n / 2 stages of the reset signal driving circuit 206.

As described above, the Q node of the gate driving circuit, the Q node of the reset signal driving circuit and the reset line are discharged once more by using the outputs of the different driving circuits to overcome the degradation of the reliability of the circuit due to the partial charging occurring during the driving. have.

FIG. 13 illustrates a driving device of an OLED display device including the gate driving circuit 202 and the reset line driving circuit 206 together with other specific configurations of the gate driving circuit 202 and the reset line driving circuit 206 of FIG. 11. It is shown. The driving device of the OLED display illustrated in FIG. 12 discharges the second k-1 and the second k gate lines G2k-1 and G2k in response to the reset signal Vr_k from the k-th reset line Rk. And a third transistor T3 for discharging the kth stage Q node of the reset signal driver circuit 206 in response to the sixth transistor and the scan signal Vg_2k-1 from the second k-1 gate line G2k-1. ) And a fourth transistor T4 that discharges the second k-1 and second k reset lines R2k-1 and R2k in response to the scan signal Vg_2k-1 from the second k-1 gate line G2k-1. It is provided.

Referring to FIG. 13, when the start signal Vst1 is input to the first stage of the gate driving circuit 202, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having the high voltage is supplied to the first gate line G1 as the first scan signal Vg_1 through the pull-up transistor T-up and simultaneously supplied to the second stage. The Q node of two stages is charged and the QB node is discharged.

Subsequently, the second scan signal Vg_2 generated in the second stage by the second clock signal C2 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. G1 is discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are made by the scan signal Vg_3 supplied from the third stage. In this manner, the gate driving circuit 202 sequentially supplies scan signals to the gate lines.

When the start signal Vst1 is input to the first stage of the reset line driving circuit 206, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having a high voltage is supplied to the first and second reset lines R1 and R2 as the first reset signal Vr_1 through the pull-up transistor T-up and at the same time, the second clock signal is supplied to the second and second reset lines R1 and R2. It is supplied to the stage to charge the Q node of the second stage and discharge the QB node.

Subsequently, the second reset signal Vg_2 generated in the second stage by the third clock signal C3 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. The two lines R1 and R2 are discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are performed by the reset signal Vg_3 supplied from the third stage. In this manner, the reset line driver circuit 206 sequentially supplies reset signals to the reset lines.

On the other hand, if the time interval between the first start signal Vst1 and the second start signal Vst2 is 1/2 frame period, the first reset signal (1) generated after 1/2 frame period after the first scan signal Vg_1 ( The fifth and sixth transistors T5 and T6 are turned on by Vr_1 to discharge the first and second gate lines G1 and G2, and the first scan signal generated after 1/2 frame period thereafter. The first stage Q node and the first and second reset lines R1 and R2 of the reset signal driving circuit 206 are discharged through the third and fourth transistors T3 turned on by Vg_1. Similarly, the same operation occurs sequentially in the second through nth stages of the gate driving circuit 202 and the second through n / 2 stages of the reset signal driving circuit 206.

As described above, the Q node and the reset line of the gate line and the reset signal driving circuit are discharged once more by using the outputs of the different driving circuits to overcome the degradation of the reliability of the circuit due to the partial charging occurring during the driving.

FIG. 14 illustrates an OLED display driving device including the gate driving circuit 202 and the reset line driving circuit 206 together with another specific configuration of the gate driving circuit 202 and the reset line driving circuit 206 of FIG. 11. It is shown. The driving device of the OLED display illustrated in FIG. 12 includes a first transistor configured to discharge the second k-1 stage Q node of the gate driving circuit 202 in response to the reset signal Vr_k from the k-th reset line Rk. T1, a second transistor T2 for discharging the second k stage Q node of the gate driving circuit 202 in response to the reset signal Vr_k from the k-th reset line Rk, and a second k-1 gate line. The third transistor T3 and the second k-1 gate line G2k-1 which discharge the k-th stage Q node of the reset signal driving circuit 206 in response to the scan signal Vg_2k-1 from the G2k-1. 4th transistor T4 which discharges 2k-1 and 2k reset lines R2k-1 and R2k in response to scan signal Vg_2k-1 from &lt; RTI ID = 0.0 &gt; 1, &lt; / RTI &gt; and reset from kth reset line Rk. And fifth and sixth transistors that discharge the second k-1 and second k gate lines G2k-1 and G2k in response to the signal Vr_k.

Referring to FIG. 14, when the start signal Vst1 is input to the first stage of the gate driving circuit 202, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having the high voltage is supplied to the first gate line G1 as the first scan signal Vg_1 through the pull-up transistor T-up and simultaneously supplied to the second stage. The Q node of two stages is charged and the QB node is discharged.

Subsequently, the second scan signal Vg_2 generated in the second stage by the second clock signal C2 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. G1 is discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are made by the scan signal Vg_3 supplied from the third stage. In this manner, the gate driving circuit 202 sequentially supplies scan signals to the gate lines.

When the start signal Vst1 is input to the first stage of the reset line driving circuit 206, the Q node is charged and the QB node is discharged. Subsequently, the first clock signal having a high voltage is supplied to the first and second reset lines R1 and R2 as the first reset signal Vr_1 through the pull-up transistor T-up and at the same time, the second clock signal is supplied to the first and second reset lines R1 and R2. It is supplied to the stage to charge the Q node of the second stage and discharge the QB node.

Subsequently, the second reset signal Vg_2 generated in the second stage by the third clock signal C3 is supplied to the first stage to discharge the Q node of the first stage and charge the QB node. The two lines R1 and R2 are discharged through the pull-down transistor T_dn. Similarly, the discharge of the Q node of the second stage and the charge of the QB node are performed by the reset signal Vg_3 supplied from the third stage. In this manner, the reset line driver circuit 206 sequentially supplies reset signals to the reset lines.

On the other hand, if the time interval between the first start signal Vst1 and the second start signal Vst2 is 1/2 frame period, the first reset signal (1) generated after 1/2 frame period after the first scan signal Vg_1 ( Vr_1) turns on the first, second fifth and sixth transistors T1, T2, T5, and T6 to turn on the first and second stage Q nodes and the first and second stages of the gate driving circuit 202. After the gate lines G1 and G2 are discharged, the reset signal driver circuits 3 and 4 are turned on by the first and fourth transistors T3 that are turned on by the first scan signal Vg_1 that occurs after a half frame period. The first stage Q node and the first and second reset lines R1 and R2 of 206 are discharged. Similarly, the same operation occurs sequentially in the second through nth stages of the gate driving circuit 202 and the second through n / 2 stages of the reset signal driving circuit 206.

As such, the Q node of the gate driving circuit and the reset signal driving circuit, the gate line and the reset line are discharged once more by using the outputs of the different driving circuits to overcome the degradation of the reliability of the circuit due to the partial charging occurring during the driving. have.

As described above, the organic light emitting diode display and the driving device according to the embodiment of the present invention use the outputs of the different driving circuits to perform the Q node, the gate line, and the reset line of the gate driving circuit and the reset signal driving circuit once. By further discharging, the reliability of the operation of the driving circuit is secured.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (90)

A first pull-up transistor for supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node, the first signal line G1 in response to a voltage on a first QB node A first pull-down transistor for discharging the first Q, a first controller controlling the first Q and the first QB node, and a first control signal Vr_1 from the second signal line R1. A gate driving circuit comprising a first transistor for discharging a node; A second pull-up transistor that supplies the second control signal Vr_1 to the second signal line R1 in response to a voltage on a second Q node, the second signal line in response to a voltage on a second QB node A second pull-down transistor for discharging R1, a second controller for controlling the second Q and second QB nodes, and a second for discharging the second Q node in response to the first control signal Vg_1. And a reset signal driving circuit comprising a transistor (T2). The method of claim 1, At least one of the first and second transistors is an amorphous transistor, the driving device of the organic light emitting diode display. The method of claim 2, And the second control signal is delayed than the first control signal. The method of claim 3, wherein And the second control signal is delayed by 1/2 frame period than the first control signal. The method of claim 1, At least one of the first and second transistors is a drive device of an organic light emitting diode display, characterized in that the polycrystalline transistor. The method of claim 5, And the second control signal is delayed than the first control signal. The method of claim 6, And the second control signal is delayed by 1/2 frame period than the first control signal. A first pull-up transistor for supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node, the first signal line G1 in response to a voltage on a first QB node A gate driving circuit including a first pull-down transistor for discharging the first transistor and a first control unit for controlling the first Q and the first QB nodes; A second pull-up transistor that supplies the second control signal Vr_1 to a second signal line R1 in response to a voltage on a second Q node, the second signal line in response to a voltage on a second QB node; A reset signal driving circuit including a second pull-down transistor for discharging R1), and a second controller for controlling the second Q and second QB nodes; A first transistor (T3) for discharging the first signal line (G1) in response to the second control signal (Vr_1) from the second signal line (R1); And a second transistor (T4) for discharging the second signal line (R1) in response to the first control signal (Vg_1) from the first signal line (G1). Drive. The method of claim 8, At least one of the first and second transistors is an amorphous transistor, the driving device of the organic light emitting diode display. The method of claim 9, And the second control signal is delayed than the first control signal. The method of claim 10, And the second control signal is delayed by 1/2 frame period than the first control signal. The method of claim 8, At least one of the first and second transistors is a drive device of an organic light emitting diode display, characterized in that the polycrystalline transistor. The method of claim 12, And the second control signal is delayed than the first control signal. The method of claim 13, And the second control signal is delayed by 1/2 frame period than the first control signal. A first pull-up transistor for supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node, the first signal line G1 in response to a voltage on a first QB node A first pull-down transistor for discharging the first Q, a first controller controlling the first Q and the first QB node, and a first control signal Vr_1 from the second signal line R1. A gate driving circuit comprising a first transistor for discharging a node; A second pull-up transistor that supplies the second control signal Vr_1 to the second signal line R1 in response to a voltage on a second Q node, the second signal line in response to a voltage on a second QB node A second pull-down transistor for discharging R1, a second controller for controlling the second Q and second QB nodes, and a second for discharging the second Q node in response to the first control signal Vg_1. A reset signal driving circuit including a transistor T2; A third transistor (T3) for discharging the first signal line (G1) in response to the second control signal (Vr_1) from the second signal line (R1); And a fourth transistor (T4) for discharging the second signal line (R1) in response to the first control signal (Vg_1) from the first signal line (G1). Drive. The method of claim 15, At least one of the first to fourth transistors is an amorphous transistor, characterized in that the driving device of the organic light emitting diode display. The method of claim 16, And the second control signal is delayed than the first control signal. The method of claim 17, And the second control signal is delayed by 1/2 frame period than the first control signal. The method of claim 15, At least one of the first to fourth transistors is a driving device of an organic light emitting diode display, characterized in that the polycrystalline transistor. The method of claim 19, And the second control signal is delayed than the first control signal. The method of claim 20, And the second control signal is delayed by 1/2 frame period than the first control signal. A first pull-up transistor for supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node, the first signal line G1 in response to a voltage on a first QB node ) A first pull-down transistor for discharging the second control signal; a first control unit controlling the first Q and first QB nodes; and a second control signal Vg_2 in response to a voltage on the second Q node. A second pull-up transistor for supplying the second pull-up transistor, a second pull-down transistor for discharging the second signal line G2 in response to a voltage on a second QB node, and controlling the second Q and second QB nodes. A second control unit, the first transistor T1 for discharging the first Q node in response to the third control signal Vr_1 from the third signal line R1 and the third from the third signal line R1. A gate driving circuit including a second transistor T2 for discharging the second Q node in response to a third control signal Vr_1 Wow; A third pull-up transistor for supplying the third control signal Vr_1 to the third signal line R1 and the fourth signal line R2 in response to a voltage on a third Q node, a voltage on a third QB node In response to the third pull-down transistor for discharging the third and fourth signal lines R1 and R2, the third controller for controlling the third Q and third QB nodes, and the first signal line G1. A reset signal driving circuit comprising a third transistor (T3) for discharging the third Q node in response to a first control signal (Vg_1) from the first control signal (Vg_1); And a fourth transistor T4 for discharging the third and fourth signal lines R1 and R2 in response to the first control signal Vg_1 from the first signal line G1. Driving device of organic light emitting diode display. The method of claim 22, At least one of the first to fourth transistors is an amorphous transistor, the driving device of the organic light emitting diode display. The method of claim 23, wherein And the third control signal is delayed than the first control signal. The method of claim 24, And the third control signal is delayed by 1/2 frame period than the first control signal. The method of claim 22, At least one of the first to fourth transistors is a driving device of an organic light emitting diode display, characterized in that the polycrystalline transistor. The method of claim 26, And the third control signal is delayed than the first control signal. The method of claim 27, And the third control signal is delayed by 1/2 frame period than the first control signal. A first pull-up transistor for supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node, the first signal line G1 in response to a voltage on a first QB node ) A first pull-down transistor for discharging the second control signal; a first control unit controlling the first Q and first QB nodes; and a second control signal Vg_2 in response to a voltage on the second Q node. To control the second pull-up transistor, the second pull-down transistor to discharge the second signal line G2 in response to the voltage on the second QB node, and the second Q and second QB nodes. A gate driving circuit including a second control unit; A third pull-up transistor for supplying a third control signal Vr_1 to the third signal line R1 and the fourth signal line R2 in response to a voltage on a third Q node, to a voltage on a third QB node; A third pull-down transistor that discharges the third and fourth signal lines R1 and R2 in response, a third controller that controls the third Q and third QB nodes, and the first signal line G1. A reset signal driving circuit including a first transistor (T3) for discharging the third Q node in response to a first control signal (Vg_1); A second transistor (T4) for discharging the third and fourth signal lines (R1, R2) in response to the first control signal (Vg_1) from the first signal line (G1); A third transistor (T5) for discharging the first signal line (G1) in response to the third control signal (Vr_1) from the third signal line (R1); And a fourth transistor T6 for discharging the second signal line G2 in response to the third control signal Vr_1 from the third signal line R1. Drive. The method of claim 29, At least one of the first to fourth transistors is an amorphous transistor, characterized in that the driving device of the organic light emitting diode display. The method of claim 30, And the third control signal is delayed than the first control signal. The method of claim 31, wherein And the third control signal is delayed by 1/2 frame period than the first control signal. The method of claim 29, At least one of the first to fourth transistors is a driving device of an organic light emitting diode display, characterized in that the polycrystalline transistor. The method of claim 30, And the third control signal is delayed than the first control signal. The method of claim 34, wherein And the third control signal is delayed by 1/2 frame period than the first control signal. A first pull-up transistor for supplying a first control signal Vg_1 to a first signal line G1 in response to a voltage on a first Q node, the first signal line G1 in response to a voltage on a first QB node ) A first pull-down transistor for discharging the second control signal; a first control unit controlling the first Q and first QB nodes; and a second control signal Vg_2 in response to a voltage on the second Q node. A second pull-up transistor for supplying the second pull-up transistor, a second pull-down transistor for discharging the second signal line G2 in response to a voltage on a second QB node, and controlling the second Q and second QB nodes A second control unit, the first transistor T1 for discharging the first Q node in response to the third control signal Vr_1 from the third signal line R1 and the third from the third signal line R1. A gate driving circuit including a second transistor T2 for discharging the second Q node in response to a third control signal Vr_1 Wow; A third pull-up transistor for supplying the third control signal Vr_1 to the third signal line R1 and the fourth signal line R2 in response to a voltage on a third Q node, a voltage on a third QB node In response to the third pull-down transistor for discharging the third and fourth signal lines R1 and R2, the third controller for controlling the third Q and third QB nodes, and the first signal line G1. A reset signal driving circuit comprising a third transistor (T3) for discharging the third Q node in response to a first control signal (Vg_1) from the first control signal (Vg_1); A fourth transistor (T4) for discharging the third and fourth signal lines (R1, R2) in response to the first control signal (Vg_1) from the first signal line (G1); A fifth transistor (T5) for discharging the first signal line (G1) in response to the third control signal (Vr_1) from the third signal line (R1); And a sixth transistor T6 for discharging the second signal line G2 in response to the third control signal Vr_1 from the third signal line R1. Drive. The method of claim 36, At least one of the first to sixth transistors is an amorphous transistor, the driving device of the organic light emitting diode display. The method of claim 37, And the third control signal is delayed than the first control signal. The method of claim 38, And the third control signal is delayed by 1/2 frame period than the first control signal. The method of claim 36, At least one of the first to sixth transistors is a driving device of an organic light emitting diode display, characterized in that the polycrystalline transistor. The method of claim 40, And the third control signal is delayed than the first control signal. 42. The method of claim 41 wherein And the third control signal is delayed by 1/2 frame period than the first control signal. A first signal line G1 and a data line crossing each other; A power supply voltage supply line supplied with a high potential power supply voltage and disposed in parallel with the data line; A second signal line R1 disposed in parallel with the first signal line G1; The organic light emitting diode emits light with the current generated by the high potential power voltage from the power supply line and the data voltage from the data line in response to the first control signal Vg_1 from the first signal line G1. A pixel including an organic light emitting diode driving circuit which drives the organic light emitting diode and is initialized in response to a second control signal Vr_2 from the second signal line R1; A first pull-up transistor that supplies the first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, the first signal line in response to a voltage on a first QB node A first pull-down transistor for discharging (G1), a first controller for controlling the first Q and first QB nodes, and the second control signal Vr_1 from the second signal line R1; A gate driving circuit including a first transistor for discharging a 1 Q node and a second pull-up supplying the second control signal Vr_1 to the second signal line R1 in response to a voltage on the second Q node. A transistor, a second pull-down transistor that discharges the second signal line R1 in response to a voltage on a second QB node, a second control unit that controls the second Q and second QB nodes, and the first control signal And a second transistor T2 for discharging the second Q node in response to Vg_1. The driving device comprising a driving circuit and to the reset signal; A data driver circuit for supplying said data voltage to said data line; The driving device may be formed on the same substrate as the substrate on which the first signal line G1, the second signal line R1, the data line, the power voltage supply line, and the pixel are formed. Light emitting diode display device. The method of claim 43, The organic light emitting diode driving circuit, A third transistor T1 for supplying a data voltage to the first node in response to the scan signal; A fourth transistor (T2) for controlling the amount of current flowing in the organic light emitting diode by the voltage on the first node; And a fifth transistor (T3) for discharging the first node in response to the second control signal. The method of claim 44, At least one of the first to fifth transistors is an amorphous transistor, characterized in that the organic light emitting diode display. The method of claim 45, The second control signal is delayed than the first control signal. The method of claim 46, And the second control signal is delayed by 1/2 frame period than the first control signal. The method of claim 44, At least one of the first to fifth transistors is a polycrystalline transistor, characterized in that the organic light emitting diode display. 49. The method of claim 48 wherein The second control signal is delayed than the first control signal. The method of claim 49, And the second control signal is delayed by 1/2 frame period than the first control signal. A first signal line G1 and a data line crossing each other; A power supply voltage supply line supplied with a high potential power supply voltage and disposed in parallel with the data line; A second signal line R1 disposed in parallel with the first signal line G1; The organic light emitting diode emits light with the current generated by the high potential power voltage from the power supply line and the data voltage from the data line in response to the first control signal Vg_1 from the first signal line G1. A pixel including an organic light emitting diode driving circuit which drives the organic light emitting diode and is initialized in response to a second control signal Vr_2 from the second signal line R1; A first pull-up transistor that supplies the first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, the first signal line in response to a voltage on a first QB node A gate driving circuit including a first pull-down transistor for discharging (G1) and a first controller for controlling the first Q and first QB nodes, and the second control signal in response to a voltage on a second Q node ( A second pull-up transistor for supplying Vr_1 to the second signal line R1, a second pull-down transistor for discharging the second signal line R1 in response to a voltage on a second QB node, and the second pull-up transistor; 2. A reset signal driving circuit including a second control unit controlling a 2 Q and a 2 QB node, and the first signal line G1 in response to the second control signal Vr_1 from the second signal line R1. The first transistor T3 and the first signal from the first signal line G1 to discharge In response to the control signal (Vg_1) and the drive system including a second transistor (T4) for discharging the second signal line (R1); A data driver circuit for supplying said data voltage to said data line; The driving device may be formed on the same substrate as the substrate on which the first signal line G1, the second signal line R1, the data line, the power voltage supply line, and the pixel are formed. Light emitting diode display device. The method of claim 51, wherein The organic light emitting diode driving circuit, A third transistor T1 for supplying a data voltage to the first node in response to the scan signal; A fourth transistor (T2) for controlling the amount of current flowing in the organic light emitting diode by the voltage on the first node; And a fifth transistor (T3) for discharging the first node in response to the second control signal. The method of claim 52, wherein At least one of the first to fifth transistors is an amorphous transistor, characterized in that the organic light emitting diode display. The method of claim 53 wherein The second control signal is delayed than the first control signal. The method of claim 54, wherein And the second control signal is delayed by 1/2 frame period than the first control signal. The method of claim 52, wherein At least one of the first to fifth transistors is a polycrystalline transistor, characterized in that the organic light emitting diode display. The method of claim 56, wherein The second control signal is delayed than the first control signal. The method of claim 57, And the second control signal is delayed by 1/2 frame period than the first control signal. A first signal line G1 and a data line crossing each other; A power supply voltage supply line supplied with a high potential power supply voltage and disposed in parallel with the data line; A second signal line R1 disposed in parallel with the first signal line G1; The organic light emitting diode emits light with the current generated by the high potential power voltage from the power supply line and the data voltage from the data line in response to the first control signal Vg_1 from the first signal line G1. A pixel including an organic light emitting diode driving circuit which drives the organic light emitting diode and is initialized in response to a second control signal Vr_2 from the second signal line R1; A first pull-up transistor that supplies the first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, the first signal line in response to a voltage on a first QB node In response to the second control signal Vr_1 from the first pull-down transistor for discharging (G1), the first control unit for controlling the first Q and first QB nodes, and the second signal line R1. A gate driving circuit including a first transistor for discharging the first Q node, and a second pool supplying the second control signal Vr_1 to the second signal line R1 in response to a voltage on a second Q node. An up-transistor, a second pull-down transistor that discharges the second signal line R1 in response to a voltage on a second QB node, a second control unit that controls the second Q and second QB nodes and the first The second transistor T2 discharges the second Q node in response to a control signal Vg_1. A reset signal driving circuit comprising: a third transistor (T3) and the first signal discharging the first signal line (G1) in response to the second control signal (Vr_1) from the second signal line (R1); A driving device including a fourth transistor (T4) for discharging the second signal line (R1) in response to the first control signal (Vg_1) from a line (G1); The driving device may be formed on the same substrate as the substrate on which the first signal line G1, the second signal line R1, the data line, the power voltage supply line, and the pixel are formed. Light emitting diode display device. The method of claim 59, The organic light emitting diode driving circuit, A fifth transistor T1 supplying a data voltage to the first node in response to the scan signal; A sixth transistor (T2) for controlling the amount of current flowing through the organic light emitting diode by the voltage on the first node; And a seventh transistor (T3) for discharging the first node in response to the second control signal. The method of claim 60, At least one of the first to seventh transistors is an amorphous transistor, characterized in that the organic light emitting diode display. 62. The method of claim 61, The second control signal is delayed than the first control signal. 63. The method of claim 62, And the second control signal is delayed by 1/2 frame period than the first control signal. The method of claim 60, And at least one of the first to seventh transistors is a polycrystalline transistor. The method of claim 64, wherein The second control signal is delayed than the first control signal. 66. The method of claim 65, And the second control signal is delayed by 1/2 frame period than the first control signal. A data line to which a data voltage is supplied; First and second signal lines G1 and G2 intersecting the data lines; A power supply voltage supply line supplied with a high potential power supply voltage and disposed in parallel with the data line; Third and fourth signal lines R1 and R2 disposed in parallel to the first and second signal lines G1 and G2; A first pull-up transistor for supplying a first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, and the first signal line in response to a voltage on a first QB node. A first pull-down transistor for discharging G1), a first controller for controlling the first Q and first QB nodes, and a second control signal Vg_2 in response to a voltage on a second Q node; A second pull-up transistor for supplying (G2), a second pull-down transistor for discharging the second signal line (G2) in response to a voltage on a second QB node, the second Q and the second QB node; A second control unit for controlling the first control unit T1 and the third signal line R1 that discharge the first Q node in response to a third control signal Vr_1 from the third signal line R1. And a second transistor T2 configured to discharge the second Q node in response to the third control signal Vr_1. A third pull-up transistor configured to supply the third control signal Vr_1 to the third and fourth signal lines R1 and R2 in response to a voltage on a third driving node and a third Q node, on a third QB node. A third pull-down transistor for discharging the third and fourth signal lines R1 and R2 in response to a voltage, a third controller for controlling the third Q and third QB nodes, and the first signal line G1; Reset signal driving circuit comprising a third transistor (T3) for discharging the third Q node in response to the first control signal (Vg_1) from the first control signal (Vg_1), the first control from the first signal line (G1) A driving device having a fourth transistor (T4) for discharging the third and fourth signal lines (R1, R2) in response to a signal (Vg_1); Data from the data line in response to a first organic light emitting diode that emits light with a current generated by a high potential power voltage from the power supply line and a first control signal Vg_1 from the first signal line G1. A first pixel including a first organic light emitting diode driving circuit which drives the first organic light emitting diode with a voltage and is initialized in response to the third control signal Vr_1 from the third signal line R1; Data from the data line in response to a second organic light emitting diode and a second control signal Vg_1 from the second signal line G2 that emit light with a current generated by a high potential power voltage from the power supply line. A second pixel including a second organic light emitting diode driving circuit which drives the second organic light emitting diode with a voltage and is initialized in response to the third control signal Vr_1 from the fourth signal line R2; A data driver circuit for supplying said data voltage to said data line; The driving device is formed on the same substrate as the substrate on which the first to fourth signal lines G1, G2, R1, and R2, the data line, the power voltage supply line, and the first and second pixels are formed. An organic light emitting diode display device with a built-in drive circuit. The method of claim 67 wherein The organic light emitting diode driving circuit, A fifth transistor T1 supplying a data voltage to the first node in response to the scan signal; A sixth transistor (T2) for controlling the amount of current flowing through the organic light emitting diode by the voltage on the first node; And a seventh transistor (T3) for discharging the first node in response to the second control signal. The method of claim 68, wherein At least one of the first to seventh transistors is an organic light emitting diode display device, characterized in that the amorphous transistor. The method of claim 69, And the second control signal is delayed than the first control signal. The method of claim 70, And the second control signal is delayed by a half frame period than the first control signal. The method of claim 68, wherein At least one or more of the first to seventh transistors are polycrystalline transistors. The method of claim 72, And the second control signal is delayed than the first control signal. The method of claim 73, wherein And the second control signal is delayed by a half frame period than the first control signal. A data line to which a data voltage is supplied; First and second signal lines G1 and G2 intersecting the data lines; A power supply voltage supply line supplied with a high potential power supply voltage and disposed in parallel with the data line; Third and fourth signal lines R1 and R2 disposed in parallel to the first and second signal lines G1 and G2; A first pull-up transistor for supplying a first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, and the first signal line in response to a voltage on a first QB node. A first pull-down transistor for discharging G1), a first controller for controlling the first Q and first QB nodes, and a second control signal Vg_2 in response to a voltage on a second Q node; A second pull-up transistor for supplying (G2), a second pull-down transistor for discharging the second signal line (G2) in response to a voltage on a second QB node, and the second Q and second QB nodes; A gate driving circuit including a second control unit for controlling the third pull-up supplying a third control signal Vr_1 to the third and fourth signal lines R1 and R2 in response to a voltage on a third Q node; Transistor, a third pull-down that discharges the third and fourth signal lines R1 and R2 in response to a voltage on a third QB node A transistor, a third controller for controlling the third Q and third QB nodes, and a first for discharging the third Q node in response to the first control signal Vg_1 from the first signal line G1. A reset signal driving circuit including a transistor T3, and a discharge unit configured to discharge the third and fourth signal lines R1 and R2 in response to the first control signal Vg_1 from the first signal line G1. A third transistor T5 and the third signal line which discharge the first signal line G1 in response to the second transistor T4 and the third control signal Vr_1 from the third signal line R1. A driving device having a fourth transistor (T6) for discharging said second signal line (G2) in response to said third control signal (Vr_1) from (R1); Data from the data line in response to a first organic light emitting diode that emits light with a current generated by a high potential power voltage from the power supply line and a first control signal Vg_1 from the first signal line G1. A first pixel including a first organic light emitting diode driving circuit which drives the first organic light emitting diode with a voltage and is initialized in response to the third control signal Vr_1 from the third signal line R1; Data from the data line in response to a second organic light emitting diode and a second control signal Vg_1 from the second signal line G2 that emit light with a current generated by a high potential power voltage from the power supply line. A second pixel including a second organic light emitting diode driving circuit which drives the second organic light emitting diode with a voltage and is initialized in response to the third control signal Vr_1 from the fourth signal line R2; A data driver circuit for supplying said data voltage to said data line; The driving device is formed on the same substrate as the substrate on which the first to fourth signal lines G1, G2, R1, and R2, the data line, the power voltage supply line, and the first and second pixels are formed. An organic light emitting diode display device with a built-in drive circuit. 76. The method of claim 75 wherein The organic light emitting diode driving circuit, A fifth transistor T1 supplying a data voltage to the first node in response to the scan signal; A sixth transistor (T2) for controlling the amount of current flowing through the organic light emitting diode by the voltage on the first node; And a seventh transistor (T3) for discharging the first node in response to the second control signal. 77. The method of claim 76, At least one of the first to seventh transistors is an organic light emitting diode display device, characterized in that the amorphous transistor. 78. The method of claim 77 wherein And the second control signal is delayed than the first control signal. The method of claim 78, And the second control signal is delayed by a half frame period than the first control signal. 77. The method of claim 76, At least one or more of the first to seventh transistors are polycrystalline transistors. 81. The method of claim 80, And the second control signal is delayed than the first control signal. 82. The method of claim 81 wherein And the second control signal is delayed by a half frame period than the first control signal. A data line to which a data voltage is supplied; First and second signal lines G1 and G2 intersecting the data lines; A power supply voltage supply line supplied with a high potential power supply voltage and disposed in parallel with the data line; Third and fourth signal lines R1 and R2 disposed in parallel to the first and second signal lines G1 and G2; A first pull-up transistor for supplying a first control signal Vg_1 to the first signal line G1 in response to a voltage on a first Q node, and the first signal line in response to a voltage on a first QB node. A first pull-down transistor for discharging G1, a first controller for controlling the first Q and first QB nodes, and a second control signal Vg_2 in response to a voltage on the second Q node; A second pull-up transistor for supplying G2), a second pull-down transistor for discharging the second signal line G2 in response to a voltage on a second QB node, and controlling the second Q and second QB nodes The second control unit, the first transistor T1 for discharging the first Q node in response to the third control signal Vr_1 from the third signal line R1, and the first signal from the third signal line R1. A gate structure including a second transistor T2 for discharging the second Q node in response to a third control signal Vr_1 Circuit, a third pull-up transistor for supplying the third control signal Vr_1 to the third and fourth signal lines R1 and R2 in response to a voltage on a third Q node, to a voltage on a third QB node. A third pull-down transistor that discharges the third and fourth signal lines R1 and R2 in response, a third controller that controls the third Q and third QB nodes, and the first signal line G1. A reset signal driving circuit including a third transistor T3 for discharging the third Q node in response to a first control signal Vg_1 of the first control signal Vg_1, and the first control signal Vg_1 from the first signal line G1. The fourth transistor T4 for discharging the third and fourth signal lines R1 and R2, and the third control signal Vr_1 from the third signal line R1. In response to the fifth transistor T5 for discharging one signal line G1 and the third control signal Vr_1 from the third signal line R1. And the driving apparatus having a sixth transistor (T6) for discharging the second signal line (G2); Data from the data line in response to a first organic light emitting diode that emits light with a current generated by a high potential power voltage from the power supply line and a first control signal Vg_1 from the first signal line G1. A first pixel including a first organic light emitting diode driving circuit which drives the first organic light emitting diode with a voltage and is initialized in response to the third control signal Vr_1 from the third signal line R1; Data from the data line in response to a second organic light emitting diode and a second control signal Vg_1 from the second signal line G2 that emit light with a current generated by a high potential power voltage from the power supply line. A second pixel including a second organic light emitting diode driving circuit which drives the second organic light emitting diode with a voltage and is initialized in response to the third control signal Vr_1 from the fourth signal line R2; A data driver circuit for supplying said data voltage to said data line; The driving device is formed on the same substrate as the substrate on which the first to fourth signal lines G1, G2, R1, and R2, the data line, the power voltage supply line, and the first and second pixels are formed. An organic light emitting diode display device with a built-in drive circuit. 84. The method of claim 83 wherein The organic light emitting diode driving circuit, A seventh transistor T1 for supplying a data voltage to the first node in response to the scan signal; An eighth transistor (T2) for controlling the amount of current flowing in the organic light emitting diode by the voltage on the first node; And a ninth transistor (T3) for discharging the first node in response to the second control signal. 87. The method of claim 84, At least one of the first to ninth transistors is an amorphous transistor, characterized in that the organic light emitting diode display device with a built-in driving circuit. 86. The method of claim 85, And the second control signal is delayed than the first control signal. 87. The method of claim 86, And the second control signal is delayed by a half frame period than the first control signal. 87. The method of claim 84, At least one or more of the first to ninth transistors are polycrystalline transistors. 81. The method of claim 80, And the second control signal is delayed than the first control signal. 92. The method of claim 89, And the second control signal is delayed by a half frame period than the first control signal.

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