KR100681810B1 - High density and high current drivability phase change memory cell array and high speed low power consumption semiconductor devices comprising the same - Google Patents

Abstract

The present invention relates to a phase change memory device, and more particularly, to a phase change memory cell array and a semiconductor memory device having high current drivability, high integration, and low power consumption characteristics of a memory cell. The semiconductor memory device of the present invention includes a phase change memory unit cell including two or three access transistors sharing a source region and a gate voltage, and a phase change resistance element connected to the shared source region. According to the present invention, it is possible to provide a phase change memory device having high current driving performance.

Phase Change Memory, Word Line Stem, Word Line Branches, Contacts, Common Drain

Description

HIGH DENSITY AND HIGH CURRENT DRIVABILITY PHASE CHANGE MEMORY CELL ARRAY AND HIGH SPEED LOW POWER CONSUMPTION SEMICONDUCTOR DEVICES COMPRISING THE SAME}

FIG. 1A illustrates a digital data storage mechanism using electrical characteristics of a phase change resistance element used in a phase change memory.

1B is a graph showing a change in resistance of a phase change resistance device according to a current pulse normalized to a threshold reset current pulse value.

2 is an equivalent circuit diagram of a conventional memory unit cell using a phase change resistance element.

FIG. 3 is an equivalent circuit diagram of a unit cell array including a conventional memory unit cell of FIG. 2.

4A is a plan view illustrating a layout of the unit cell array of FIG. 3 disposed on a semiconductor substrate.

FIG. 4B is a cross-sectional view illustrating the semiconductor substrate of FIG. 4A taken along a line A-A '.

5 is an equivalent circuit diagram of a phase change memory unit cell according to an exemplary embodiment of the present invention.

FIG. 6 is a plan view illustrating a layout of a phase change memory unit cell of FIG. 5 implemented on a semiconductor substrate.

FIG. 7 is a block diagram reconstructing the memory cell array structure of FIG. 5 from the perspective of the standard cell of FIG. 6.

FIG. 8 is a block diagram schematically illustrating a memory cell area formed by the arrangement of the unit cell arrays UC shown in FIG. 7.

FIG. 9 is an equivalent circuit diagram of a standard cell having two unit cells shown in FIG. 5 as layout units.

FIG. 10 is a block diagram reconstructing the memory cell region of FIG. 8 from the perspective of the standard cell of FIG. 9.

FIG. 11 is a plan view illustrating a layout of a standard cell array DC described with reference to FIGS. 9 and 10 disposed on a semiconductor substrate 200.

FIG. 12 is a cross-sectional view of the cell array structure illustrated in FIG. 11 taken along a line B-B '.

FIG. 13 is a cross-sectional view illustrating a cross section taken along the line CC ′ of the cell array structure illustrated in FIG. 11.

FIG. 14 is an equivalent circuit diagram illustrating a unit cell array and a peripheral circuitry driving the unit cell array of the phase change memory device of the present invention.

The present invention relates to a phase change memory device, and more particularly, to a phase change memory cell array having high current drivability, high integration, and low power consumption, and a semiconductor memory device including the same.

With the spread of portable devices, the demand for nonvolatile memory devices is increasing rapidly. As nonvolatile memory devices, ferroelectric memory, magnetic memory, and phase change memory are attracting attention as well as flash memory which is widely used now. In particular, the phase change memory is able to overcome the disadvantages of the slow memory access speed, the number of uses, which is a disadvantage of the flash memory, and the research is focused as a new memory device that can solve the problem that a high voltage is required during operation.

Phase change memory is a memory device that uses a chalcogenide-based phase change material, which mainly contains Te or Se, as a resistive element among the chalcogenide elements belonging to group 16 (VIA) of the periodic table. -Sb-Te (mainly Ge ₂ Sb ₂ Te ₅ ) system is mainly used as the phase change material. The phase change resistive element has a phase change characteristic in which the state of the material is reversibly changed from the crystalline phase to the amorphous phase and vice versa according to the application condition of the thermal energy according to the initial state, and the two phases have the optical constant And physical resistances such as resistivity and the like, which are remarkable differences. These characteristics can be used in memory devices for the purpose of recording, erasing and reproducing information.

FIG. 1A illustrates a digital data storage mechanism using electrical characteristics of a phase change resistance element used in a phase change memory.

As shown, the phase change material is amorphous when the phase change resistance element is heated above the melting point Tm by a high-pressure Amorphizing RESET PULSE for a short period and then quenched. In addition, the phase change material is crystallized when a low voltage pulse (Crystallizing SET Pulse) is applied for a long time to heat the phase change material above the crystallization temperature (Tc) or below the melting point (Tm). Before and after the phase change process, the resistivity of the phase change resistive element is different, and the resistivity of the amorphous state is higher than that of the crystalline state. In the phase change memory, when the phase change resistance element is in a low resistance crystalline state, it is called a SET or ON state, and when it is in a high resistance amorphous state, it is called a RESET or OFF state. These states correspond to logic values '0' and '1' of the memory cell, respectively.

1B is a graph showing a change in resistance of a phase change resistance device according to a current pulse normalized to a threshold reset current pulse value. In the graph, when the initial state is set state (indicated by '□'), there is no change according to the increase in pulse size, but the state transitions to the reset state above the threshold reset current, and when the initial state is reset state ('■' It can be seen that the characteristic of first transitioning to a crystalline state with increasing pulse size and then transitioning to a reset state at or above a threshold reset current. Also, as can be seen from the graph, the specific resistance of the reset state and the set state is more than 100 times different, which shows that a sufficient signal ratio can be obtained only by the phase change of the local region of the phase change material.

2 is an equivalent circuit diagram of a conventional memory unit cell using a phase change resistance element.

Referring to FIG. 2, a phase change memory cell is composed of one access transistor T _A , such as a field emission transistor FET, and one phase change resistance element GST. The lower electrode of the phase change resistance element GST is connected to the source of the transistor T _A , and the upper electrode is connected to the bit line BL. In addition, the drain of the access transistor T _A is connected to a power supply line, and the gate of the transistor is connected to a word line WL. The conventional phase change memory unit cell structure is very similar to that of a conventional DRAM unit cell except for replacing the capacitor with a phase change resistance element.

3 is an equivalent circuit diagram of a unit cell array including a conventional memory unit cell described with reference to FIG. 2.

First, referring to FIG. 3, a unit cell array includes transistors TA0, TA1,..., TA7 having respective gates connected to a common word line WL, and a phase change resistor connected to a source of the transistor. (GST0, GST1, ..., GST7). The phase change resistance elements GST0, GST1,..., GST7 are again connected to the respective bit lines BL0, BL1,..., BL7. Although FIG. 3 illustrates a case where the unit cell array is composed of cells of 8 bits (eg, 8 bits as shown), the number of bits in the array may be appropriately changed as necessary.

In the conventional unit cell array of FIG. 3, one access transistor TA0, TA1, ..., TA7 is coupled to the phase change resistance elements GST0, GST1, ..., GST7, respectively. In the conventional memory device having such a structure, as the degree of integration of the memory cells is gradually increased and the gate widths of the access transistors TA0, TA1,..., TA7 are gradually reduced, sufficient current required for driving the memory devices is not secured. There is a problem that it is difficult to secure the stability and reliability of the device. Therefore, the conventional memory cell array structure is insufficient to cope with high integration of memory devices.

4A is a plan view illustrating a layout of the unit cell array of FIG. 3 disposed on the semiconductor substrate 100, and FIG. 4B is a cross-sectional view illustrating a cross section taken along the AA ′ direction of the semiconductor substrate of FIG. 4A. .

4A and 4B, an isolation layer 102 defining an active region 110 of a semiconductor device is formed in a predetermined region of the semiconductor substrate 100. On the active region 110, a pair of parallel word lines WL0 and WL1 serving as gates of the transistors intersect the active region 110, and the word lines WL0 and WL1 are transistors. Source region 112 and drain region 114 are defined. That is, the active region 110 between the pair of word lines WL0 and WL1 is defined as the common drain region 114 of the transistor, and two regions outside the word line are defined as the source region 112 of the transistor, respectively. do. As illustrated, a first interlayer insulating layer 162 is interposed between the semiconductor substrate 100 and the transistor, and a common drain region 114 of the transistor penetrates through the first interlayer insulating layer 162 ( 172 is electrically connected to the power line wiring 174. A second interlayer insulating layer 164 is interposed on the first interlayer insulating layer 162 including the power line wiring 174, and a lower electrode 142 / phase change resisting film () is disposed on the second interlayer insulating layer 164. A phase change resistance element 140 is formed that includes 144 / upper electrode 146. The phase change resistance element 140 is electrically connected to the source region 112 of the transistor through a contact 130 penetrating through the first and second interlayer insulating layers 162 and 164. Although not shown, a planarized interlayer insulating film is interposed on the phase change resistance element 140, and a bit line is disposed on the interlayer insulating film.

In the conventional phase change memory device described with reference to FIGS. 4A and 4B, the common drain region on the semiconductor substrate is electrically connected to the power supply line through the contact. In such a structure, sufficient process margin for contact formation on the common drain must be ensured, which inevitably increases the area occupied by the unit cell. Therefore, the conventional phase change memory device employs a cell structure that is not suitable for implementing a high density phase change memory device.

In order to achieve the above technical problem, an object of the present invention is to provide a phase change memory cell array and a semiconductor memory device including the same, which is advantageous for high integration and large capacity.

Another object of the present invention is to provide a phase change memory cell array and a semiconductor memory device including the same, which provide a current driving force sufficient to drive a highly integrated phase change memory device.

In addition, an object of the present invention is to provide a semiconductor memory device that can be driven at a power of several times or less than the conventional sensing method of the phase change memory device.

In order to achieve the above technical problem, a semiconductor memory device of the present invention includes a phase change memory unit cell including two or three access transistors sharing a source region and a gate voltage, and a phase change resistance element connected to the shared source region. .

In addition, the memory cell array of the present invention includes a first active region formed on a semiconductor substrate, a stem portion extending along the first active region, and defining a source region and a drain region in the first active region and the source region. A word line including a plurality of branch portions branched in a vertical direction to the stem portion so as to be divided into a plurality of regions, a plurality of bit lines crossing substantially in a direction perpendicular to the word line, and the separated source of the first active region And a plurality of phase change resistance elements formed on the region and electrically connected to the respective bit lines.

In addition, the memory cell array of the present invention includes a first active region formed on a semiconductor substrate, a pair of words extending in parallel along the first active region to define a source region and a common drain region in the first active region. Lines, a plurality of bit lines crossing substantially in a direction perpendicular to the pair of word lines, and a plurality of images formed on the source region of each of the first active regions and electrically connected to the respective bit lines. And a plurality of word line branches, each of the pair of word lines branching and extending in a direction of the source region to separate the source region.

The memory cell array of the present invention further includes a second active region extending outside the first active region from the common drain region between the pair of parallel word lines, wherein the second active region includes the common drain region. A contact for supplying a power supply voltage may be formed. Here, the second active region is a semiconductor region of the same conductivity type as the common drain region.

The branch portion of the word line of the memory cell array of the present invention is located between the plurality of bit lines in plan view.

Another object of the present invention is to provide a memory device including the above-described memory cell array and one sense amplifier commonly connected to the plurality of bit lines of the memory cell array.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is an equivalent circuit diagram of a phase change memory unit cell according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the phase change memory unit cell of the present invention is composed of three transistors T _A , T _SL, and T _SR and one phase change resistance element Rc. Each gate of the three transistors T _A , T _SL, and T _SR is electrically connected to one word line WL, and the three transistors share a source region. The shared source region is connected to the lower electrode of the phase change resistance element Rc. The upper electrode of the phase change resistance element Rc is electrically connected to the bit line BL. As described above, in the phase change memory unit cell of the present invention, three access transistors T _A , T _SL and T _SR are operated by a driving voltage applied to one word line WL. Supply the current. Therefore, even when the gate width of the transistor is narrowed according to the decrease of the ground rule, sufficient current required for driving the phase change resistance element can be supplied.

Although the case in which three access transistors of a unit cell are configured with reference to FIG. 5 has been described, the present invention can be easily applied even when two access transistors, that is, none of T _SL or T _SR , are present. Will be readily apparent to those skilled in the art.

FIG. 6 is a plan view illustrating a layout of the phase change memory unit cell of FIG. 5 implemented on the semiconductor substrate 200.

Referring to FIG. 6, the word line WL is disposed to cross the active region 280 on the semiconductor substrate in a transverse direction to serve as a gate of the transistor, and the active region 280 is connected to the source region 212 of the transistor. The drain region 214 is defined. On the source region 212, a phase change resistance element 240 including the lower electrode 242, the phase change resistance layer 244, and the upper electrode 246 is formed, and is formed through the bit line contact 230. It is electrically connected to the source region 214. The phase change resistance element 240 is electrically connected to a bit line BL that intersects the word line in a vertical direction. A power line is supplied to the drain region 214 through a power line contact 272.

As shown, in the present invention, the word line WL is a word line stem member that crosses the active region in a lateral direction and branches from the word line stem member so as to be perpendicular to the word line stem. It consists of a word line branch member surrounding 212.

When a voltage is applied to the word line WL during the operation of the memory cell, the image connected to the source region 212 through a channel formed by the word line stem and two word line branches in contact with the source region. Since the current is supplied to the variable resistance element 240, the channel width of the word line is about three times wider than that of the conventional word line. Accordingly, the driving current decrease due to the decrease in the channel width of the word line due to the high integration of the memory device can be prevented.

FIG. 7 is a diagram illustrating an equivalent circuit of a cell array including the phase change memory unit cells of FIG. 5.

Referring to FIG. 7, the array is composed of eight unit cells. In the present invention, the number of unit cells constituting the unit cell array may be changed as necessary, but is not absolute.

When the word line WL0 is selected in the array and any one of the bit lines BL0, BL1, ..., BL7 is selected, three transistors and one phase change resistor GST1, GST2, ..., GST3) operates, and the potential difference between the source and drain of the resistor elements across the cell connected to the unselected bit line and the transistors T _A , T _SL and T _SR associated with the cell becomes 0 V. It will be disconnected from the bit line.

FIG. 8 is a block diagram schematically illustrating a configuration of a memory cell region formed by the arrangement of the unit cell arrays UC illustrated in FIG. 7. As shown, the unit cells in the unit cell array are selected by selection of the word lines WL0, WL1, ..., WL7 and the bit lines BL0, BL1, ..., BLn.

FIG. 9 is an equivalent circuit diagram of a standard cell including two unit cells shown in FIG. 5. Here, the standard cells are classified for convenience by the repeat unit of the memory array of the present invention.

Referring to FIG. 9, the standard cell is composed of two unit cells. Gates of the transistors constituting each unit cell are connected to word lines WL0 and WL1, respectively, and the phase change resistance element GST shares the bit line BL.

FIG. 10 is a block diagram reconstructing the memory cell region of FIG. 8 from the perspective of the standard cell of FIG. 9. In the figure, the standard cell array DC is composed of two unit cell arrays UC.

FIG. 11 is a plan view illustrating a layout in which a standard cell array DC described with reference to FIG. 10 is disposed on a semiconductor substrate 200.

Referring to FIG. 11, a rectangular first active region 210 is formed in the semiconductor substrate 200. A pair of word lines WL0 and WL1 extend along the first active region 210 on the first active region 210. The word lines WL0 and WL1 define source regions 212 and drain regions 214 of a unit cell transistor constituting a standard cell array on the first active region 210. It acts as the gate of the transistor. That is, the first active region 210 between the pair of word lines corresponds to the common drain region 214 of two unit cells, and the outer two regions correspond to the source region 212 of each unit cell. .

A phase change resistance element 240 including a lower electrode 242 / a phase change resisting film 244 / an upper electrode 246 is formed on each source region 212 of the first active region. The phase change resistance element 240 is electrically connected to the source region 212 by a normal contact.

A plurality of parallel bit lines BL0, BL1, ..., BL7 are arranged in a direction substantially orthogonal to the word lines WL0, WL1. The bit lines BL0, BL1,..., BL7 are electrically connected to the upper electrode 246 of the phase change resistor 240.

As shown in FIG. 11, in the present invention, the word lines WL0 and WL1 branch from a stem member crossing the first active region and the stem and extend in a direction perpendicular to the stem. Branch parts WL01, WL02, ..., WL07 and WL11, WL12, ..., WL17; The branch portions WL01, WL02,..., WL07, and WL11, WL12,..., WL17 of the word line form source regions 212 of two adjacent cell transistors formed on the first active region 210. Compartment.

In the present invention, each source region 212 of two adjacent cell transistors having a word line branch between them serves as a source or a drain depending on whether the corresponding bit line is selected. It is referred to as a source region to distinguish it from the common drain region 214 between one or two word lines WL0 and WL1, and the description and claims of the specification of the present invention are described based on the use of such terms.

In the present invention, the source region 212 of two adjacent cell transistors is bounded by the branch of the word line, but a conduction channel is also formed between the two source regions 212 when the word line is turned on.

Accordingly, the unit cell of the phase change memory device of the present invention can provide a higher current carrying current than the unit cell of the conventional phase change memory device described with reference to FIG. 4. Specifically, the outermost cells of the cell array shown in FIG. 11 obtain about twice the channel width increase effect, and the inner cells may obtain about three times the channel width increase effect.

In addition, although the phase change memory cell array structure of the present invention shown in FIG. 11 further includes a word line branch portion, the increase in driving current is obtained, the memory cell density decreases as compared with the conventional cell array structure. I never do that. This is because the region where the branch portions WL01, WL02, ..., WL07 and WL11, WL12, ..., WL17 of the word line are formed is occupied by an element isolation structure that separates active regions in a conventional cell array structure. Because it is space. As described above, in the present invention, the entire cell array is formed on one active region, that is, the first active region 210, and does not adopt an element isolation structure to distinguish the unit cells of the cell array. Are separated by word line branches.

12 and 13 are cross-sectional views illustrating a cross section of the cell array structure illustrated in FIG. 11 in the B-B 'direction and the C-C' direction. The manufacturing method of the memory cell array shown here is not an essential part of the present invention, and can be easily carried out by those skilled in the art by methods widely used in the conventional DRAM manufacturing process. Omit the description.

12 and 13, an isolation layer 202 and a first active region 210 are formed on a semiconductor substrate 200. A transistor structure including source / drain regions 212 and 214 and gates WL0, WL1, WL01 and WL02 is formed on the first active region 210. The isolation layer 202 defines the first active region 210 described with reference to FIG. 11.

The source region 212 of the transistor 220 is electrically connected to the phase change resistance element 240 through the normal contact 230 and the stud 232. The phase change resistance device 240 includes a lower electrode 242, a phase change resistance film 244, and an upper electrode 246, and the upper electrode 246 is electrically connected to the bit line 250. . In the pattern process of the normal contact 230 and the phase change resistance element 240, interlayer insulating layers 262, 264, 266, and 268 are interposed. Since the number of interlayer insulating films to be interposed may vary depending on the manufacturing method or the structure of the component parts, the interlayer insulating film may not have any particular meaning in the drawings.

Referring back to FIG. 11, second active regions 270 are disposed on left and right sides of the first active region 210 of the semiconductor substrate 100. The second active region 270 extends outward from an intermediate point of the first active region 210. The second active region 270 is formed on the semiconductor substrate 200 in substantially the same plane as the first active region 210, and has the same conductivity type as the source region 212 and the common drain region 214. It is a semiconductor region having. For example, when the access transistor is an n-channel transistor, the second active region 270 is composed of an n-type semiconductor region. The second active region 270 electrically connects common drain regions 214 of the cell array. Of course, a low resistance film such as a silicide compound may be provided on a portion of the surface of the second active region to provide a conductive path having a lower resistance.

Unlike the conventional phase change memory cell array described with reference to FIG. 4A, the phase change memory cell array of the present invention has a contact providing electrical connection to the common drain region 214 of the first active region 210. It is not installed. As shown, a contact for providing an electrical connection to the common drain 214 is provided in the second active region 270 outside the common drain 214.

Such a memory cell array structure has the following advantages. First, there is no need for the common drain 214 to be provided with a contact for connection with a bit line or a common drain electrode. Therefore, the interval between the pair of word lines WL0 and WL1 that cross the first active region 210 can be designed to be narrower. This may eventually reduce the size of the first active region 210 and the size of the standard cell, and increase the density of memory cells.

Next, in the memory cell array of the present invention, a contact 272 for supplying a signal to the common drain 214 is provided outside the first active region 210. Therefore, as shown in the figure, a larger contact formation space can be secured by adjusting the spacing of word lines in the vicinity where the contact 272 is installed.

In the present exemplary embodiment, the second active region 270 is electrically connected to the common drain through the contact 272 to supply the power voltage V _AA to the common drain region 214.

FIG. 14 is an equivalent circuit diagram illustrating a unit cell array and a peripheral circuitry driving the unit cell array of the phase change memory device of the present invention.

As illustrated, the memory device of the present invention reads data input through eight bit lines of a unit cell array using one sense amplifier (S / A). Therefore, compared to the conventional method using one sense amplifier for each bit line, only 1/8 of the sensing current is required, thereby implementing a low power memory device.

Preferred embodiments of the present invention described above are merely illustrative of embodiments of the present invention, and can be modified and applied in various forms within the scope of the technical spirit of the present invention described above. In addition, the embodiments and drawings are used for the purpose of describing the contents of the present invention in detail, and are not intended to limit the technical scope of the present invention. Therefore, one of ordinary skill in the art to which the present invention pertains will be able to make various substitutions and modifications based on the above-described embodiments and the accompanying drawings without departing from the spirit of the present invention. The scope of the invention should be construed to include the claims and their equivalents as well as the claims that follow.

According to the present invention, by increasing the number of access transistors per memory cell, the effect of substantially increasing the channel width of the transistor can be obtained, and sufficient current necessary for driving the phase change element can be provided. The memory cell structure of the present invention can adequately cope with a trend of decreasing transistor channel width due to high integration.

In addition, according to the present invention, the size of the unit memory cell of the phase change memory cell can be reduced by drawing a contact formed in the common drain to the outside of the semiconductor active region. This meets the demand for high integration and large capacity of semiconductors.

In addition, according to the present invention, by forming a contact outside the semiconductor active region, sufficient process margin necessary for forming the contact can be secured. In addition, in the semiconductor manufacturing process, the possibility of poor contact of a contact caused by mask misalignment or the like becomes low.

In addition, according to the present invention, by using only one sense amplifier for one memory cell array, it is possible to significantly reduce power consumption during operation of the memory cell.

Claims (9)

Two or three transistors having a common gate voltage and having a common source region connected thereto; And And a phase change resistance element having one end connected to the commonly connected source region. The method of claim 1, And a bit line electrically connected to the other end of the phase change resistance element. The method of claim 1, Phase change semiconductor memory device, characterized in that the power supply voltage is commonly applied to the drain region of each transistor. A first active region formed on the semiconductor substrate; A stem portion extending along the first active region to define a source region and a drain region in the first active region, and a plurality of branch portions branched in a vertical direction to divide the source region into a plurality of regions; A word line; A plurality of bit lines crossing in a direction substantially perpendicular to the word line; And And a plurality of phase change resistance elements formed on the separated source regions of the first active region and electrically connected to the respective bit lines. A first active region formed on the semiconductor substrate; A pair of word lines extending in parallel along the first active region to define a source region and a common drain region in the first active region; A plurality of bit lines crossing the pair of word lines in a substantially perpendicular direction; And A plurality of phase change resistance elements formed on the source region of each of the first active regions and electrically connected to the respective bit lines; And each of the pair of word lines includes a plurality of word line branches which branch and extend in the direction of the source region to separate the source region. The method of claim 5, A second active region extending outside the first active region from the common drain region between the pair of parallel word lines, And a contact for supplying a power voltage to the common drain region in the second active region. The method of claim 6, And the second active region is a semiconductor region of the same conductivity type as the common drain region. The method of claim 5, And the branch of the word line is planarly positioned between the plurality of bit lines. The memory cell array of claim 5; And And a sense amplifier commonly connected to the plurality of bit lines of the memory cell array.

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