KR100679097B1 - Circuit for Electro Luminescence Cell And Electro Luminescence Pannel Using The Same - Google Patents

Abstract

An object of the present invention relates to an EL cell driving circuit and an EL panel using the same which prevent leakage of a pixel signal so that an image corresponding to a video signal or a video signal is displayed without deterioration and distortion.

An EL cell driving circuit according to an embodiment of the present invention comprises: an EL cell provided at a cross section of a gate line and a data line in a state of being connected to a base voltage line; First and second switch elements for forming a current mirror between the EL cell, the supply voltage line, and the first node with a second node therebetween; A voltage charging element connected between the supply voltage line and the second node to charge a pixel signal from the data line and apply the charged pixel signal to the current mirror; A third switch element for selectively applying a pixel signal on the data line to the current mirror via the first node in response to a signal on the gate line; A fourth switch element for selectively connecting said first node to said voltage charging element in response to a signal on said gate line; And signal delay means formed between the gate line and the third switch element and delaying a signal to be supplied from the gate line to the third switch element.

Description

Electroluminescence cell driving circuit and electroluminescence panel using the same {Circuit for Electro Luminescence Cell And Electro Luminescence Pannel Using The Same}

1 is a circuit diagram for driving a conventional electro luminescence cell.

2 is a driving circuit diagram of an electro luminescence cell according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

C1: Capacitor ELC: EL Cell

MP1 to MP4: first to fourth PMOS TFTs

R1: Resistor 2: Current Mirror

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro luminescence (EL) panel, in particular an EL cell driving circuit for driving each of the EL cells arranged in a matrix form on the EL panel and an EL panel using the same. It is about.

A conventional EL panel displays an image corresponding to a video (or video) signal by converting an electrical signal into energy of light. This EL panel has EL cells arranged at each of the intersections of the gate lines and the data lines. Each of the EL cells generates light corresponding to the magnitude of the pixel signal in response to the pixel signal from the data line. In order to stably apply the pixel signal to each of the EL cells, the EL panel has cell driving circuits which are sequentially scanned in units of lines. Each of these EL cell driving circuits samples the pixel signal on the data line in response to a control signal on the gate line and then holds it for a frame period so that the pixel signal is stably applied to the EL cell.

As shown in FIG. 1, a typical EL cell driving circuit which performs the sampling and holding operation of such a pixel signal includes an EL cell ELC, a first node N1, and a supply connected to a ground voltage line GNDL. First and second PMOS thin film transistors (hereinafter referred to as "TFTs") MP1 and MP2 connected to form a current mirror between the voltage lines VDDL, and these first and second PMOS TFTs ( The capacitor C1 is connected between the second node N2 to which the gate electrodes of MP1 and MP2 are commonly connected and the supply voltage line VDDL.

When the pixel signal is applied from the data line DL, the capacitor C1 charges a difference voltage corresponding to a difference between the voltage of the pixel signal and the supply voltage VDD on the supply voltage line VDDL to reduce the difference voltage. Commonly supplied to the gate electrodes of the first and second PMOS TFTs MP1 and MP2. The first PMOS TFT MP1 is turned on by the difference voltage charged in the capacitor C1 so that the supply voltage VDD on the supply voltage line VDDL is supplied to the EL cell ELC. At this time, the first PMOS TFT MP1 varies its channel width according to the voltage level of the pixel signal so that the amount of current supplied from the supply voltage line VDDL to the EL cell ELC is adjusted. Then, the EL cell ELC generates a light amount corresponding to the amount of current applied from the supply voltage line VDDL via the first PMOS TFT MP1. On the other hand, when the pixel signal is applied from the data line DL, the second PMOS TFT MP2 adjusts the amount of current flowing from the supply voltage line VDDL to the data line DL via the first PMOS TFT ( The amount of current to flow toward the EL cell ELC through MP1) is determined.

In addition, the conventional EL cell driving circuit further includes third and fourth PMOS TFTs MP3 and MP4 which commonly respond to gate signals on the gate lines GL.

The third PMOS TFT MP3 is turned on in a period in which a low logic gate signal is supplied from the gate line GL, so that the source electrode of the third PMOS TFT MP2 connected to the first node N1 is a data line. To the DL. In other words, the third PMOS TFT MP3 transmits the pixel signal on the data line DL toward the first node N1 in response to the low logic gate signal. The fourth PMOS TFT MP4 is also turned on during the period in which the low logic gate signal is supplied from the gate line GL toward the gate electrode thereof, and thus the gate electrodes of the first and second PMOS TFTs MP1 and MP2 are connected to each other. The second node N2 to which one terminal of the capacitor C1 is connected is connected to the data line DL via the first node N1. In other words, the third and fourth PMOS TFTs MP3 and MP4 are turned on during the period in which the gate signal on the gate line GL maintains low logic so that the pixel signal is turned on to the second node N2 and the supply voltage line. The capacitor C1 connected between the VDDLs is charged.

In this conventional EL cell driving circuit, when the gate signal on the gate line GL is changed from low logic to high logic, both the third and fourth PMOS TFTs MP3 and MP4 must be turned off at the same time so that the capacitor ( The voltage charged in C1) does not leak. However, when the third PMOS TFT MP3 is turned off before the fourth PMOS TFT MP4 when the gate signal on the gate line GL is changed from low logic to high logic, one terminal of the capacitor C1 is turned off. Is connected to the supply voltage line VDDL via the fourth and second PMOS TFTs MP4 and MP2. As a result, the voltage charged in the capacitor C1 follows the supply voltage VDD. In other words, the voltage charged in the capacitor C1 leaks. As a result, the amount of light generated in the EL cell ELC is not only different from the voltage level of the pixel signal, but also the image displayed by the EL panel is deteriorated and / or distorted.

It is therefore an object of the present invention to provide an EL cell driver circuit suitable for preventing leakage of pixel signals.

Another object of the present invention is to provide an EL panel capable of displaying a video signal or an image corresponding to a video signal without deterioration and distortion.

In order to achieve the above object, an EL cell driving circuit according to an embodiment of the present invention includes an EL cell provided in a state in which a base voltage line is connected to an intersection of a gate line and a data line; First and second switch elements for forming a current mirror between the EL cell, the supply voltage line, and the first node with a second node therebetween; A voltage charging element connected between the supply voltage line and the second node to charge a pixel signal from the data line and apply the charged pixel signal to the current mirror; A third switch element for selectively applying a pixel signal on the data line to the current mirror via the first node in response to a signal on the gate line; A fourth switch element for selectively connecting said first node to said voltage charging element in response to a signal on said gate line; And signal delay means formed between the gate line and the third switch element and delaying a signal to be supplied from the gate line to the third switch element.
The signal delay means has a resistor connected between the gate line and the third switch element.
The third switch element is turned off later than the fourth switch element by the signal delay means.
The third and fourth switch elements are turned on while the signal on the gate line remains low to supply the pixel signal to the voltage charging element.

An EL panel according to an embodiment of the present invention includes an EL cell provided at a cross section of a gate line and a data line while being connected to a base voltage line; First and second switch elements for forming a current mirror between the EL cell, the supply voltage line, and the first node with a second node therebetween; A voltage charging element connected between the supply voltage line and the second node to charge a pixel signal from the data line and apply the charged pixel signal to the current mirror; A third switch element for selectively applying a pixel signal on the data line to the current mirror via the first node in response to a signal on the gate line; A fourth switch element for selectively connecting said first node to said voltage charging element in response to a signal on said gate line; And an EL cell driving circuit formed between the gate line and the third switch element, and having signal delay means for delaying a signal to be supplied from the gate line to the third switch element.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2 shows an EL cell driving circuit according to an embodiment of the present invention. The EL cell driving circuit shown in FIG. 2 is connected to form a current mirror 2 between the EL cell ELC, the first node N1 and the supply voltage line VDDL connected to the base voltage line GNDL. Between the first and second PMOS TFTs MP1 and MP2 and between the second node N2 and the supply voltage line VDDL to which the gate electrodes of these first and second PMOS TFTs MP1 and MP2 are commonly connected. The capacitor C1 connected is provided.

When the pixel signal is applied from the data line DL, the capacitor C1 charges a difference voltage corresponding to a difference between the voltage of the pixel signal and the supply voltage VDD on the supply voltage line VDDL to reduce the difference voltage. Commonly supplied to the gate electrodes of the first and second PMOS TFTs MP1 and MP2. The first PMOS TFT MP1 is turned on by the difference voltage charged in the capacitor C1 so that the supply voltage VDD on the supply voltage line VDDL is supplied to the EL cell ELC. At this time, the first PMOS TFT MP1 varies its channel width according to the voltage level of the pixel signal so that the amount of current supplied from the supply voltage line VDDL to the EL cell ELC is adjusted. Then, the EL cell ELC generates a light amount corresponding to the amount of current applied from the supply voltage line VDDL via the first PMOS TFT MP1. On the other hand, when the pixel signal is applied from the data line DL, the second PMOS TFT MP2 adjusts the amount of current flowing from the supply voltage line VDDL to the data line DL via the first PMOS TFT ( The amount of current to flow toward the EL cell ELC through MP1) is determined.

Further, the EL cell driving circuit according to the embodiment of the present invention further includes third and fourth PMOS TFTs MP3 and MP4 which commonly respond to gate signals on the gate line GL. The third PMOS TFT MP3 is turned on in a period in which a low logic gate signal is supplied from the gate line GL, so that the source electrode of the third PMOS TFT MP2 connected to the first node N1 is a data line. To the DL. In other words, the third PMOS TFT MP3 transmits the pixel signal on the data line DL toward the first node N1 in response to the low logic gate signal. The fourth PMOS TFT MP4 is also turned on during the period in which the low logic gate signal is supplied from the gate line GL toward the gate electrode thereof, and thus the gate electrodes of the first and second PMOS TFTs MP1 and MP2 are connected to each other. The second node N2 to which one terminal of the capacitor C1 is connected is connected to the data line DL via the first node N1. In other words, the third and fourth PMOS TFTs MP3 and MP4 are turned on in the period in which the gate signal on the gate line GL maintains low logic so that the pixel signal is turned on to the second node N2 and the supply voltage line. The capacitor C1 connected between the VDDLs is charged.

Furthermore, the EL cell driving circuit according to the embodiment of the present invention further includes a resistor R1 connected between the gate line GL and the gate electrode of the third PMOS TFT MP3. This resistor R1 causes the gate signal to be supplied from the gate line GL to the gate electrode of the third PMOS TFT MP3 to be delayed. Accordingly, the third PMOS TFT MP3 is turned off later than the fourth PMOS TFT MP4 when the gate signal is changed from low logic to high logic. Therefore, the voltage charged in the capacitor C1 does not leak when the gate signal falls. As a result, the EL cell ELC can accurately generate an amount of light corresponding to the voltage level of the pixel signal, and furthermore, the EL panel can display an image corresponding to the video signal (or image signal) without deterioration or distortion. do.

In order to delay the gate signal, the present invention may further include a second capacitor connected between the gate electrode of the third PMOS TFT MP3 and the base voltage line GNDL as well as the resistor R1. In other words, the signal delay means for delaying the gate signal applied from the gate line GL toward the gate electrode of the third PMOS TFT MP3 is replaced by not only the resistor R1 but also other impedance elements or other impedance elements. It may be further provided.

As described above, the EL cell driving circuit according to the present invention charges the charging capacitor by causing the TFT which selectively connects the current mirror to the data line to be turned off later than another TFT which selectively connects itself to the charging capacitor. It is possible to prevent leakage of a given voltage. Accordingly, the EL cell driving circuit according to the present invention causes the EL cell to accurately generate light in an amount corresponding to the voltage level of the pixel signal. As a result, the EL cell driving circuit according to the present invention enables the EL panel to accurately display an image corresponding to the video signal or the image signal without distortion and / or deterioration.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

An EL cell provided in a state of being connected to a base voltage line at an intersection of the gate line and the data line; First and second switch elements for forming a current mirror between the EL cell, the supply voltage line, and the first node with a second node therebetween; A voltage charging element connected between the supply voltage line and the second node to charge a pixel signal from the data line and apply the charged pixel signal to the current mirror; A third switch element for selectively applying a pixel signal on the data line to the current mirror via the first node in response to a signal on the gate line; A fourth switch element for selectively connecting said first node to said voltage charging element in response to a signal on said gate line; And And a signal delay means formed between said gate line and said third switch element, for delaying a signal to be supplied from said gate line to said third switch element. According to claim 1, And the signal delay means has a resistor connected between the gate line and the third switch element. According to claim 1, And the third switch element is turned off later than the fourth switch element by the signal delay means. According to claim 1, The third and fourth switch elements, And the pixel signal is supplied to the voltage charging element while being turned on while the signal on the gate line remains low. An EL cell provided in a state of being connected to a base voltage line at an intersection of the gate line and the data line; First and second switch elements for forming a current mirror between the EL cell, the supply voltage line, and the first node with a second node therebetween; A voltage charging element connected between the supply voltage line and the second node to charge a pixel signal from the data line and apply the charged pixel signal to the current mirror; A third switch element for selectively applying a pixel signal on the data line to the current mirror via the first node in response to a signal on the gate line; A fourth switch element for selectively connecting said first node to said voltage charging element in response to a signal on said gate line; And an EL cell driving circuit formed between the gate line and the third switch element, and having signal delay means for delaying a signal to be supplied from the gate line to the third switch element. .

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