KR100676614B1 - A flash memory device having the improved structure for elevating operation performance - Google Patents

Abstract

According to the present invention, memory cell blocks and page buffers are arranged such that the loading capacitance and the resistance component of the bit lines are reduced, The leakage current due to the lines can be reduced, the operating speed of the flash memory device can be increased, and the power consumption can be reduced.

Memory cell block, selection control circuit, X-decoder

Description

[0001] The present invention relates to a flash memory device having an improved structure for improving operational performance,

1 is a block diagram showing a part of a conventional flash memory device.

2 is a block diagram of a flash memory device in accordance with an embodiment of the present invention.

Description of the Related Art

100: flash memory device 101: input buffer

102: control logic circuit 103: high voltage generator

104: X-decoder 105, 106: selection control circuit

107: first block selector 108: second block selector

109 to 112: page buffer 113: Y-decoder

114: Data I / O buffer

The present invention relates to a semiconductor memory device, and more particularly, to a flash memory device.

Generally, a flash memory device includes a page buffer for programming or reading large amounts of data for a short time. Therefore, the program operation or the read operation of the flash memory device is executed page by page by the page buffer. FIG. 1 is a block diagram showing a portion of a conventional flash memory device, which includes an X-decoder 10, page buffers 11 to 14, and memory cell blocks BF1 to BFK, BS1 to BSK ) Are shown. The memory cell blocks BF1 to BFK share bit lines BLe1, BLo1, BLe2 and BLo2 and the memory cell blocks BS1 to BSK share bit lines BLe3, BLo3, BLe4 and BLo4. . The memory cell blocks BF1 to BFK are disposed on one side of the X-decoder 10 and the memory cell blocks BS1 to BSK are disposed on the other side of the X-decoder 10 . The X-decoder 10 selects one of the memory cell blocks BF1 to BFK and one of the memory cell blocks BS1 to BSK. The page buffer 11 is connected to the bit lines BLe1 and BLo1 and the page buffer 12 is connected to the bit lines BLe2 and BLo2. The page buffer 13 is connected to the bit lines BLe3 and BLo3 and the page buffer 14 is connected to the bit lines BLe4 and BLo4. As described above, in the conventional flash memory device having a structure in which the memory cell blocks BF1 to BFK and BS1 to BSK are continuously arranged on both sides of the X-decoder 10, BLe4, BLo1 to BLo4) are increased. Because the bit lines BLe1, BLo1, BLe2 and BLo2 are shared by all the memory cell blocks BF1 to BFK, the lengths of the bit lines BLe1, BLo1, BLe2 and BLo2 are And must be formed corresponding to the entire length of the memory cell blocks BF1 to BFK. Similarly, since the bit lines BLe3, BLo3, BLe4 and BLo4 are also shared by all the memory cell blocks BS1 to BSK, the lengths of the bit lines BLe3, BLo3, BLe4 and BLo4 are Is formed to correspond to the entire length of the memory cell blocks BS1 to BSK. When the loading capacitance and resistance of the bit lines BLe1 to BLe4 and BLo1 to BLo4 are increased, there is a problem that the leakage current due to the bit lines BLe1 to BLe4 and BLo1 to BLo4 increases. Further, there is a problem that the operating speed is reduced and the consumed power is increased during the program operation or the read operation of the flash memory device.

SUMMARY OF THE INVENTION Accordingly, it is an aspect of the present invention to provide a memory device that reduces leakage current due to bit lines, increases operating speed, and reduces power consumption by disposing memory cell blocks and page buffers so that the loading capacitance and resistance component of the bit lines are reduced. And to provide a flash memory device having an improved structure capable of reducing power consumption.

According to an aspect of the present invention, there is provided a flash memory device including first memory cell blocks, second memory cell blocks, a page buffer, and a selection control circuit. The first memory cell blocks each include first memory cells sharing first bit lines. The second memory cell blocks each include second memory cells sharing second bit lines. The page buffer stores read data or program data of the first memory cells included in one of the first memory cell blocks, or the second memory cells included in one of the second memory cell blocks. The selection control circuit, in response to the select signal, connects the first bit lines to the page buffer, or connects the second bit lines to the page buffer.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limiting the scope of the invention to those skilled in the art It is provided to let you know completely.

2 is a block diagram of a flash memory device in accordance with an embodiment of the present invention. 2, the flash memory device 100 includes an input buffer 101, a control logic circuit 102, a high voltage generator 103, an X-decoder 104, first to fourth memory cell blocks MF1 (J is an integer), selection control circuits 105 and 106, a first block selection unit 107, a second block selection unit 108, a page selection unit 108, Buffers 109 to 112, a Y-decoder 113, and a data input / output buffer 114. The input buffer 101 receives the command signal CMD or the address signal ADD and outputs it to the control logic circuit 102. The control logic circuit 102 receives the command signal CMD or the address signal ADD in response to external control signals WEB, REB, ALE, and CLE. The control logic circuit 102 generates one of a program command (PGM), a read command (READ), and an erase command (ERS) in response to the command signal (CMD). The control logic circuit 102 generates a row address signal RADD and a column address signal CADD based on the address signal ADD. The high voltage generator 103 generates one of the bias voltages HV1 to HV3 in response to one of the program command PGM, the read command READ and the erase command ERS. More specifically, in response to the program command (PGM), the high voltage generator 103 generates the bias voltage HV1. The high voltage generator 103 generates the bias voltage HV2 in response to the read command READ and generates the bias voltage HV3 in response to the erase command ERS.

The X-decoder 104 decodes the row address signal RADD and outputs a row decoding signal DRED and selection signals SEL1 and SEL2 as a decoding result.

Each of the first memory cell blocks MF1 to MFJ includes memory cells (not shown) sharing memory cells (not shown) sharing bit lines BLe1 and BLo1 and bit lines BLe3 and BLo3 . Each of the second memory cell blocks MS1 to MSJ includes memory cells (not shown) sharing memory cells (not shown) sharing bit lines BLe2 and BLo2 and bit lines BLe4 and BLo4 . The third memory cell blocks MT1 to MTJ may include memory cells (not shown) that share bit lines BLe5 and BLo5 and memory cells (not shown) that share bit lines BLe7 and BLo7, . The fourth memory cell blocks MY1 to MYJ include memory cells (not shown) that share bit lines BLe6 and BLo6 and memory cells (not shown) that share bit lines BLe8 and BLo8 do.

The selection control circuit 105 includes an inverter 121 and selection circuits 122 to 125. The inverter 121 inverts the selection signal SEL1 and outputs the inverted selection signal SEL1B. The selection circuit 122 includes NMOS transistors N1 and N2 and the selection circuit 123 includes NMOS transistors N3 and N4. The NMOS transistors N1 to N4 are simultaneously turned on or off in response to the selection signal SEL1. And connects the bit lines BLe1 and BLo1 to the page buffer 109 when the NMOS transistors N1 and N2 are turned on. And connects the bit lines BLe3 and BLo3 to the page buffer 110 when the NMOS transistors N3 and N4 are turned on.

In addition, the selection circuit 124 includes NMOS transistors N5 and N6, and the selection circuit 125 includes NMOS transistors N7 and N8. The NMOS transistors N5 to N8 turn on or off at the same time in response to the inverted selection signal SEL1B. The NMOS transistors N5 and N6 connect the bit lines BLe2 and BLo2 to the page buffer 109 when the NMOS transistors N5 and N6 are turned on. And connects the bit lines BLe4 and BLo4 to the page buffer 110 when the NMOS transistors N7 and N8 are turned on. Therefore, when the NMOS transistors N1 to N4 are turned on, the NMOS transistors N5 to N8 are turned off. The selection control circuit 105 connects the bit lines BLe1, BLo1, BLe3 and BLo3 to the page buffers 109 and 110 or connects the bit lines BLe2, BLo2, BLe4, BLo4 to the page buffers 109 and 110, respectively. As a result, it is included in one of the first memory cell blocks (MF1 to MFJ) or in the second memory cell blocks (MS1 to MSJ) during a read or program operation, and the bit lines (BLe1, The read data or program data of the memory cells (preferably two pages) connected to the page buffers 109 and 110 are stored in the page buffers 109 and 110, respectively. Alternatively, the selection circuits 122 to 125 may be implemented as PMOS transistors, respectively.

The selection control circuit 106 includes an inverter 131 and selection circuits 132-135. The inverter 131 inverts the selection signal SEL2 and outputs the inverted selection signal SEL2B. The selection circuit 132 includes NMOS transistors N9 and N10 and the selection circuit 133 includes NMOS transistors N11 and N12. The NMOS transistors N9 to N12 are simultaneously turned on or off in response to the selection signal SEL2. And connects the bit lines BLe5 and BLo5 to the page buffer 111 when the NMOS transistors N9 and N10 are turned on. And connects the bit lines BLe7 and BLo7 to the page buffer 112 when the NMOS transistors N11 and N12 are turned on.

The selection circuit 134 includes NMOS transistors N13 and N14 and the selection circuit 135 includes NMOS transistors N15 and N16. The NMOS transistors N13 to N16 are simultaneously turned on or off in response to the inverted selection signal SEL2B. The NMOS transistors N13 and N14 connect the bit lines BLe6 and BLo6 to the page buffer 111 when the NMOS transistors N13 and N14 are turned on. And connects the bit lines BLe8 and BLo8 to the page buffer 112 when the NMOS transistors N15 and N16 are turned on. Therefore, when the NMOS transistors N9 to N12 are turned on, the NMOS transistors N13 to N16 are turned off. The selection control circuit 106 connects the bit lines BLe5, BLo5, BLe6 and BLo6 to the page buffers 111 and 112 or the bit lines BLe7, BLo7, BLe8, BLo8 to the page buffers 111 and 112, respectively. As a result, at the time of the read or program operation, one of the third memory cell blocks MT1 to MTJ or the second memory cell blocks MS1 to MSJ is included, and the bit lines BLe5 The read data or the program data of the memory cells (preferably two pages) connected to the page buffers 111 and 112 is stored (one page at a time) in the page buffers 111 and 112 connected to the memory cells BL05, BLo7, and BLo7. Alternatively, the selection circuits 132-135 may be implemented as PMOS transistors, respectively.

The first block selector 107 selects one of the first memory cell blocks MF1 to MFJ and the third memory cell block MT1 to MTJ in response to the row decode signal DRED. And supplies the bias voltages (one of HV1 to HV3) to the selected memory cell blocks (one of MT1 to MTJ, MT1 to MTJ). The second block selection unit 108 selects one of the second memory cell blocks MS1 to MSJ and the fourth memory cell block MY1 to MYJ in response to the row decode signal DRED. And supplies the bias voltages (one of HV1 to HV3) to the selected memory cell blocks (one of MS1 to MSJ, one of MY1 to MYJ). In the reading operation, the Y-decoder 113 decodes the column address signal CADD and outputs the data DAT1 to DAT4 received from the page buffers 109 to 112 And outputs one through the data input / output buffer 114 as output data DO. In the program operation, the Y-decoder 113 decodes the column address signal CADD and outputs the input data DI received through the data input / output buffer 114 to the page buffer 114, Respectively.

As described above, in the flash memory device according to the present invention, since the page buffers are disposed between the memory cell blocks, the length of the bit lines actually connected to the page buffers during the read or program operation Can be significantly reduced compared to the length. Thus, the leakage current due to the bit lines can be reduced, the operation speed of the flash memory device can be increased, and the power consumption can be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

As described above, according to the present invention, by arranging the memory cell blocks and the page buffers so that the loading capacitance and the resistance component of the bit lines are reduced, the leakage current due to the bit lines can be reduced, And the power consumption can be reduced.

Claims (8)

In a flash memory device, A first memory cell block comprising memory cell blocks including a plurality of bit lines connected to each of a plurality of memory strings; A second memory cell block including memory cell blocks including a plurality of bit lines connected to each of the plurality of memory strings; A page buffer connected to a first bit line and a second bit line respectively included in the first memory cell block or the second memory cell block and storing read data or program data of a memory cell connected to the bit line; And And a select control circuit responsive to the select signal for connecting the first bit lines to the page buffer or connecting the second bit lines to the page buffer. The method according to claim 1, Wherein the first memory cell blocks further include third memory cells each sharing third bit lines and the second memory cell blocks further each include fourth memory cells sharing fourth bit lines, A first additional page for storing read data or program data of the third memory cells included in one of the first memory cell blocks or the fourth memory cells included in one of the second memory cell blocks, Further comprising a buffer, Wherein the selection control circuit is responsive to the selection signal for connecting the third bit lines to the first additional page buffer or for connecting the fourth bit lines to the first additional page buffer, Device. The semiconductor memory device according to claim 2, An inverter for inverting the selection signal and outputting an inverted selection signal; A first selection circuit responsive to the selection signal for coupling the first bit lines to the page buffer; A second selection circuit responsive to the selection signal for coupling the third bit lines to the first additional page buffer; A third selection circuit responsive to the inverted selection signal for coupling the second bit lines to the page buffer; And And a fourth selection circuit responsive to the inverted selection signal for coupling the fourth bit lines to the first additional page buffer. 3. The method of claim 2, Third memory cell blocks each including fifth memory cells sharing fifth bit lines; Fourth memory cell blocks each including sixth memory cells sharing sixth bit lines; A second additional page for storing read data or program data of the sixth memory cells included in one of the third memory cell blocks or one of the fifth memory cells included in one of the fourth memory cell blocks, buffer; And Further comprising a further select control circuit responsive to a further select signal for connecting said fifth bit lines to said second additional page buffer or for connecting said sixth bit lines to said second additional page buffer Lt; / RTI > 5. The method of claim 4, Wherein the third memory cell blocks further comprise seventh memory cells each sharing seventh bit lines and the fourth memory cell blocks further each eighth memory cells sharing eighth bit lines, A third additional page for storing read data or program data of the eighth memory cells included in one of the seventh memory cells or the fourth memory cell blocks included in one of the third memory cell blocks, Further comprising a buffer, Wherein the further select control circuit is further operable in response to the further select signal to further connect the seventh bit lines to the third additional page buffer or to further connect the eighth bit lines to the third additional page buffer A connecting flash memory device. 6. The apparatus of claim 5, wherein the further selection control circuit comprises: An inverter for inverting the additional selection signal and outputting an inverted additional selection signal; A first selection circuit responsive to the further selection signal for coupling the fifth bit lines to the second additional page buffer; A second selection circuit responsive to the further selection signal for coupling the seventh bit lines to the third additional page buffer; A third selection circuit responsive to the inverted further select signal for connecting the sixth bit lines to the second additional page buffer; And And a fourth selection circuit responsive to the inverted further select signal for connecting the eighth bit lines to the third additional page buffer. 6. The method of claim 5, A high voltage generator for generating a bias voltage in response to one of a program command, a read command, and an erase command; And Decoder for decoding a row address signal and outputting a row decode signal, the select signal, and the further select signal as a result of the decoding. 8. The method of claim 7, A first block selection circuit for selecting one of the first memory cell blocks and one of the third memory cell blocks in response to the row decode signal and supplying the bias voltage to the selected memory cell blocks, part; And A second block selection circuit for selecting one of the second memory cell blocks and one of the fourth memory cell blocks in response to the row decode signal and supplying the bias voltage to the selected memory cell blocks, Flash memory device.

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