KR101098425B1 - Circuit of selecting block and non volatile memory device having the same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device, wherein a plurality of block selection circuits for selecting each memory block of a nonvolatile memory device including a plurality of memory blocks, each block selection circuit according to an address control signal. A first control signal generator configured to generate a first control signal for selecting a corresponding memory block; A block switching signal generator for outputting a block switching signal for providing to the selected memory block using the precharge control signal and the first control signal when the corresponding memory block is selected according to the address control signal; A control circuit for connecting a common source line of the unselected memory block to a ground node when the corresponding memory block is unselected according to the address control signal; And pass transistors for providing operating voltages to the selected memory block according to the block switching signal.

Block switch, common source line

Description

Circuit of selecting block and non volatile memory device having the same

The present invention relates to a nonvolatile memory device, and more particularly, to a block selection circuit capable of controlling a common source line voltage of an unselected memory block and a nonvolatile memory device having the same.

The memory cell array of the nonvolatile memory device includes a plurality of memory blocks including a plurality of memory cells. When the nonvolatile memory device is operated, the X decoder of the nonvolatile memory device may operate in units of memory blocks, and select a memory block and perform a switching operation for applying a voltage to the selected memory block. The X decoder may further include memory block switches for enabling each memory block and an operation voltage provided by a voltage providing means by an enable signal of the memory block switch. And a switching unit for transmitting to a drain select line (DSL) and a source select line (SSL).

When the nonvolatile memory device performs a program, the memory block is selected using the input address information. At this time, the block switch connected to the corresponding memory block by the address information outputs the enable signal. The switching unit switches according to the enable signal so that the operating voltage is transferred to the word lines, the drain select line DSL, and the source select line SSL of the memory block. This operation is similarly performed in the data read operation as well as the program operation.

In the program operation, the power source voltage VCC is equally supplied to the common source lines SL of the memory blocks. Therefore, not only the memory block selected for the program operation but also the common source lines Sources of the unselected memory blocks are supplied with the power supply voltage VCC.

After the program is finished, the powered word lines, bit lines, and common source lines are connected to the ground node (GND) to have a voltage of 0V. At this time, as all word lines, bit lines, and common source lines GND are changed to 0 V, bouncing occurs due to the influence of the substrate of the memory cell array.

When bouncing occurs on the substrate, some of the transistors of the memory cell array may be affected, resulting in a problem of weakening characteristics.

Accordingly, an aspect of the present invention is to provide a block selection circuit and a nonvolatile memory device including the same in a common source line of a memory block that is not selected for a program so as not to input a power supply voltage during a program operation. .

Block selection circuit according to a feature of the invention,

In a plurality of block selection circuits for selecting respective memory blocks of a nonvolatile memory device including a plurality of memory blocks, each block selection circuit includes a first control for selecting a corresponding memory block in accordance with an address control signal. A first control signal generator for generating a signal; A block switching signal generator for outputting a block switching signal for providing to the selected memory block using the precharge control signal and the first control signal when the corresponding memory block is selected according to the address control signal; A control circuit for connecting a common source line of the unselected memory block to a ground node when the corresponding memory block is unselected according to the address control signal; And pass transistors for providing operating voltages to the selected memory block according to the block switching signal.

The control circuit includes a switching element connected between a common source line of the memory block and a ground node, and a signal generation circuit outputting a control signal for controlling the operation of the switching element according to the first control signal.

When the common source line is connected to the ground node by the control signal, the block switching signal is discharged to the ground voltage.

Nonvolatile memory device according to a feature of the present invention,

A memory cell array including a plurality of memory blocks; A plurality of block selection circuits respectively connected to the plurality of memory blocks and configured to provide an operating voltage to a memory block selected according to an address control signal, or to connect a common source line of an unselected memory block to a ground node; Decoder; A voltage providing unit generating the operating voltage for providing the selected memory block; And a control unit for controlling the voltage providing unit to output the address control signal for controlling the operations of the plurality of block selection circuits by an input address and to generate the operating voltage according to an operation mode.

Each of the block selection circuits includes: a first control signal generator for generating a first control signal for selecting a corresponding memory block according to an address control signal; A first control signal generator configured to generate a first control signal for selecting a corresponding memory block according to the address control signal; A block switching signal generator for outputting a block switching signal for providing to the selected memory block using the precharge control signal and the first control signal when the corresponding memory block is selected according to the address control signal; A control circuit for connecting a common source line of the unselected memory block to a ground node when the corresponding memory block is unselected according to the address control signal; And pass transistors for providing operating voltages to the selected memory block according to the block switching signal.

The control circuit includes a switching element connected between a common source line of the memory block and a ground node, and a signal generation circuit outputting a control signal for controlling the operation of the switching element according to the first control signal.

The voltage providing unit is controlled to provide a power supply voltage to the global source line of the selected memory block during the program.

As described above, the block selection circuit and the nonvolatile memory device having the same according to the present invention can control the common source line voltage of the memory blocks, so that the common source line of the memory block that is not selected during the program operation is included. By not supplying the power supply voltage, the influence of the substrate Well due to the voltage discharge operation after the end of the program can be reduced.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a nonvolatile memory device 100 according to an exemplary embodiment may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, and a voltage providing unit. 150 and the controller 160.

The memory cell array 110 includes a plurality of memory blocks BK. Each memory block has memory cells for data storage connected to word lines and bit lines.

The page buffer unit 120 is connected to a bit line of the memory cell array 110 and includes page buffer circuits for providing data input for a program or reading and storing the programmed data.

The Y decoder 130 provides a data input / output path of the page buffer circuits of the page buffer unit 120, and the X decoder 140 selects a memory block BK of the memory cell array 110 according to an input address. The word line of the selected memory block BK may be connected to provide an operating voltage provided by the voltage provider 150.

The voltage providing unit 150 generates an operating voltage required to perform a program operation or a read operation, and the controller 160 outputs a control signal for controlling the operation of the nonvolatile memory device 100.

The X decoder 140 includes a block selection circuit connected to each memory block, and the block selection circuit may be divided into a memory block switch and a switching unit.

The memory block switch enables the memory block selected by the control signal of the controller 160. The switching unit generates an operating voltage generated by the voltage providing unit 150 according to the enable signal of the memory block switch, and includes a word line, a drain select line (DSL), and a source select line (Source) of the selected memory block. Connect to Select Line (SSL) and Common Source Line (SL). The memory block switch and the switching unit are configured for each memory block, and a detailed circuit configuration is as follows.

FIG. 1B is a partial circuit diagram of the X decoder of FIG. 1A.

1B illustrates a connection relationship between one block selection circuit and a memory block BK.

Referring to FIG. 1B, the block selection circuit of the X decoder 140 includes a memory block switch 141 and a switching unit 142.

As described above, the memory block switch 141 enables the corresponding memory block according to the control signal of the controller 160. The switching unit 142 connects the memory block with the operating voltage line output from the voltage providing unit 150 according to the enable signal of the memory block switch 141.

The voltage generated by the voltage providing unit 150 may include a global drain select line GDSL and a global source select line GSSL, which are voltage lines provided to the drain select line DSL and the source select line SSL. First to thirty-second global word lines GWL <0> to GWL <31>, which are voltage lines provided to the lines.

In addition, the global source line GSL for providing the voltage of the common source line SL of the memory block BK is also provided from the voltage providing unit 150 according to an embodiment of the present invention.

The memory block switch 141 may be configured to connect the first to second PMOS transistors P1 and P2, the first to ninth NMOS transistors N1 to N9, and the first to third NAND gates NA1 to NA3. Include.

The first and second PMOS transistors P1 and P2 are connected in series between the power supply voltage and the node a1, and the gates of the first and second PMOS transistors P1 and P2 are connected to the ground node. Therefore, the first and second PMOS transistors P1 and P2 are always turned on, and the node a1 is always kept at a high level.

The first NAND gate NA1 receives the address control signals XA, XB, XC, and XD input from the controller 160, and transfers the NAND logic result to the node a1.

The controller 160 high-levels all of the address control signals XA, XB, XC, and XD in a memory block that needs to process and select memory block address information among address signals input together with an operation command such as a program or a read. If it should not be selected, input one of the control signals to the low level.

The first NAND gate NA1 outputs a low level signal only when the input address control signals XA, XB, XC, and XD are all at a high level, and one address control signal XA, XB, XC, or XD is provided. Even at the low level, a high level signal is output.

Therefore, when the memory block is selected, the node a1 is at the low level, and otherwise, the high level is maintained.

Node a1 is input to the second NAND gate NA2. The control signal PGMPREb is input to the other input terminal of the second NAND gate NA2. The control signal PGMPREb is a signal input from the controller 160. When the operation command is input to select a memory block, the control signal PGMPREb is changed to a low level and then maintained at a high level. The output terminal of the second NAND gate NA2 is connected to the node a2.

The third NAND gate NA3 receives the node a2 and the enable control signal EN, and an output terminal of the third NAND gate NA3 is connected to the node a3.

The first and second NMOS transistors N1 and N2 are connected in series between the node a5 and the node a4, and a voltage VPP is input to the node a5. The control signal GA is input to the gate of the first NMOS transistor N1, and the control signal GB is input to the gate of the second NMOS transistor N2. The control signals GA and GB are signals input from the controller 160.

The third and fourth NMOS transistors N3 and N4 are connected in series between the node a5 and the node A4, and the gates of the third NMOS transistor N3 are connected to the third NMOS transistor N3 and the fourth NMOS. It is connected to the contact of transistor N4. The gate of the fourth NMOS transistor N4 is connected to the node a4.

The first to fourth NMOS transistors N1 to N4 apply the voltage VPP to the node a4 by the control signal so that the block switching signal BLKWL is at a high level.

The fifth NMOS transistor N5 is connected between the node a2 and the node a4, and the control signal PRE is input to the gate of the fifth NMOS transistor N5. The sixth NMOS transistor N6 is connected between the node a4 and the ground node, and the gate of the sixth NMOS transistor N6 is connected to the node a3.

The seventh NMOS transistor N7 is connected between the node a7 and the node a6, and the eighth NMOS transistor N8 is connected between the node a8 and the node a6, and the ninth NMOS transistor N7 is connected between the node a7 and the node a6. N9 is connected between the node a9 and the node a6. Gates of the seventh to ninth NMOS transistors N7 to N9 are connected to the node a3.

The node a4 is connected to the switching unit 142 as a block switching signal BLKWL.

The switching unit 142 that performs the switching operation by the block switching signal BLKWL includes the tenth to forty-fourth NMOS transistors N10 to N44. The eleventh to 42nd NMOS transistors N11 to N42 are high voltage transistors capable of passing a high voltage in a turn-on state.

The tenth NMOS transistor N10 is connected between the global drain select line GDSL of the voltage providing unit 150 and the drain select line DSL of the memory block BK, and the eleventh through 43rd NMOS transistors N11 through. N43 is connected to the global word lines GWL <31> to GWL <0> of the voltage providing unit 150 and the 32nd to 1st word lines WL <31> to WL <0> of the memory block BK. Each is connected between.

The 43rd NMOS transistor N43 is connected between the global source select line GSSL and the source select line SSL, and the 44th NMOS transistor N44 is connected between the global source line GSL and the common source line SL. Is connected to.

The block switching signal BLKWL of the memory block switch unit 141 is input to the gates of the tenth to 44th NMOS transistors N10 to N44.

The operation of the X decoder 140 will now be described in detail.

2A is a timing diagram of a control signal applied to a block switch of a selected memory block, and FIG. 2B is a timing diagram of a control signal applied to a block switch of an unselected memory block.

First, a case of a memory block selected for a program operation will be described with reference to FIG. 2A. The memory block address control signals AX, XB, and XC to be enabled by the controller 160 using address information input together with an operation command are described. , XD is input to the first NAND gate NA1. The control signal PGMPREb is input at a low level, and the control signal PRE and the control signal EN are input at a high level. In this case, all of the address control signals AX, XB, XC, and XD inputted to enable the memory block are high level signals.

Therefore, the first NAND gate NA1 outputs a low level signal to the node a1. The second NAND gate NA2 receives the low level signal of the node a1 and outputs a high level signal to the node a2 while the control signal PGMPREb is at the low level.

Since the fifth NMOS transistor N5 is turned off by the low level control signal PRE, the high level signal of the node a2 is not transmitted to the node a4.

In addition, the voltage VPP is applied for the operation, and the first to fourth NMOS transistors N1 to N4 pull up the voltage level of the node a4 to a high level by the control signals GA and GB.

Meanwhile, the third NAND gate NA3 outputs the low level signal to the node a3 by the high level node a2 and the high level enable signal EN. When the node a3 is at the low level, all of the sixth to ninth NMOS transistors N6 to N9 are turned off.

When the node a4 pulled up to a high level is pulled up, it means that the block switching signal BLKWL is at a high level. Accordingly, the tenth to forty-fourth NMOS transistors N10 to N44 of the switching unit 142 are turned on and connect the global lines to the memory block so that an operating voltage for operation may be provided. The global lines refer to the global drain select line GDSL, the global word lines GWL <0> to GWL <31>, the global source select line GSSL, and the global source line GSL.

The memory block selected by the operation of the X decoder 140 as described above performs a program operation.

In the case of a memory block that is not selected, the memory block switch 141 and the switching unit 142 operate according to the control signal as shown in FIG. 2B.

Referring to FIG. 2B, in the case of the memory block that is not selected as described above, one or more signals of the address control signals XA, XB, XC, and XD are received from the controller 160 at a low level. In FIG. 2B, the address control signal XD is at a low level.

The first NAND gate NA1 outputs a high level signal to the node a1 by the address signals XA, XB, XC, and XD.

When the node a1 is at the high level, when the voltage level of the control signal PGMPREb is at the low level, the high level signal is output to the node a2. When the control signal PGMPREb is at the high level, the low level signal is output to the node. Output as (a2).

Meanwhile, the first to fourth NMOS transistors N1 to N4 pull up the node a4 by the voltage VPP to a high level. At this time, when the node a2 is changed from the high level to the low level, the third NAND gate NA3 outputs the high level signal to the node a3 by the high level enable signal EN.

When the node a3 is at the high level, the sixth to ninth NMOS transistors N9 are turned on. When the sixth transistor N6 is turned on, the node a4 is connected to the ground node. Therefore, even if the first to fourth NMOS transistors N1 to N4 are pulled up by the voltage VPP, the node a4 does not maintain a high level and is changed to the ground node.

In addition, the node a6 to which the seventh to ninth NMOS transistors are commonly connected is a node connected to the ground node SEGND. Therefore, when the seventh to ninth NMOS transistors N7 to N9 are turned on, all of the nodes a7 to a9 are connected to the ground node.

Therefore, the drain select line DSL, the source select line SSL, and the common source line SL of the memory block BK are all connected to the ground node.

By the above operation, the power source voltage VCC may be provided to the common source line of the selected memory block while the program is being executed, and the common source line of the unselected memory block may provide the ground voltage. Accordingly, only the common source line of the selected memory block needs to be discharged after the program ends. Therefore, the influence on the substrate (Well) is greatly reduced.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 1B is a partial circuit diagram of the X decoder of FIG. 1A.

2A is a timing diagram of a control signal applied to a block switch of a selected memory block.

2B is a timing diagram of a control signal applied to a block switch of an unselected memory block.

* Brief description of the main parts of the drawings *

100 nonvolatile memory device 110 memory cell array

120: page buffer unit 130: Y decoder

140: X decoder 150: voltage provider

160: control unit 141: memory block switch unit

142: switching unit

Claims (7)

A plurality of block selection circuits for selecting each memory block of a nonvolatile memory device including a plurality of memory blocks, Each block selection circuit, A first control signal generator configured to generate a first control signal for selecting a corresponding memory block according to the address control signal; A block switching signal generator for outputting a block switching signal for providing to the selected memory block using the precharge control signal and the first control signal when the corresponding memory block is selected according to the address control signal; A control circuit for connecting a common source line of the unselected memory block to a ground node when the corresponding memory block is unselected according to the address control signal; And Pass transistors for providing operating voltages to the selected memory block according to the block switching signal Block selection circuit comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The control circuit, A switching element connected between the common source line and the ground node of the memory block; And a signal generation circuit for outputting a control signal for controlling the operation of the switching element according to the first control signal. Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, And the block switching signal is discharged to the ground voltage when the common source line is connected to the ground node by the control signal. A memory cell array including a plurality of memory blocks; A plurality of block selection circuits respectively connected to the plurality of memory blocks and configured to provide an operating voltage to a memory block selected according to an address control signal, or to connect a common source line of an unselected memory block to a ground node; Decoder; A voltage providing unit generating the operating voltage for providing the selected memory block; And A control unit for controlling the voltage providing unit to output the address control signal for controlling the operations of the plurality of block selection circuits by an input address and to generate the operating voltage according to an operation mode Nonvolatile memory device comprising a. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein Each block selection circuit, A first control signal generator configured to generate a first control signal for selecting a corresponding memory block according to the address control signal; A first control signal generator configured to generate a first control signal for selecting a corresponding memory block according to the address control signal; A block switching signal generator for outputting a block switching signal for providing to the selected memory block using the precharge control signal and the first control signal when the corresponding memory block is selected according to the address control signal; A control circuit for connecting a common source line of the unselected memory block to a ground node when the corresponding memory block is unselected according to the address control signal; And And pass transistors for providing operating voltages to the selected memory block according to the block switching signal. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, The control circuit, A switching element connected between the common source line and the ground node of the memory block; And a signal generation circuit outputting a control signal for controlling the operation of the switching element according to the first control signal. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, The control unit, And controlling the voltage providing unit to supply a power supply voltage to the common source line of the selected memory block during program execution.

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