KR100675638B1 - A method for forming complementary metal oxide semiconductor - Google Patents

Abstract

The present invention relates to a method of manufacturing a complementary metal oxide semiconductor (CMOS) thin film transistor using a printing method, comprising the steps of: preparing a substrate in which an NMOS region and a PMOS region are defined, forming polycrystalline silicon on the substrate; Patterning the polysilicon to form an active layer; forming a gate electrode on the active layer to expose portions of both sides of the active layer; and forming the active layer in any one of the NMOS and PMOS regions. Printing a resist pattern that blocks the layer and the gate electrode, and doping impurities in both regions of the active layer exposed by using the gate electrode as a mask in an area where the resist pattern is not printed, thereby providing a source and a drain. Forming a region and a source electrode in contact with the source region and a region in contact with the drain region; Comprising the step of forming a rain electrode, the resist pattern provides a method for manufacturing a CMOS thin film transistor, characterized in that the chemical properties do not change by the doped impurity ions.

Description

Method for manufacturing CMOS thin film transistor {A METHOD FOR FORMING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR}

1 is a plan view schematically showing the structure of a general liquid crystal display device.

2 shows a cross section of a CMOS;

3A to 3C are views showing a pattern forming method by a gravure offset printing method.

4A to 4H are cross-sectional views illustrating a method of manufacturing a CMOS thin film transistor according to the present invention.

*** Explanation of symbols for main parts of drawing ***

130: Cliché 131: printing roll

220 ': polysilicon layer 221: gate electrode

224 Sn, 224 Sp: Source area 224 Dn, 224 Dp: Drain area

224Cn, 224Cp: Channel area 240A: First contact hole

240B: second contact hole 270A: first resist pattern

270B: second resist pattern

The present invention relates to a method of manufacturing a CMOS thin film transistor using a printing method, and in particular, by forming a resist used as a doping mask in a process of doping impurities in an active layer through a printing method, a CMOS to simplify the process further. It relates to a method for manufacturing a thin film transistor.

 Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

In this case, a thin film transistor (TFT) is generally used as a switching element of the liquid crystal display, and amorphous silicon or polycrystalline silicon is used as a channel layer of the thin film transistor. .

In particular, a liquid crystal display device using a polycrystalline silicon thin film transistor has a structure in which a driving circuit portion and a pixel portion are built in a glass substrate, and the driving circuit integrated liquid crystal display device is formed for each pixel to drive the pixel. The thin film transistor for driving and the pixel driving thin film transistor for driving the pixel driver may be divided into a thin film transistor for a driving circuit for applying a signal to a gate line and a data line, which will be described in detail with reference to the accompanying drawings.

Fig. 1 is a plan view schematically showing the structure of a general liquid crystal display device, showing a drive circuit-integrated liquid crystal display device in which a drive circuit portion is integrated on an array substrate.

As shown in the figure, the driving circuit-integrated liquid crystal display device 5 is largely composed of an array substrate 10 and a color filter substrate 20 and a liquid crystal layer formed between the array substrate 10 and the color filter substrate 20. Not shown).

The array substrate 10 includes a pixel portion 35, which is an image display area in which unit pixels are arranged in a matrix form, a gate driving circuit portion 34 and a data driving circuit portion 33 positioned outside the pixel portion 35. It consists of a driving circuit part.

In this case, although not shown in the drawing, the pixel units 35 of the array substrate 10 are arranged horizontally and horizontally on the substrate 10 to define a plurality of gate lines and data lines, and the gate lines and data. A thin film transistor, which is a switching element formed in an intersection region of a line, and a pixel electrode formed in the pixel region.

The thin film transistor is a switching element that applies and cuts off a signal voltage to a pixel electrode and is a type of field effect transistor (FET) that controls the flow of current by an electric field.

In the driving circuit units 33 and 34 of the array substrate 10, the data driving circuit unit 33 is positioned at one long side of the array substrate 10 protruding from the color filter substrate 20. The gate driving circuit part 34 is positioned at one end side of the array substrate 10.

In this case, the gate driving circuit part 34 and the data driving circuit part 33 use a thin film transistor having a CMOS structure as an inverter to properly output the input signal.

CMOS is a kind of integrated circuit with MOS structure which is used for thin film transistor of driving circuit which requires high speed signal processing. It requires P channel and N channel transistor, and the speed and density characteristics are intermediate between NMOS and PMOS.

2 shows a thin film transistor having a CMOS structure. As shown in the figure, the CMOS thin film transistor 10 is composed of an NMOS and a PMOS.

The NMOS and the PMOS are formed on the substrate 11 by an active layer 24An, which is divided into channel regions 24Cn and 24Cp and source regions 24Sn and 24Sp and drain regions 24Dn and 24Dp on both sides of the channel regions 24Cn and 24Cp, respectively. 24Ap is formed, and a gate electrode 21 is formed on the channel regions 24Cn and 24Cp. In this case, a first insulating film 15A is formed between the channel regions 24Cn and 24Cp and the gate electrode 21, and the first insulating film 15A includes a substrate including the active layers 24An and 24Ap. 11) formed over the entire surface.

In addition, a second insulating film 15B is formed on the entire surface of the substrate 11 including the gate electrode 21, and source regions 24Sn of the NMOS and PMOS are formed on the first and second insulating films 15A and 15B. A source contact hole 22 'and a drain contact hole 23' exposing the portions 24Sp and portions of the drain regions 24Dn and 24Dp are formed.

On the second insulating film 15B, the source electrode 22 which contacts the source contact hole 22 'to the source regions 24Sn and 24Sp, and the drain region 24Dn through the drain contact hole 23'. A drain electrode 23 is formed in contact with 24Dp.

On the other hand, in order to fabricate the CMOS thin film transistor configured as described above, the pattern (gate electrode, source / drain region, source / drain electrode, source / drain contact hole, etc.) by photolithography method using an exposure apparatus. Will form. However, the photolithography process is a process that forms a pattern through a continuous process such as photo-resist coating, alignment & exposure, development, strip, etc., and the process is complicated. Do.

In addition, since a plurality of photo processes must be repeated to form a pattern of the thin film transistor, there is a problem that productivity is lowered.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a CMOS thin film transistor which can improve the productivity by simplifying the process.

In order to achieve the above object, a method of manufacturing a CMOS thin film transistor according to the present invention includes preparing a substrate in which an NMOS region and a PMOS region are defined, forming polycrystalline silicon on the substrate, and patterning the polysilicon. Forming an active layer, forming a gate electrode on the active layer to expose a portion of both sides of the active layer, and forming the active layer and the gate electrode in one of the NMOS and PMOS regions. Printing a blocking resist pattern and forming a source and a drain region by doping impurities in both regions of the active layer exposed by using the gate electrode as a mask in an area where the resist pattern is not printed; Forming an insulating film on an entire surface of the substrate including the source region and the drain region; By the Rafi processing step by etching the insulating film to form a second contact hole exposing a portion of the first contact hole and the respective drain regions to expose each of the source regions of the NMOS and PMOS regions; And forming a source electrode in contact with the source region and a drain electrode in contact with the drain region on a substrate having the first contact hole and the second contact hole, wherein the resist pattern is formed in the first contact hole. And relatively larger than the pattern size of the second contact hole.

The printing of the resist pattern may include preparing a cliché in which a plurality of grooves are formed in a region where the resist pattern is to be formed, filling a resist into the groove, and printing a cylindrical printing roll on the cliché. After contacting, rotating the resist filled in the groove on the surface of the printing roll and transferring the resist transferred on the surface of the printing roll onto the substrate.

The printing of the resist pattern may include preparing a cliché in which a plurality of grooves are formed in a region where the resist pattern is to be formed, filling a resist into the groove, and attaching the cliché to a substrate. Thereafter, as it is isolated from the substrate, the resist filled in the groove may be transferred onto the substrate.

At this time, since the resist used should not be chemically changed by impurities, it is preferable to use a resist whose viscosity is between 100p and 1000p.

The forming of the source region and the drain region in the NMOS region and the PMOS region may include exposing a gate electrode formed in the NMOS region and printing a first resist pattern blocking the active layer and the gate electrode formed in the PMOS region. Forming a source and a drain region of the NMOS region by doping n + impurity ions in the exposed regions on both sides of the active layer using the gate electrode of the NMOS region as a mask; and forming a first resist pattern of the PNMOS region. After removal, printing a second resist pattern for blocking the active layer and the gate electrode formed in the NMOS region and the PMOS by doping p + impurity ions in the exposed regions on both sides of the active layer using the gate electrode of the PMOS region as a mask Forming a source and a drain region of the region.

In this case, the resist pattern may be removed using a stripper such as acetone or NMP.

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The method may further include forming a low doped drain (LDD) region or an offset region between the active region and the source and drain regions.

The present invention further includes forming a first insulating film on a substrate having the active layer after forming the active layer and before forming the gate electrode.

The active layer, the gate electrode, and the source / drain electrode may be formed through a photolithography process. That is, by forming a pattern through a printing method when forming a pattern (particularly, a resist pattern formed to block an NMOS or PMOS region in a doping process) in which a fine pattern is not required in the present invention, the process can be further simplified. In the case of a pattern requiring a fine pattern, a fine pattern can be accurately formed by forming a pattern through a photolithography process.

Furthermore, since the use of the resist pattern formed by the printing method in the present invention merely serves as an impurity blocking film to block the doping material, there should be no chemical change by impurity doping so that it can be easily removed by a stripper such as acetone or NMP. do.

In the present invention, a printing method is used in a method of forming a CMOS pattern, in particular, a resist pattern used as a doping mask. In particular, gravure offset printing is a printing method in which a resist is buried in a concave plate to scrape off excess resist and printed, and is known as a printing method in various fields such as publishing, packaging, cellophane, vinyl, polyethylene, and the like. In the present invention, such an printing method is used to produce an active element or a circuit pattern applied to the display element.

Since gravure offset printing transfers resist onto a substrate using a printing roll, a pattern can be formed by one transfer even in the case of a large area element by using a transfer roll corresponding to the area of a desired element. Such gravure offset printing can be used to pattern various patterns of display devices, for example, TFTs as well as gate patterns and data lines, pixel electrodes, and capacitor metal patterns connected to the TFTs.

Hereinafter, a pattern forming method according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C show a method of forming a resist pattern on a substrate using a printing method. As shown in FIG. 3A, in the printing method, first, the groove 132 is formed at a specific position of the concave plate or the cliché 130, and then the resist 134 is filled in the groove 132. The groove 132 formed in the cliché 130 is formed by a general photolithography method, and filling the resist 134 into the groove 132 is a pattern forming resist 134 on the top of the cliché 130. ) And then push the doctor blade 138 in contact with the surface of the cliché 130. Accordingly, as the doctor blade 138 proceeds, the resist 134 is filled in the groove 132 and the resist 134 remaining on the surface of the cliché 130 is removed.

As shown in FIG. 3B, the resist 134 filled in the groove 132 of the cliché 130 is transferred to the surface of the printing roll 131 which rotates in contact with the surface of the cliché 130. do. The printing roll 131 is formed to have the same width as the width of the panel of the display device to be manufactured, and has a circumference of the same length as the length of the panel. Therefore, the resist 134 filled in the groove 132 of the cliché 130 is transferred to the circumferential surface of the printing roll 131 by one rotation.

3C, the resist transferred to the printing roll 131 as the printing roll 131 is rotated in contact with the surface of the etch target layer 140 formed on the substrate 130 ′. 134 is transferred to the etching target layer 140, and the resist pattern 133 is formed by applying UV radiation or heat to the transferred resist 134 to dry. In this case, the desired pattern 133 may be formed over the entire substrate 130 ′ of the display device by one rotation of the printing roll 131. Subsequently, by etching the etching target layer 140 using the resist pattern 133 as a mask, a desired pattern can be formed.

As described above, in the printing method, the cliché 130 and the printing roll 131 can be manufactured according to the size of the desired display element, and a pattern can be formed on the substrate 130 'by one transfer. The pattern of the area display element can also be formed by one process.

The etching target layer 140 may be a metal layer for forming an electrode such as a gate electrode, a source / drain electrode, a gate line, a data line, or a pixel electrode of the TFT, or may be a semiconductor layer for forming an active layer, and may be formed of SiOx or SiNx. Similarly, the insulating layer may be used.

When forming a pattern of an actual display device, the resist pattern 133 serves as a resist in a conventional photo process. Therefore, after forming the resist pattern 133 as described above on the metal layer or the insulating layer, the metal layer or the insulating layer is etched by a general etching process, so that the metal layer (ie, the electrode structure) or the insulating layer (for example, the contact) of the desired pattern is formed. Holes, etc.) can be formed.

On the other hand, although not shown in the drawing, without using the printing roll, the cliché is brought into contact with the substrate, and then separated from the substrate, thereby directly transferring the resist filled in the groove of the cliché onto the substrate. It may be.

As described above, when the resist filled in the grooves of the cliché is directly transferred onto the substrate, a printing roll is not required, and the process of transferring the resist of the cliché to the printing roll is omitted, thereby simplifying the printing process. There is an advantage.

As described above, the printing method has many advantages. In particular, a resist pattern is formed on a large display device by one process or the process is very simple compared to a conventional photolithography process, which is a representative advantage of the printing method.

However, the printing method as described above is less accurate than the photolithography method, and thus, in forming an element requiring a fine pattern, it may cause a decrease in productivity due to a pattern defect, and thus is applied to forming a pattern of an actual element. There is no way down.

Accordingly, in the present invention, a photolithography method is used for a pattern requiring a fine pattern, and a printing method is used for a relatively large pattern, so that the process can be simplified. In particular, in the present invention, a resist pattern is printed as a doping mask by implanting impurity ions into a region of NMOS or PMOS in a CMOS thin film transistor.

Hereinafter, a method of manufacturing a CMOS thin film transistor according to the present invention will be described in detail with reference to the accompanying drawings.

4A to 4C are cross-sectional views illustrating a method of manufacturing a CMOS thin film transistor according to the present invention. First, as shown in FIG. 4A, an amorphous silicon layer 220 is formed on a substrate 210 on which an NMOS region and a PMOS region are defined. ). The amorphous silicon thin film may be formed by depositing in various ways, and representative methods of depositing the amorphous silicon thin film include low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor). Deposition (PECVD) method. In this case, after forming a buffer layer consisting of a silicon oxide film (SiO ₂ ) on the substrate 210, an amorphous silicon layer 120 may be formed on the buffer layer. The buffer layer serves to block impurities such as sodium (natrium) from the glass substrate 210 from penetrating into the upper layer during the process.

After the amorphous silicon layer 220 is formed, a heat treatment is performed at a temperature of about 400 ° C., followed by a dehydrogenation process to release hydrogen contained in the amorphous silicon layer 220.

Dehydrogenating amorphous silicon is previously removed by heat treatment because hydrogen gas contained in the amorphous silicon layer may explode in the process of crystallizing the amorphous silicon and may damage the substrate.

Then, by irradiating the laser to the amorphous silicon layer 220, as shown in Figure 4b, to form a polysilicon layer 220 '.

The polysilicon layer 220 'is patterned to form an active layer 224 remaining in the NMOS and PMOS regions, as shown in FIG. 4C. In this case, the active layer 224 pattern may be formed by a printing method or a photolithography method.

That is, after the photoresist is applied on the polysilicon layer, the photoresist is exposed through a mask prepared in advance, and the exposed photoresist is developed to form a photoresist pattern selectively remaining on the polysilicon layer. . The polysilicon layer is etched using the photosensitive pattern as a mask to form an active layer. Alternatively, although the active layer may be formed through the printing method described with reference to FIGS. 3A to 3C, the photolithography method may be used to form the active layer pattern more accurately than the printing method.

As described above, after the active layer 224 is formed, as shown in FIG. 4D, the first insulating layer 215A is formed on the entire surface of the substrate 210 including the active layer 224. A gate electrode 221 made of a conductive metal material is formed on the first insulating layer 215A. In this case, the gate electrode 221 is formed of aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), and molybdenum on the first insulating layer 215A. After depositing a conductive metal material such as Mo), and then patterning the conductive metal material using a photolithography process, and the gate electrode 221 does not cover both partial regions of the active layer 224. To avoid formation.

As such, after the gate electrode 221 is formed, as shown in FIG. 4E, a first resist pattern 270A for blocking the PMOS region is formed. In this case, the first resist pattern 270A may be formed by a printing method. The first resist pattern 270A is for blocking the PMOS region, and does not require the accuracy of the pattern. Therefore, it is more advantageous in terms of process efficiency to use a printing method than a photolithography method.

Subsequently, n + impurities are formed on both sides of the active layer 224 of the NMOS region in which the gate electrode 221 is not formed, using the first resist pattern 270A formed in the PMOS region and the gate electrode 221 formed in the NMOS region as a mask. Ions are implanted to form N-type source / drain regions 224Sn / 224Dn.

As a result, in the active layer 224 of the NMOS region, a channel region 224Cn is formed in a region corresponding to the gate electrode 221, and in both regions of the active layer 224 that do not overlap the gate electrode 221. The source region 224Sn and the drain region 224Dn are formed.

In this case, the first resist pattern 270A should have no change in chemical properties by implantation of n + impurity ions, and perfect implantation of the impurity ions into the active layer 224 formed under the first resist pattern 270A. It must be strong enough to block it. Therefore, in the present invention, a resist having a viscosity of 50p or more is used as a doping mask, and more preferably, a resist having a viscosity in the range of 100p to 1000p.

After the N-type source / drain regions are formed in the NMOS region, the first resist pattern 270A blocking the PMOS region is removed. In this case, the first resist pattern 270A may be completely removed by a stripper such as NMP or acetone. In addition, the first resist pattern 270A may be removed by an ashing process.

As shown in FIG. 4F, a second resist pattern 270B for blocking the NMOS region is formed. In this case, like the first resist pattern, the second resist pattern 270B is formed through the printing method described with reference to FIGS. 3A to 3C.

Subsequently, p + impurity ions are formed in the active layer 224 of the PMOS region, which does not overlap the gate electrode 221, using the second resist pattern 270B formed in the NMOS region and the gate electrode 221 formed in the PMOS region as a mask. Is injected to form P-type source / drain regions 224Sp / 224Dp.

As a result, in the active layer 224 of the PMOS region, a channel region 224Cp is formed in a region corresponding to the gate electrode 221, and in both regions of the active layer 224 that do not overlap the gate electrode 221. The source region 224Sp and the drain region 224Dp are formed.

In this case, the first resist pattern 270A should have no change in chemical characteristics by implantation of p + impurity ions, and the impurity ions are implanted into the active layer 224 formed under the second resist pattern 270B. It should be strong enough to completely block the process, and a resist having a viscosity of 50p or more used for printing the second resist pattern is used as a doping mask, and more preferably has a viscosity in the range of 100p to 1000p. Use a resist.

In addition, after printing the first or second resist patterns 270A and 270B, the patterns 270A and 270B may be further cured by irradiating heat or UV.

Meanwhile, an undoped region is formed in a predetermined portion between the channel region and the source / drain region of the NMOS region to form an offset, or a lightly doped drain (LDD) region that is lightly doped to form an off current. You can also reduce and minimize the reduction of on current.

In addition, in the present embodiment, the n-type source / drain regions 124An and 124Bn (that is, the NMOS thin film transistor) and the P-type source / drain 124Ap and 124Bp are formed in a manner of performing p + doping after n + doping. That is, a case of forming a PMOS thin film transistor) is described as an example, but the present invention is not limited thereto, and the two processes may be changed.

The electrical characteristics of the active layer are changed according to the type of dopant to be implanted. An N-type element may be formed by injecting a Group 5 element such as phosphorus or arsenic or a P-type may be formed by injecting a Group 3 element such as boron.

Subsequently, an activation process of activating the ions may be performed by using a laser or heat treatment at about 450 ° C. or instantaneous heat treatment.

As described above, both the N-type source / drain regions 224Sn and 224Dn and the P-type source / drain regions 224Sp and 224Dp are formed, and as shown in FIG. 4G, the gate electrode 221 is included. After the second insulating film 215B is coated on the entire surface of the substrate, the first contact hole 240A and the drain regions 224Dn and 224Dp exposing the source regions 224Sn and 224Sp of the NMOS and PMOS regions are exposed. Two contact holes 240B are formed.

In this case, the first and second contact holes 240A and 240B are formed through patterning of the first and second insulating layers 215A and 215B. In this case, a photolithography method is used. In particular, since the first and second contact holes 240A and 240B are smaller in size than other patterns (eg, active layers, gate electrodes, etc.), only the photolithography method can be used, and the printing method can be used. In this case, a defect is caused.

Next, as shown in FIG. 4H, a conductive metal material is deposited on the second insulating layer 215B, and then patterned, so that a source region (N) and a PMOS region may be formed through the first contact hole 270A. Source electrodes 222 connected to 224Sn and 224Sp and drain electrodes 223 connected to drain regions 224Dn and 224Dp are formed through the second contact hole 270B.

In this case, the source electrode 222 and the drain electrode 223 may be formed using a photolithography method, and may cause a pattern defect when using the printing method.

Subsequently, although not shown in the drawings, a protective film is formed on the entire surface of the substrate including the source electrode and the drain electrode, a contact hole exposing the source electrode and the drain electrode is formed, and then the electrodes are connected to each other through the contact hole. Will be connected.

Meanwhile, the present invention may separately form a surface treatment or an adhesion strengthening film in order to improve adhesion with the lower layer in the process of printing a resist pattern.

Surface treatment may use plasma such as N ₂ , O ₂ , He, H, and the like, and as an adhesion enhancing film, reactive monomers such as polyethyleneimine, isocyanate compounds, polyester resins, vinyl acetate resins, polymers or resin films, etc. Can be used.

As described above, the process has been described with reference to a manufacturing process of a CMOS formed in the driving circuit unit. In the process of forming the driving circuit unit, a thin film transistor may be simultaneously formed as a switching element in the pixel portion of the liquid crystal display. The thin film transistor of the pixel portion may be formed by selecting from PMOS or NMOS.

As described above, the present invention can simplify the process by applying a printing method to a pattern for which precision is not required when forming a CMOS. That is, the precision of the pattern like the gate electrode, the source electrode, the drain electrode, and the contact hole active layer (where the precision of the pattern means that the pattern has a fatal effect on the product when the pattern is not formed at a desired position. When the precision of a pattern is required, such as a fine pattern, a pattern is formed through a photolithography method, and a pattern is formed through a printing method for a large pattern in a state where the giant pattern selectively implants impurity ions. In this case, it means a resist pattern used as a blocking film of impurity ions.

Therefore, when manufacturing a CMOS thin film transistor, by forming a resist pattern used for blocking impurity ion implantation through a printing method, two photolithography processes can be reduced. In the present invention, two photolithography processes are omitted in comparison with the conventional art, but two printing processes are added. However, as described above, since the printing process is very simple compared to the photolithography process, the CMOS thin film is substantially reduced. In manufacturing the transistor, the process time can be shortened.

As described above, according to the present invention, a photolithography method is used when forming a CMOS thin film transistor used in a driving circuit, and in particular, when a n + or p + doped region is formed, a pattern used as a doping blocking film is printed. By forming through the method, process time can be shortened.

In addition, the present invention can be completely removed to a stripper such as acetone or NMP by using a material that the pattern used as the doping barrier film does not change the chemical properties by the doping impurity ion.

Claims (14)

Preparing a substrate in which an NMOS region and a PMOS region are defined; Forming polycrystalline silicon on the substrate; Patterning the polysilicon to form respective active layers in the NMOS region and the PMOS region; Forming respective gate electrodes in the NMOS region and the PMOS region so that portions of both sides of the active layer are exposed on the active layer; Printing a resist pattern on one of the NMOS and PMOS regions to block the active layer and the gate electrode; Forming a source and a drain region by doping impurities in both regions of the active layer exposed by using the gate electrode as a mask in a region where the resist pattern is not printed; Forming an insulating film on an entire surface of the substrate including the source and drain regions; And Etching the insulating film by a photolithography process to form a first contact hole exposing each source region of the NMOS and PMOS regions and a second contact hole exposing a portion of each drain region; And Forming a source electrode in contact with the source region and a drain electrode in contact with the drain region on a substrate having the first contact hole and the second contact hole; The resist pattern has no chemical property change due to impurity implantation, and the manufacturing method of the CMOS thin film transistor, characterized in that the relatively larger than the pattern size of the first contact hole and the second contact hole. The method of claim 1, wherein the printing of the resist pattern comprises: Preparing a cliché having a plurality of grooves formed in a region where the resist pattern is to be formed; Filling resist into the groove; Contacting a cylindrical printing roll on the cliché and rotating it, thereby transferring a resist filled in the groove to the surface of the printing roll; And And retransferring the resist transferred onto the surface of the printing roll onto a substrate. The method of claim 1, wherein the printing of the resist pattern comprises: Preparing a cliché having a plurality of grooves formed in a region where the resist pattern is to be formed; Filling resist into the groove; And And attaching the cliché to the substrate and isolating it, thereby transferring a resist filled in the groove onto the substrate. The method of manufacturing a COMS thin film transistor according to claim 2 or 3, wherein the resist has a viscosity of 100p to 1000p. The method of claim 1, wherein forming a source region and a drain region in the NMOS region and the PMOS region comprises: Exposing a gate electrode formed in the NMOS region, and printing a first resist pattern blocking the active layer and the gate electrode formed in the PMOS region; Forming a source and a drain region of the NMOS region by doping n + impurity ions in the exposed regions on both sides of the active layer using the gate electrode of the NMOS region as a mask; After removing the first resist pattern of the PNMOS region, printing a second resist pattern blocking the active layer and the gate electrode formed on the NMOS region; And And forming a source and a drain region of the PMOS region by doping p + impurity ions in the exposed regions on both sides of the active layer using the gate electrode of the PMOS region as a mask. The method of claim 5, further comprising a surface treatment step using N ₂ , O ₂ , He, H, or the like to form the adhesion of the resist pattern on the areas where the first and second resist patterns are printed. Method for manufacturing a CMOS thin film transistor. The method of claim 5, wherein the reactive monomer or polymer such as polyethyleneimine, isocyanate-based compound, polyester-based resin, vinyl acetate-based resin in order to form the adhesion of the resist pattern in the area where the first and second resist pattern is printed; A method of manufacturing a CMOS thin film transistor further comprising the step of coating a resin having excellent adhesion. delete The method of claim 5, wherein the resist pattern is removed using a striper such as acetone or NMP. The method of manufacturing a CMOS thin film transistor according to claim 5, wherein the resist pattern is removed by an ashing process. The method of claim 1, wherein after forming the source and drain regions, And forming a low doped drain (LDD) region between the active region and the source and drain regions. The method of claim 1, wherein after forming the source and drain regions, And forming an offset (off-set) region between the active region and the source and drain regions. The method of claim 1, further comprising forming a first insulating layer on the substrate having the active layer after forming the active layer and before forming the gate electrode. The method of claim 1, wherein the active layer, the gate electrode, and the source / drain electrode are formed by a photolithography method.

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