KR100673146B1 - Power-on reset circuit in rfid with non-volatile ferroelectric memory - Google Patents

Abstract

A power-on reset circuit in RFID having a non-volatile ferroelectric memory is provided to generate a power-on reset signal irrespective of a power-up slope by generating the power-on reset signal by a sensing current level without using an RC delay method. A latch unit(151) outputs a supply voltage to a first node. A pull-down control unit(154,155) pulls down a second node according to the voltage level of the first node and pulls down the first node according to the voltage level of the second node. A pull-up current supply unit(152) supplies pull-up current to the first node according to the voltage level of the second node. A reset voltage control unit(157) outputs the dropped supply voltage to the second node. A pull-up control unit(156) controls the supply of the pull-up current in order to pull up the voltage level of the second node after transition of a power-on reset signal. A reset signal output unit(153) senses the threshold voltage of the first node and outputs the power-on reset signal. Each of the latch unit, the pull-down control unit, the pull-up current supply unit, and the reset signal output unit includes a plurality of current limit resistance elements.

Description

Power-On reset circuit in RFID with non-volatile ferroelectric memory

1 is a circuit diagram of a power-on reset circuit according to the prior art.

2A and 2B are operational timing diagrams of a power-on reset circuit according to the prior art.

3 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention;

4 is a circuit diagram of a power-on reset circuit in RFID including a nonvolatile ferroelectric memory in accordance with the present invention.

5 is an operation timing diagram of a power-on reset circuit according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit in an RFID including a nonvolatile ferroelectric memory, and a technique for reducing current consumption during power-on reset in an RFID power-on reset circuit using a nonvolatile ferroelectric capacitor. to be.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

In a system using such a nonvolatile ferroelectric memory as a memory device, when the system controller outputs a chip enable signal to the nonvolatile ferroelectric memory chip, the memory device in the memory chip operates the memory cell of the chip according to the chip enable signal. Generates an on-chip control signal for Data is written to or read from memory cells in response to these in-chip control signals.

In addition, a system using a nonvolatile ferroelectric memory needs to read and set up data stored in a code register again when power is first applied to the nonvolatile ferroelectric memory. This code register read operation allows the use of a power-on reset signal.

The conventional reset circuit is configured such that the voltage generated by the reset signal is greatly affected by the power-up slope of the power supply voltage. Accordingly, the reset signal has a problem that occurs even at a low power supply voltage when the power-on slope is gentle.

1 is a circuit diagram related to such a conventional power-on reset circuit.

The conventional power-on reset circuit includes PMOS transistors P1 and P2, capacitors C1 and inverters IV1 to IV3.

Here, the PMOS transistor P1, which is a pull-up current source, is connected between the power supply voltage VDD applying terminal and the capacitor C1 and a ground voltage is applied through the gate terminal. The PMOS transistor P1 is always turned on to supply a pull-up current. Capacitor C1 is composed of an NMOS capacitor and is connected between the PMOS transistor P1 and the ground voltage VSS applying terminal. The PMOS transistor P2 is connected between the power supply voltage VDD applying stage and the output terminal of the inverter IV1 to receive the output of the inverter IV2 through the gate terminal. The inverter IV3 inverts the output of the inverter IV2 and outputs a reset signal RESET.

In the conventional power-on reset circuit having this configuration, the slope of the reset signal RESET is determined by the RC delay time between the PMOS transistor P1 and the capacitor C1, the pull-up current source having the channel resistance.

Therefore, in order for the memory chip to operate stably, the power-up operation must be performed within a certain time. However, if the power-up time exceeds a certain time due to any cause in the code register, the data stored in the code register is destroyed.

2A and 2B are timing diagrams illustrating that the reset signal RESET is generated when the power supply voltage VDD increases with a fast slope and with a slow slope, respectively.

As shown in FIG. 2A, when the power supply voltage rises from the ground voltage VSS level to the power supply voltage VDD level with a fast slope, it can be seen that the power-on reset signal POR is generated at a predetermined voltage (time T3) or more.

On the contrary, as shown in FIG. 2B, when the power supply voltage gradually rises from the ground voltage VSS level to the power supply voltage VDD level with a slow slope, the capacitor C1 is precharged for more time than in the case of FIG. 2A. Accordingly, it can be seen that the power-on reset signal POR is generated at a low voltage (time T2) as the sensing level of the capacitor C1 is rapidly increased.

As such, the generation of the reset signal may become unstable according to the degree of change in the power supply voltage, thereby operating the code register at a voltage lower than the normal voltage. In this case, there is a problem in that data stored in the code register is erroneously read or restored in an insufficient state to cause an error in the code register.

Therefore, there is an urgent need for a circuit that can generate a power-on reset signal POR above a certain voltage on any power-up slope. Control of the reset signal in such a power-on reset circuit has a great influence on reducing the current consumption of the radio frequency identification (RFID) device.

The present invention has been made to solve the above problems, and in the power-on reset circuit of RFID using a nonvolatile ferroelectric capacitor, the reset signal is stably stable only when the power supply voltage becomes higher than a predetermined level regardless of the power-on slope. The purpose of this is to reduce the current consumption by generating.

A power-on reset circuit in an RFID including a nonvolatile ferroelectric memory of the present invention for achieving the above object comprises: a latch unit for maintaining a level of a power supply voltage for a predetermined period and outputting it to a first node; Pull-down control means for pull-down control of the second node according to the voltage level of the first node, and pull-down control of the first node according to the voltage level of the second node; A pull-up current supply unit supplying a pull-up current to the first node according to the voltage level of the second node; A reset voltage adjusting unit outputting the power supply voltage to the second node by dropping the power supply voltage to a predetermined level; A pull-up adjustment unit controlling the supply of the pull-up current according to the self-biased gate voltage to pull up the voltage level of the second node to the power supply voltage level after the power-on reset signal transition; And a reset signal output unit for outputting a power-on reset signal by buffering the voltage of the first node, wherein the latch unit, the pull-down control unit, the pull-up current supply unit, and the reset signal output unit each include a plurality of currents for restricting the flow of the current. It is characterized by including a limiting resistor element.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention. The radio frequency identification (RFID) device of the present invention includes an analog block 100, a digital block 200, and a non-volatile ferroelectric random access memory (FeRAM) 300.

Here, the analog block 100 may include a voltage multiplier 110, a voltage limiter 120, a modulator 130, a demodulator 140, and a power on reset; 150 and a clock generator 160.

And, the antenna 10 of the analog block 100 is a configuration for transmitting and receiving radio frequency signal RF between the external reader or writer and RFID. The voltage multiplier 110 generates a power supply voltage VDD which is a driving voltage of the RFID by the radio frequency signal RF applied from the antenna 10. The voltage limiter 120 limits the magnitude of the transmission voltage of the radio frequency signal RF applied from the antenna 10 and outputs it to the demodulator 140 and the clock generator 160.

In addition, the modulator 130 modulates the response signal RP applied from the digital block 200 and transmits it to the antenna 10. The demodulator 140 detects an operation command signal from a radio frequency signal RF applied from the antenna 10 according to the output voltages of the voltage multiplier 110 and the voltage limiter 120 and transmits the command signal DEMOD to the digital block 200. Output

The power-on reset unit 150 detects the output voltage VDD of the voltage multiplier 110 and outputs a power-on reset signal POR for controlling the reset operation to the digital block 200. The clock generator 160 supplies the clock CLK for controlling the operation of the digital block 200 to the digital block 200 according to the output voltage VDD of the voltage multiplier 110.

In addition, the above-described digital block 200 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal DEMOD from the analog block 100 to interpret the command signal and generate control signals and processing signals to generate the analog block. The response signal RP corresponding to 100 is output. The digital block 200 outputs the address ADD, the input / output data I / O, the control signal CTR, and the clock CLK to the FeRAM 300. The FeRAM 300 is a memory block that reads / writes data using a nonvolatile ferroelectric capacitor element.

The passive element power of the RFID chip having such a configuration uses the power delivered to the antenna 10. However, in the case of the RFID chip for long-distance operation, the power delivered to the antenna 10 is very weak. At this time, when the power consumed by the RFID chip is larger than the power delivered to the RFID chip, the power of the RFID chip no longer increases.

When power is supplied to the RFID chip, the power-on reset circuit initially consumes all the power. After the generation of the power-on reset signal POR, the power is used in the remaining circuit blocks of the RFID chip.

Therefore, power consumption in the power-on reset circuit becomes a very important item. The present invention allows the configuration of the power-on reset circuit to limit the flow of current by using a high resistance element to satisfy this requirement. Therefore, a small current of 1 mA or less flows during the power-on reset operation to reduce power consumption. In addition, after the generation of the power-on reset signal POR, the current path is blocked to reduce the current consumption.

4 is a detailed configuration diagram illustrating the power-on reset unit 150 of FIG. 3.

The power-on reset unit 150 includes pull-down capacitors PD1 and PD2, a latch unit 151, a pull-up capacitor PU1, a pull-up current supply unit 152, a reset signal output unit 153, and a pull-down adjusting unit ( 154, 155, a pull-up adjusting unit 156, and a reset voltage adjusting unit 157.

Here, the pull-down capacitor PD1 includes an NMOS transistor N1 and a capacitor C2. The NMOS transistor N1 has a source / drain terminal connected to the node NPOR_2, and a ground voltage is applied through the gate terminal. The capacitor C2 is composed of an NMOS capacitor connected to the node NPOR_2.

The latch unit 151 includes resistors R1 and R2, PMOS transistors P3 and P4, and NMOS transistors N2 to N4. Here, the resistor R1 is connected between the supply voltage VDD applying terminal and the common source terminal of the PMOS transistors P3 and P4. PMOS transistors P3 and P4 and NMOS transistors N2 and N3 are cross-coupled to form a latch structure. The NMOS transistor N4 is connected between the common source terminals of the NMOS transistors N2 and N3 so that the gate terminal is connected to the node NPOR_1. Resistor R2 is connected between NMOS transistor N4 and ground GND voltage terminal. At this time, the resistors R1 and R2 use a resistor having a large resistance value to allow a small current of 1 mA or less to flow through the nodes NPOR_1 and NPOR_2.

In addition, the pull-up capacitor PU1 is connected between the power supply voltage terminal and the node NPOR_1 to form a PMOS capacitor. The pull-up current supply unit 152 includes a resistor R3 and a PMOS transistor P5. Resistor R3 is connected between the supply voltage terminal and the PMOS transistor P5. The PMOS transistor P5 is connected between the resistor R3 and the node NPOR_1 so that the gate terminal is connected to the node NPOR_3. At this time, the resistor R3 allows a small current of 1 mA or less to flow through the node NPOR_1 using a resistor having a large resistance value.

The reset signal output unit 153 includes resistors R4 and R5, PMOS transistors P6 and P7, and NMOS transistors N5 and N6. Here, the PMOS transistors P6 and P7 and the NMOS transistors N5 and N6 have a structure in which two CMOS inverters are connected to each other. That is, the PMOS transistor P6 and the NMOS transistor N5 are connected in series between the resistor R4 and the resistor R5 so that the gate terminal is connected to the node NPOR_1. The PMOS transistor P7 and the NMOS transistor N6 are connected between the resistor R4 and the resistor R5 so that the gate terminal is connected to the common drain terminal of the PMOS transistor P6 and the NMOS transistor N5. The power-on reset signal POR is output through the common source terminal of the PMOS transistor P7 and the NMOS transistor N6.

In addition, the resistor R4 is connected between the power supply voltage terminal and the PMOS transistor P6, and the resistor R5 is connected to the NMOS transistor N5 and the ground voltage terminal to serve as a current limiting device. At this time, the resistors R4 and R5 allow a small current of 1 mA or less to flow through the power-on reset unit 150 by using a resistor having a large resistance value.

In addition, the pull-down adjusting unit 154 is connected between the node NPOR_1 and the ground voltage terminal, and the gate terminal is connected to the node NPOR_3. The pull-down adjuster 155 includes a resistor R6 and an NMOS transistor N8. Here, the resistor R6 is connected between the node NPOR_3 and the NMOS transistor N8. The NMOS transistor N8 is connected between the resistor R6 and the ground voltage terminal so that the gate terminal is connected to the node NPOR_1. The pull-down capacitor PD2 includes an NMOS transistor N9 having a source / drain terminal connected to the node NPOR_3 and applying a ground voltage through the gate terminal. At this time, the resistor R6 causes a small current of 1 mA or less to flow through the node NPOR_3 using a resistor having a large resistance value.

The pull-up adjusting unit 156 includes PMOS transistors P8 to P12 and NMOS transistor N10. Here, in the PMOS transistor P8, a source / drain terminal is connected to a power supply voltage terminal and a gate terminal is connected to an NMOS transistor N10. The NMOS transistor N10 is connected between the gate terminal and the ground voltage terminal of the PMOS transistor P8 so that the gate terminal is commonly connected to the drain terminal. The PMOS transistors P9 to P12 are connected in series between the power supply voltage terminal and the node NPOR_3 so that the gate terminal is commonly connected to the gate terminal of the PMOS transistor P8.

The reset voltage adjusting unit 157 includes NMOS transistors N11 and N12 and a switch SW. Here, the NMOS transistors N11 and N12 are connected in series between the power supply voltage terminal and the node NPOR_3 so that the gate terminal is connected to the switch SW.

An operation process of the present invention having such a configuration will be described below with reference to the operation timing diagram of FIG. 5.

First, the pull-down capacitor PD1 couples the voltage of the node NPOR_2 to the ground voltage in the T1 period before the output of the power-on reset signal POR transitions. Here, the NMOS transistor N1 maintains a floating state in an operation mode and a short state in a power down mode.

The latch unit 151 maintains the voltages of the nodes NPOR_1 and NPOR_2 at a stable voltage level. Here, the resistors R1 and R2 are resistance elements for limiting the currents of the nodes NPOR_1 and NPOR_2.

That is, when the level of the power supply voltage VDD increases due to the turn-on of the PMOS transistor P4, current inflow increases to the node NPOR_1, and the voltage level of the node NPOR_1 increases as the power supply voltage increases. When the voltage level of the node NPOR_1 rises, the NMOS transistor N4 is turned on so that the node NPOR_2 maintains a low level stably, and the node NPOR_1 maintains a high level as the power supply voltage level rises.

Next, the pull-down adjustment unit 155 stably maintains the rising voltage of the node NPOR_3 by the voltage of the node NPOR_1. That is, when there is no pull-down adjuster 155, the node NPOR_3 is in a floating state, and the voltage level of the node NPOR_3 becomes unstable. Here, the resistor R6 is a resistor element for limiting the current of the node NPOR_3. When the node NPOR_1 maintains the high level, the NMOS transistor N8 is turned on so that the node NPOR_3 maintains a stable low level.

In this case, when the voltage of the node NPOR_1 is small, the pull-down capacitor PD2 couples the node NPOR_3 to the ground voltage to reinforce the current driving capability of the pull-down adjusting unit 155.

Thereafter, the pull-up capacitor PU1 couples the node NPOR_1 to the high voltage in the power-up stage before the power-on reset signal POR transitions. Then, the pull-up current supply unit 152 maintains the node NPOR_1 at a high voltage before the power-up reset signal POR transitions according to the voltage level of the node NPOR_3. Here, the resistor R3 is a resistor element for limiting the current of the pull-up current supply unit 152.

Subsequently, the reset signal output unit 153 detects the threshold voltage of the node NPOR_1 and outputs a power-on reset signal POR. Here, the resistors R4 and R5 are resistance elements for limiting the current of the node NPOR_1. At this time, when the voltage of the node NPOR_3 reaches the threshold voltage, the pull-down adjusting unit 154 turns on the NMOS transistor N7 to transition the voltage of the node NPOR_1 from high to low.

The power-on reset signal POR of the present invention is generated by the voltage change of the node NPOR_1, and the voltage change of the node NPOR_1 is determined by the voltage of the node NPOR_3. Therefore, in the present invention, the voltage of the node NPOR_3 is stably maintained at the low level until the power supply voltage reaches a constant level for generating the power-on reset signal POR.

Accordingly, the pull-up controller 156 controls the PMOS transistor P8 to turn on after the generation of the power-on reset signal POR by using the self bias gate voltages of the PMOS transistors P9 to P12.

Therefore, after generation of the power-on reset signal POR, the voltage of NPOR_3 is raised to the power supply voltage VDD level again in the node T2 section. That is, the PMOS transistors P9 to P12 suppress the supply of current to the node NPOR_3 until a certain level is reached after the power supply voltage is applied according to the self-biased gate voltage applied through the gate terminal. The current is supplied to pull up the node NPOR_3 voltage up to the supply voltage VDD level.

That is, the voltage of the node NPOR_3 is initially kept low by the NMOS transistor N8. However, the voltage magnitude of the node NPOR_3 is determined by the current flowing into the node NPOR_3 as the power supply voltage level gradually increases, and the current flowing into the pull-up adjusting unit 156 and the reset voltage adjusting unit 157.

In addition, the reset voltage adjusting unit 157, which is a power supply voltage drop adjusting unit, drops the power supply voltage VDD to VDD-Vth using the threshold voltages Vth of the NMOS transistors N11 and N12 to supply the node NPOR_3. At this time, the reset voltage adjusting unit 157 determines the voltage level at which the power-on reset signal POR is generated by adjusting the number of NMOS transistors N11 and N12 connected in series by the switch SW.

That is, until the power supply voltage VDD reaches a predetermined level, only the current supplied by the reset voltage adjusting unit 157 is supplied to the node NPOR_3 so that the NMOS transistor N7 maintains the turn-off state. However, when the power supply voltage VDD increases to increase the current supply by the reset voltage adjusting unit 157 and the current supply by the pull-up adjusting unit 156 than the current of the node NPOR_3, the voltage of the node NPOR_3 transitions to a high level.

Accordingly, the NMOS transistor N7 is turned on and the voltage of the node NPOR_1 is pulled down to generate a power-on reset signal POR. At this time, when the node NPOR_1 is pulled down, current leakage by the NMOS transistor N8 is blocked, and current supply is started by the pull-up adjusting unit 156, so that the voltage of the node NPOR_3 is maintained at a high level more stably.

As described above, the present invention provides the following effects.

First, the present invention generates the power-on reset signal by the sensing current level rather than the conventional RC delay method to generate the power-on reset signal independent of the power-up slope.

Second, by using a high resistance element in the power-on reset circuit to limit the flow of current to reduce the current consumption during the power-on reset operation.

Third, the present invention returns to the latched state after the power-on reset operation and cuts off the current path, thereby reducing current consumption and removing glitches near the sensing voltage.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (17)

A latch unit maintaining a level of the power supply voltage for a predetermined period and outputting the same to the first node; Pull-down control means for pull-down controlling a second node according to the voltage level of the first node and pulling-down control of the first node according to the voltage level of the second node; A pull-up current supply unit supplying a pull-up current to the first node according to the voltage level of the second node; A reset voltage adjusting unit for dropping the power supply voltage to a predetermined level and outputting the voltage to the second node; A pull-up adjustment unit controlling a supply of a pull-up current according to a self-biased gate voltage to pull up the voltage level of the second node to a power supply voltage level after a power-on reset signal transition; And A reset signal output unit configured to sense the threshold voltage of the first node and output the power-on reset signal; The latch unit, the pull-down control unit, the pull-up current supply unit, and the reset signal output unit each includes a plurality of current limiting resistor elements for restricting the flow of current. Power-on reset circuit. The method of claim 1, A first pull-down capacitor configured to couple an input terminal of the latch unit to a ground voltage before the power-on reset signal transitions; A pull-up capacitor configured to couple the first node to a high voltage before the power-on reset signal transitions; And And a second pull-down capacitor configured to couple the second node to a ground voltage. The method of claim 2, wherein the first pull-down capacitor portion A first MOS transistor having a source / drain terminal connected to the input terminal and a ground voltage applied to the input terminal; And And a first MOS capacitor configured to supply a ground voltage to the input terminal. 3. The power-on reset circuit of claim 2, wherein the pull-up capacitor comprises a second MOS capacitor supplying a power supply voltage to the first node. 3. The nonvolatile ferroelectric memory of claim 2, wherein the second pull-down capacitor includes a second MOS transistor having a source / drain terminal connected to the second node and a ground voltage applied to the second node. Power-on reset circuit in RFID. The method of claim 1, wherein the latch unit A first current limiting resistor element connected to an input terminal of the power supply voltage and one end thereof; A second current limiting resistor element connected to the ground voltage terminal and one end thereof; A second MOS transistor configured to supply a voltage of the second current limiting resistor element according to the voltage level of the first node; And And a CMOS latch portion coupled between the other end of the first current limiting resistor element and the second MOS transistor to latch the level of the power supply voltage. Power-on in an RFID including a nonvolatile ferroelectric memory. Reset circuit. The method of claim 1, wherein the pull-down control means A first pull-down adjuster configured to pull-down control the second node according to the voltage level of the first node; And And a second pull-down adjuster configured to pull-down control of the first node according to the voltage level of the second node. The method of claim 7, wherein the first pull-down adjustment unit A third MOS transistor configured to supply a ground voltage according to the voltage level of the first node; And And a third current limiting resistor element coupled between the third MOS transistor and the second node. The nonvolatile ferroelectric memory of claim 7, wherein the second pull-down adjuster comprises a fourth MOS transistor connected between the first node and a ground voltage terminal and having a gate terminal connected to the second node. Power-on reset circuit in RFID. The nonvolatile ferroelectric memory of claim 1, wherein the pull-up current supply unit supplies a high voltage to the first node before the power-up reset signal transitions according to the voltage level of the second node. Power-on reset circuit in RFID. The method of claim 1 or 10, wherein the pull-up current supply unit A fourth current limiting resistor element whose one end is connected to the application terminal of the power supply voltage; And A power-on reset in an RFID including a nonvolatile ferroelectric memory, characterized in that it comprises a fifth MOS transistor connected between the fourth current limiting resistor element and the first node and having a gate terminal connected to the second node. Circuit. The method of claim 1, wherein the reset voltage adjusting unit A plurality of sixth MOS transistors connected in series between the supply terminal of the power supply voltage and the second node such that a gate terminal is commonly connected to a drain terminal; And And a switch for selectively connecting gate terminals of the plurality of sixth MOS transistors. A power-on reset circuit in an RFID including a nonvolatile ferroelectric memory. The method of claim 1, wherein the pull-up controller suppresses a current supply below the self-bias gate voltage level, and initiates the current supply above the self-bias gate voltage level to pull up the second node to the power supply voltage level. A power-on reset circuit in an RFID comprising a nonvolatile ferroelectric memory. The method of claim 1, wherein the pull-up adjustment unit A seventh MOS transistor to which the supply terminal of the power supply voltage and the source / drain terminal are connected and the self bias gate voltage is applied through a gate terminal; And An eighth MOS transistor connected between a gate terminal and a ground voltage terminal of the seventh MOS transistor, wherein a gate terminal is commonly connected with a drain terminal; And RFID including a plurality of ninth MOS transistors connected in series between the supply terminal of the power supply voltage and the second node, the gate terminals of which are commonly connected to the gate terminals of the seventh MOS transistor. Power-on reset circuit The nonvolatile ferroelectric memory of claim 1, wherein the pull-up controller controls the second node to be at a low level until the power supply voltage reaches a predetermined level for generating the power-on reset signal. Power-on reset circuit in the RFID comprising a. The method of claim 1, wherein the reset signal output unit A plurality of inverters connected in series between the first node and the output terminal of the power-on reset signal; A fifth current limiting resistor element connected between the plurality of inverters and a power supply voltage terminal; And And a sixth current limiting resistor element coupled between the plurality of inverters and a ground voltage terminal. The method of claim 16, wherein the plurality of inverters Tenth and eleventh MOS transistors connected in series between the fifth current limiting resistor element and the sixth current limiting resistor element and having a gate terminal connected to the first node; And Power in an RFID including a nonvolatile ferroelectric memory, wherein a gate terminal includes the tenth and eleventh MOS transistors in series between the fifth current limiting resistor element and the sixth current limiting resistor element; On reset circuit.

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