KR100673123B1 - Non-volatile ferroelectric memory device in rfid - Google Patents

Abstract

A non-volatile ferroelectric memory device in RFID(Radio Frequency Identification) is provided to reduce operation current in the RFID and to optimize a reference voltage by using a 2T2C reference cell array having a time interval corresponding to the time interval of a 1T1C main memory cell. A cell array unit(310) includes a plurality of cells for storing data of bit lines to a non-volatile ferroelectric capacitor. A reference cell array unit(320) includes a plurality of reference cells, which are arranged in a column direction and connected to a reference bit line and a reference bit line bar, respectively, to store difference data in the non-volatile ferroelectric capacitor. A reference switching unit(330) outputs an average voltage of the reference bit line and the reference bit line bar to a plurality of reference nodes when a reference enable signal is activated. A sense amplifier unit(340) amplifies the voltage of bit lines on the basis of the voltage of the reference nodes. A reference sense amplifier unit(350) amplifies the different data and outputs the amplified data to the reference bit line and the reference bit line bar.

Description

Non-volatile ferroelectric memory device in RFID

1 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention.

2 is a block diagram of a nonvolatile ferroelectric memory device in RFID according to the present invention;

3 is another embodiment of a nonvolatile ferroelectric memory device in RFID according to the present invention;

4 is a detailed configuration diagram illustrating the cell array unit of FIGS. 2 and 3.

5 is an operation timing diagram of the cell array unit of FIGS. 2 and 3.

6 is an operation timing diagram of the reference cell array unit of FIGS. 2 and 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device in RFID, and includes a 2T2C reference cell array having the same number of operations as a main memory cell so as to reduce the operating current in the RFID.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

On the other hand, a general radio frequency identification (RFID) device includes an analog block, a digital block, and a memory block. However, in the case of a high frequency RFID chip, the power supply amount of the antenna power is very small. At this time, when the power consumption of the RFID tag chip is large and a large current flows, the output voltage VDD of the voltage multiplier circuit, which is a voltage generator, is lowered.

Therefore, for stable operation of the RFID tag chip, the operating current of the RFID tag chip to which the above-described voltage VDD is applied should flow small. Therefore, there is a need for the present invention to reduce the consumption of current consumed in the memory block in order to reduce unnecessary power consumption in the RFID chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has an object of reducing the operating current in RFID by providing a 2T2C reference cell array having the same number of operations as the main memory cell.

A nonvolatile ferroelectric memory device in an RFID of the present invention for achieving the above object is a cell including a plurality of cells arranged in the row and column direction for storing data applied from a plurality of bit lines in a nonvolatile ferroelectric capacitor A reference cell array unit in which a plurality of reference cells connected to the array unit, the reference bit line and the reference bit line bar to store different data in the nonvolatile ferroelectric capacitor are arranged in the column direction, and the reference bits when the reference enable signal is activated. A reference switching unit for averaging the voltages of the lines and the reference bit line bars and outputting them to a plurality of reference nodes, a sense amplifier unit for amplifying voltages on the plurality of bit lines based on voltages of the plurality of reference nodes, and a reference bit line And reference bits It characterized in that it comprises a reference sense amplifier for amplifying and outputting different data in the Invar.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is an overall configuration diagram of an RFID including a nonvolatile ferroelectric memory according to the present invention. The radio frequency identification (RFID) device of the present invention generally includes an analog block 100, a digital block 200, and a non-volatile ferroelectric random access memory (FeRAM) 300.

Here, the analog block 100 may include a voltage multiplier 110, a voltage limiter 120, a modulator 130, a demodulator 140, and a power on reset; 150 and a clock generator 160.

And, the antenna 10 of the analog block 100 is a configuration for transmitting and receiving radio frequency signal RF between the external reader or writer and RFID. The voltage multiplier 110 generates a power supply voltage VDD which is a driving voltage of the RFID by the radio frequency signal RF applied from the antenna 10. The voltage limiter 120 limits the magnitude of the transmission voltage of the radio frequency signal RF applied from the antenna 10 and outputs it to the demodulator 140 and the clock generator 160.

In addition, the modulator 130 modulates the response signal RP applied from the digital block 200 and transmits it to the antenna 10. The demodulator 140 detects an operation command signal from a radio frequency signal RF applied from the antenna 10 according to the output voltages of the voltage multiplier 110 and the voltage limiter 120 and transmits the command signal DEMOD to the digital block 200. Output

The power-on reset unit 150 detects the output voltage VDD of the voltage multiplier 110 and outputs a power-on reset signal POR for controlling the reset operation to the digital block 200. The clock generator 160 supplies the clock CLK for controlling the operation of the digital block 200 to the digital block 200 according to the output voltage VDD of the voltage multiplier 110.

In addition, the above-described digital block 200 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal DEMOD from the analog block 100 to interpret the command signal and generate control signals and processing signals to generate the analog block. The response signal RP corresponding to 100 is output. The digital block 200 outputs the address ADD, the input / output data I / O, the control signal CTR, and the clock CLK to the FeRAM 300. The FeRAM 300 is a memory block that reads / writes data using a nonvolatile ferroelectric capacitor element.

FIG. 2 is a detailed circuit diagram of the FeRAM 300 of FIG. 1.

The FeRAM 300 includes a cell array unit 310, a reference cell array unit 320, a reference switch unit 330, a sense amplifier unit 340, and a reference sense amplifier unit 340.

In the cell array unit 310, a plurality of 1T1C cells C0 to Cn are arranged in the row and column directions. Each 1T1C cell C0-Cn has one switching transistor T1 and one nonvolatile ferroelectric capacitor FC1. The switching transistor T1 is connected between the nonvolatile ferroelectric capacitor FC1 and the bit line BL so that the gate terminal is connected to the plate line PL. The nonvolatile ferroelectric capacitor FC1 is connected between the switching transistor T1 and the word line WL.

In the reference cell array unit 320, a plurality of 2T2C reference cells RC are arranged in a column direction. Each 2T2C reference cell RC includes unit reference cells RC1 and RC2 to store different data. In addition, the unit reference cell RC1 includes one switching transistor T2 and one nonvolatile ferroelectric capacitor FC2.

Here, the switching transistor T2 is connected between the nonvolatile ferroelectric capacitor FC2 and the reference bit line R_BL so that the gate terminal is connected to the plate line PL. The nonvolatile ferroelectric capacitor FC2 is connected between the switching transistor T2 and the word line WL. In addition, the switching transistor T3 is connected between the nonvolatile ferroelectric capacitor FC3 and the reference bit line bar R_ / BL so that the gate terminal is connected to the plate line PL. The nonvolatile ferroelectric capacitor FC3 is connected between the switching transistor T3 and the word line WL.

In addition, the reference switch unit 330 includes a plurality of switching transistors N0 to N3. Here, each of the switching transistors N0 to N1 is connected between the node ND1 and the plurality of reference nodes REF0 to REFn so that the reference enable signal REF_EN is commonly applied through each gate terminal. Each of the switching transistors N2 and N3 is connected between the node ND1, the reference bit line R_BL, and the reference bit line bar R_ / BL so that the reference enable signal REF_EN is commonly applied through each gate terminal.

In addition, the sense amplifier unit 340 includes a plurality of sense amplifiers S / A <0> to S / A <n>. Here, each of the sense amplifiers S / A <0> to S / A <n> is connected between a plurality of cells C0 to Cn and a plurality of reference nodes REF0 to REFn corresponding thereto. In addition, the reference sense amplifier unit 350 includes a reference sense amplifier R_S / A connected between the reference bit line R_BL and the reference bit line bar R_ / BL.

3 is another embodiment of the FeRAM 300 of FIG. 1.

The embodiment of FIG. 3 further includes a load adjuster 360 compared to the configuration of FIG. 2. The load adjuster 360 includes capacitors CP1 and CP2 connected in parallel between the node ND1 and the ground voltage terminal to adjust the load applied to the node ND1.

4 is a detailed configuration diagram illustrating the cell array unit 310 and the reference cell array unit 320 of FIG. 1.

In the cell array unit 310, the bit lines BL <0> to BL <n> and the reference nodes REF0 to REFn are formed on different layers on the layout. In this case, the reference nodes REF0 to REFn are formed on the upper layers of the bit lines BL <0> to BL <n>, and the reference bit lines R_BL and the reference bit line bars R_ / BL are connected to the bit lines BL <0> to BL <n>. It is formed on the same layer.

An operation process of the present invention having such a configuration will be described with reference to the operation timing diagrams of FIGS. 5 and 6 as follows.

First, when the word line WL and the plate line PL are activated in the period t1, the charges of the unit reference cells RC1 and RC2 storing different data are output to the reference bit line R_BL and the reference bit line bar R_ / BL.

That is, when data '0' is stored in the unit reference cell RC1, data '1' is stored in the unit reference cell RC2. On the other hand, when data '0' is stored in the unit reference cell RC2, data '1' is stored in the unit reference cell RC1. Accordingly, when the reference enable signal REF_EN is activated, the switching transistors N2 and N3 are turned on so that the charges of the reference bit line R_BL and the reference bit line bar R_ / BL are averaged and output to the node ND1.

When the reference enable signal REF_EN is activated, the plurality of switching transistors N0 to N1 are turned on to apply the signal of the node ND1 to the reference nodes REF0 to REFn. At the same time, " 1 " or " 0 " data stored in the nonvolatile ferroelectric capacitor FC of the cell array unit 310 is applied to the bit line BL. Here, the sense amplifier enable signal SEN remains inactive.

Thereafter, when the sense amplifier enable signal SEN is activated and the reference enable signal REF_EN is deactivated in the period t2, the plurality of switching transistors N0 to N3 are turned off.

Accordingly, the sense amplifier 340 amplifies and outputs data of the cell array unit 310 applied from the bit line BL based on the reference voltages applied from the reference nodes REF0 to REFn. The reference sense amplifier 350 amplifies and outputs high or low data of the reference cell array unit 320 applied through the reference bit line R_BL and the reference bit line bar R_ / BL, respectively.

In this case, data may be written to the cells C0 to Cn through the sense amplifier 340, and different data may be written to the unit reference cells RC1 and RC2 through the reference sense amplifier 350.

Subsequently, the plate line PL is deactivated low in the period t3. Accordingly, data '1' or '0' stored in the sense amplifier unit 340 may be re-stored in the cells C0 to Cn, and data '1' or '0' stored in the reference sense amplifier 350 may be unit-referenced. Can be resaved in cells RC1 and RC2.

When the word line WL and the sense amplifier enable signal SEN are inactivated and the reference enable signal REF_EN is activated in the period t4, the plurality of switching transistors N0 to N3 are turned on again.

As described above, the present invention provides the following effects.

First, a 2T2C reference cell array with the same time interval as the 1T1C main memory cell is provided to reduce the operating current in the RFID and to optimize the reference voltage to the data of the main cell.

Second, the 2T2C reference cell array having the same number of operations as the 1T1C main memory cell increases the cell layout efficiency and provides the same stress degradation characteristics as the main cell.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (14)

A cell array unit including a plurality of cells arranged in row and column directions to store data applied from a plurality of bit lines in a nonvolatile ferroelectric capacitor; A reference cell array unit having a plurality of reference cells arranged in a column direction, each of which is connected to a reference bit line and a reference bit line bar and stores different data in a nonvolatile ferroelectric capacitor; A reference switching unit for averaging voltages of the reference bit line and the reference bit line bar when the reference enable signal is activated and outputting the averaged voltages to the plurality of reference nodes; A sense amplifier unit configured to amplify voltages on the plurality of bit lines based on voltages of the plurality of reference nodes; And And a reference sense amplifier unit configured to amplify and output the different data on the reference bit line and the reference bit line bar. 2. The nonvolatile ferroelectric memory device of claim 1, wherein each of the plurality of cells comprises a 1T1C structure including one switching transistor element and one nonvolatile ferroelectric capacitor. The nonvolatile ferroelectric memory device of claim 1, wherein the reference cell has a 2T2C structure including two switching transistor elements and two nonvolatile ferroelectric capacitors. The method of claim 3, wherein the reference cell A first switching transistor connected between the reference bit line and a second nonvolatile ferroelectric capacitor and having a gate terminal connected to the plate line; The second nonvolatile ferroelectric capacitor connected between the first switching transistor and a word line; A second switching transistor connected between the reference bit line bar and a third nonvolatile ferroelectric capacitor and having a gate terminal connected to the plate line; And And a third nonvolatile ferroelectric capacitor connected between the second switching transistor and a word line. The method of claim 1, wherein the reference switching unit First switching means for averaging voltages of the reference bit line and the reference bit line bar according to the reference enable signal and outputting the averaged voltages to the first node; And And second switching means for outputting a voltage of the first node to the plurality of reference nodes according to the reference enable signal. The method of claim 5, wherein the first switching means A third switching transistor connected between the reference bit line and the first node to receive the reference enable signal through a gate terminal; And And a fourth switching transistor connected between the reference bit line bar and the first node to receive the reference enable signal through a gate terminal thereof. 6. The method of claim 5, wherein the second switching means comprises a plurality of switching transistors connected in parallel between the first node and the plurality of reference nodes to which the reference enable signal is applied through a gate terminal. Nonvolatile Ferroelectric Memory Device in RFID. The nonvolatile ferroelectric memory device of claim 7, wherein the number of the plurality of switching transistors corresponds to the number of the reference nodes. The method of claim 1, wherein the sense amplifier unit And a plurality of sense amplifiers connected between the plurality of bit lines and the plurality of reference nodes, respectively. The nonvolatile ferroelectric memory device of claim 1, wherein the plurality of reference nodes and the plurality of bit lines are formed in different layers on a layout. 12. The nonvolatile ferroelectric memory device of claim 10, wherein the plurality of reference nodes are formed on the plurality of bit line upper layers. The nonvolatile ferroelectric memory device of claim 10, wherein the reference bit line and the reference bit line bar are formed on the same layer as the plurality of bit lines on a layout. The nonvolatile ferroelectric memory device of claim 1, further comprising a load adjuster configured to adjust a load of the reference switch. The nonvolatile ferroelectric memory device of claim 13, wherein the load adjuster comprises a plurality of capacitors connected in parallel between the reference switch and a ground voltage terminal.

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