KR100671521B1 - Method for fabricating array substrate of TFT-LCD - Google Patents

Abstract

The present invention discloses a method for manufacturing an array substrate of a thin film transistor liquid crystal display device. The disclosed method includes forming a gate line and a gate shield bar including a gate electrode on a glass substrate, depositing a gate insulating film covering the gate line and the gate shield bar, and depositing a-Si film and n + a on the gate insulating film. Depositing a Si film in sequence, patterning an n + a-Si film and an a-Si film to form a channel layer and an ohmic layer on the gate electrode, an Si stacked pattern on the gate shield bar, and an active line in the data line forming region, respectively And depositing a source / drain metal film covering the ohmic layer, the Si stacking pattern, and the act line, and patterning the metal film to form a data line on the active line and a source / drain electrode on the upper surface of the ohmic layer and a Si stack pattern. Forming a metal pattern on the substrate, forming a protective film on the data line, the source / drain electrodes, and the metal pattern having the steps, and etching the protective film Forming a via hole exposing the via film, depositing an ITO metal film on the protective film, patterning the photoresist film on the ITO metal film to reduce the initial coating thickness by dark erosion of the photoresist film, and the edge is self-aligned to the edge of the metal pattern. Forming a photoresist pattern and etching the ITO metal film to form a pixel electrode having a constant distance from the data line in all pixels.

Description

Method for fabricating array substrate of thin film transistor liquid crystal display device

1A to 1C are cross-sectional views illustrating processes for manufacturing an array substrate of a thin film transistor liquid crystal display according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1: glass substrate 2: gate shield bar

3: gate insulating film 4: active line

4a: silicon pattern 5: data line

5a: metal pattern 6: protective film

7: ITO metal film 7a: pixel electrode

8: photosensitive film 9: exposure mask

The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing an array substrate of a thin film transistor liquid crystal display device capable of improving display defects caused by variations in parasitic capacitance between data lines and pixel electrodes. It is about.

Liquid crystal displays have been developed in place of CRTs. In particular, a thin film transistor liquid crystal display device (hereinafter, TFT-LCD) having a thin film transistor (Thin Film Transistor) as a switching element for each pixel realizes high quality, large size, and color of a screen comparable to a CRT. It is a big hit in the notebook PC and monitor market.

Such a TFT-LCD typically has a structure in which an array substrate including a thin film transistor and a pixel electrode, and a color filter substrate provided with a color filter and a counter electrode are bonded under an intervening liquid crystal layer.

Here, the following processes are conventionally performed to manufacture the array substrate.

First, a gate line including a gate electrode is formed on a glass substrate, and then a gate insulating film is deposited on the entire surface of the substrate to cover the gate electrode and the gate line. After that, a channel layer and an ohmic layer formed of a-Si and n + a-Si are formed on the gate insulating layer on the gate electrode, and a source / drain electrode is formed on the ohmic layer to form a thin film transistor. At the same time, a data line integral with the drain electrode and orthogonal to the gate line is formed to define a unit pixel area.

Next, after depositing a protective film for protecting the thin film transistor on the entire surface of the substrate, the protective film is etched to form a via hole exposing the source electrode. Then, by forming a pixel electrode of ITO material in contact with the source electrode through the via hole on the protective film, the manufacturing of the array substrate is completed.

On the other hand, when the gate line including the gate electrode is formed, a gate shield bar is generally formed around the data line, and the gate is formed when the pixel electrode is formed through deposition and etching of an ITO metal film. The shield bar is used as an alignment mark so that the edges of the pixel electrodes are aligned thereon.

However, when driving the TFT-LCD having the above-described array substrate, parasitic capacitance is generated between the data line and the pixel electrode, which causes non-uniformity in the liquid crystal array as well as a difference in luminance between the pixels. Display defects are caused by variations in the parasitic capacitance between the pixels, such that a mur is seen on the display screen.

This problem is not a big problem in the screen display even if the parasitic capacitance between the data line and the pixel electrode is generated, but if the parasitic capacitance between the pixels is not large or not large, but if the parasitic capacitance between the pixels is large, it will seriously affect the display. do.

Accordingly, an object of the present invention is to provide a method for manufacturing a TFT-LCD which can solve a display defect caused by parasitic capacitance between a data line and a pixel electrode. .

In order to achieve the above object, the present invention, forming a gate line and a gate shield bar including a gate electrode on a glass substrate, depositing a gate insulating film covering the gate line and the gate shield bar, a on the gate insulating film Depositing a -Si film and an n + a-Si film in sequence, patterning the n + a-Si film and a-Si film, and forming a channel layer and an ohmic layer on the gate electrode, a Si stacked pattern on the gate shield bar, and a data line forming region Forming an active line on the active layer, depositing a source / drain metal film covering the ohmic layer, the Si stacking pattern, and the act line, and patterning the metal film to form a data line on the active line and a source / drain on the top of the ohmic layer. Forming a metal pattern on an electrode, a Si stacked pattern, forming a protective film on a data line, a source / drain electrode, and a metal pattern having a step, and protecting Forming a via hole exposing the source electrode by etching, depositing an ITO metal film on the protective film, patterning the photoresist film on the ITO metal film to reduce the initial coating thickness by dark erosion of the photoresist film, and the edge of the metal pattern A method of manufacturing an array substrate of a TFT-LCD, including forming a self-aligned photoresist pattern on the substrate, and etching the ITO metal film to form a pixel electrode having a constant distance from the data line in all pixels.

Here, the initial coating thickness of the photoresist film at the portion corresponding to the upper surface of the metal pattern is smaller than the thickness at which the photoresist film shrinks due to dark erosion.

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(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention, the present invention is to leave a metal film for forming a data line on the gate shield bar to make a structurally high step between the transmissive portion and the gate shield bar, thereby forming a pixel electrode Make the edge self-align to the edge of the metal pattern.

In this case, since the distance between the data line and the pixel electrode is uniform in all pixels, even if the parasitic capacitance is generated between the data line and the pixel electrode, there is no variation in the parasitic capacitance, so that display defects such as spots appearing in a specific pixel are not generated. Therefore, the screen quality of the TFT-LCD can be improved.

1A to 1C are cross-sectional views illustrating processes for manufacturing an array substrate of a TFT-LCD according to the present invention. Here, each drawing is shown only for the data line forming part including the shield bar pattern.

Referring to FIG. 1A, in a state in which a gate metal film is deposited on a glass substrate 1, the gate metal film is patterned to form several gate lines including gate electrodes, and at the same time, a gate shield near a region where a data line is to be formed. Form a bar (2). Thereafter, a gate insulating film 3 is deposited on the entire surface of the substrate to cover the gate line including the gate electrode and the gate shield bar 2.

Next, in a state in which an a-Si film n + a-Si film is sequentially deposited on the gate insulating film 3, the laminated film is patterned to form an active line 4 in the data line forming part and at the same time on the gate electrode. A channel layer and an ohmic layer are formed, and at the same time, a Si stacked pattern 4a is formed on the gate insulating film portion on the gate shield bar 2.

Then, a source / drain metal film is deposited on the substrate, and then patterned to form a data line 5 including a source / drain electrode to form a thin film transistor in a substrate location, and at the same time, the Si stacked pattern. The metal pattern 5a covering 4a is formed.

Subsequently, after forming the passivation layer 6 to protect the thin film transistor on the substrate result up to the step, the passivation layer 6 is etched to form via holes exposing the source electrode.

Then, an ITO metal film 7 is deposited as the pixel electrode material on the protective film 6 including the via hole. At this time, in relation to the Si stacked pattern 4a and the metal pattern 5a formed on the gate shield bar 2, the edge of the gate shield bar 2, that is, between the transmissive portion and the gate shield bar 2, is formed. A step is generated structurally.

Referring to FIG. 1B, a photosensitive film is coated on the ITO metal film 7. In this case, the photoresist film has the same surface step due to the step of the underlying layer, and the step corresponds to the gate shield bar 2 as well as the size corresponding to the sum of the thicknesses of the Si laminated pattern 4a and the metal pattern 5a. Has

Subsequently, the photosensitive film is exposed using an exposure mask 9 covering the transmissive portion, and then developed to form a photosensitive film pattern 8 covering only the transmissive portion. At this time, the thickness of the photoresist pattern 8 is reduced than the initial coating thickness, and the reduced degree is dark erosion (Dark Erosion), which is a characteristic that the volume of the photoresist film is reduced by a certain volume after developing the photoresist film. ) Is as much as shrinkage. For example, when the initial thickness of the photoresist film is set to be less than or equal to the dark erosion on the upper portion of the metal pattern 5a, the step of the photoresist pattern 8 obtained through exposure and development is controlled so that the edge thereof is formed at the edge of the metal pattern 5a. Self-alignment.

On the other hand, the degree of self-alignment of the photoresist pattern 8 can be adjusted not only by the coating thickness of the photoresist film but also by the degree of dark erosion of the photoresist film and the thickness of the metal pattern 5a.

Referring to FIG. 1C, the exposed ITO metal film portion is etched away using the photoresist pattern as an etch barrier, thereby forming the pixel electrode 7a.

Then, after removing the photoresist pattern, a series of known subsequent processes are performed to complete the array substrate manufacturing.

Here, the pixel electrode 7a may be formed by adjusting the initial photoresist film thickness, the gate shield bar 2 and the metal film thickness so that the photoresist film thickness on the upper portion of the metal pattern 5a is less than or equal to dark erosion. 5a) self-aligned at the edges, so that the distance between the pixel electrode 7a and the data line 5 is equally spaced at all the pixels, so that the pixel electrode 7a and the data line between the pixels (5) Poor display due to the parasitic capacitance deviation does not occur.

As described above, the present invention forms a metal pattern on the gate shield bar to form a surface step, and the pixel electrode finally formed by allowing the edge of the photoresist pattern covering the transmissive part to be self-aligned to the metal pattern edge. In all these pixels, the distance from the data line can be made uniform, and thus there can be no variation in the parasitic capacitance between the pixels, so that the screen quality of the TFT-LCD can be improved.

As mentioned above, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (3)

Forming a gate line including a gate electrode and a gate shield bar on the glass substrate; Depositing a gate insulating film covering the gate line and the gate shield bar; Sequentially depositing an a-Si film and an n + a-Si film on the gate insulating film; Patterning the n + a-Si film and the a-Si film to form a channel layer and an ohmic layer over the gate electrode, an Si stacked pattern on the gate shield bar, and an active line in a data line formation region, respectively; Depositing a source / drain metal film covering the ohmic layer, the Si stacking pattern, and the act line; Patterning the metal layer to form a metal pattern on a data line on the active line, a source / drain electrode on an upper surface of the ohmic layer, and a metal layer on the Si stacked pattern; Forming a passivation layer on the data line, the source / drain electrode and the metal pattern having a step; Etching the passivation layer to form a via hole exposing a source electrode; Depositing an ITO metal film on the protective film; Patterning the photoresist on the ITO metal film to form a photoresist pattern that is less than an initial coating thickness by the dark erosion of the photoresist and whose edge is self-aligned at the edge of the metal pattern; And And etching the ITO metal film to form pixel electrodes having a constant distance from the data line in all the pixels. 2. The fabrication of an array substrate of a thin film transistor liquid crystal display device according to claim 1, wherein an initial coating thickness of the photoresist film at a portion corresponding to the upper surface of the metal pattern is smaller than a thickness at which the photoresist film is contracted by the dark erosion. Way. delete

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