KR100670880B1 - Cold cathode type flat panel display - Google Patents

Abstract

A second interlayer insulating layer 15 is formed under the upper wiring electrode 16 serving as a feed line to the upper electrode 13 of the thin film type electron source array to prevent a short circuit failure. In addition, by limiting the electron emission portion to the second interlayer insulating layer 15, defects ubiquitous at the boundary between the electron acceleration layer 12 and the first interlayer insulating layer 14 are covered, thereby preventing the failure of dielectric breakdown over time. .

Lower electrode, upper electrode, electron acceleration layer, feed wiring, electron source array

Description

Cold Cathode Flat Panel Display {COLD CATHODE TYPE FLAT PANEL DISPLAY}

The present invention is formed of an electron acceleration layer such as a lower electrode and an upper electrode, and an insulating layer sandwiched therebetween, and is a thin film type electron that emits electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode. The present invention relates to a cold cathode flat panel display having a second substrate having a substrate in which sources are arranged in an array and a fluorescent surface in which a plurality of phosphors excited by electrons emitted from the first substrate side are arranged.

As display devices for television receivers, personal computer monitors, and other various electronic devices, so-called flat panel displays are known. Flat panel displays of this kind include a liquid crystal display, an organic electroluminescent (organic EL) display, a plasma display, or a field emission panel display (field emission display: FED).

In particular, in the field emission panel display, a cold cathode flat panel display using a thin film type electron source as the electron emission source is in the stage of practical use. The thin film type electron source is based on the three-layer thin film structure of the upper electrode, the electron acceleration layer, and the lower electrode, and applies a voltage between the upper electrode and the lower electrode to emit electrons from the surface of the upper electrode into the vacuum.

For example, metal-insulator-metal (MIM) type, metal-insulator-semiconductor (MIS) type, metal-insulator-semiconductor (MIM) type, metal-insulator-semiconductor-metal type, etc. have.

The MIM type is disclosed in, for example, Japanese Patent Laid-Open No. 7-65710. In addition, for the metal-insulator-semiconductor type, the MOS type (see J. Vac. Sci. Techonol. B11 (2) p.429-432 (1993)) and the HEED type (high for the metal-insulator-semiconductor-metal type) -efficiency-electro-emission device, see Jpn. J. Appl. Phys. vol 36 p L939, etc.), EL type (Electroluminescence, described in Application Physics, Vol. 63, No. 6, page 592, etc.), porous silicon type ( Applied Physics Vol. 66, No. 5, page 437, etc.) have been reported.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram explaining the operating principle of a thin film type electron source, taking MIM type as an example. 2 is a schematic cross section explaining the device structure of a conventional thin electron source. In Fig. 1, reference numeral 11 denotes a lower electrode, reference numeral 12 denotes an insulating layer, reference numeral 13 denotes an upper electrode, and reference numeral 20 denotes a vacuum. When the driving voltage Vd is applied between the upper electrode 13 and the lower electrode 11 to make the electric field in the insulating layer 12 about 1 to 10 MV / cm, electrons near the Fermi level in the lower electrode 11 are tunneled. It penetrates a barrier by this, and it injects into the conduction band of the insulating layer 12 and the upper electrode 13, and turns into hot electrons.

These hot electrons are scattered in the insulating layer 12 and in the upper electrode 13 to lose energy, but some hot electrons having energy above the work function φ of the upper electrode 13 are released into the vacuum 20. do.

Other thin film electron sources are somewhat different in principle, but they are common in that they emit hot electrons through the thin upper electrode 13.

Such a thin film type electron source can be used for an electron source such as an image display device because an electron beam can be generated from an arbitrary place when a plurality of upper electrodes 13 and a plurality of lower electrodes 11 are orthogonal to form a matrix. Can be. Up to now, electron emission has been observed from a metal-insulator-metal (MIM) structure having an Au-Al ₂ O ₃ -Al structure.

In general, when a thin film type electron source array having such a matrix structure is formed, as shown in FIG. 2, the electron emission unit is limited, and the concentration of the electric field on the wiring end of the lower electrode 11 and a short circuit between both electrodes are prevented. An interlayer insulating layer 14 for preventing and an upper electrode feeding wiring 15 for the purpose of feeding power to the upper electrode 13 which is thin and has high sheet resistance are formed in addition to the electron emitting portion. Reference numeral 10 is a substrate, and reference numeral 17 is a surface protective layer, reference numeral 17a is a lower surface protective film layer, and reference numeral 17b is an upper surface protective film layer.

Since the thin film type electron source array performs an image display apparatus by applying a voltage to the XY matrix of the lower electrode 11, the upper electrode 13, and the upper electrode feed wiring 16, insulation between these electrodes is important. If there is a poor insulation, the lower electrode 11 and the upper electrode 13 or the upper electrode power supply wiring 16 are electrically shorted to cause an image defect. Therefore, it is desired that the tunnel insulating film 12 serving as the electron accelerating layer and the interlayer insulating film 14 restricting the electron emission portion be defect free.

Usually, there are two types of insulation failures: time zero insulation breakdown and time-dependent insulation breakdown. Time zero dielectric breakdown is a mode in which breakdown occurs when a voltage is applied between electrodes. In the MIM type electron source, the interlayer insulating layer 14 that insulates the lower electrode 11 and the upper electrode feed wiring 16 is attached to the breakdown time. Defects appear.

On the other hand, dielectric breakdown over time is a mode in which initial breakdown does not occur when voltage is applied between electrodes, but gradually breaks down when voltage is continuously applied. In the MIM type electron source, the lower electrode 11 and the upper electrode are fed. The tunnel insulating film 12 that insulates the wiring 16 exhibits this breakdown mode.

In forming the tunnel insulating film 12 and the interlayer insulating film 14, an electrochemical film formation method called anodization has conventionally been used. This is because the uniformity of film quality and film thickness is very excellent compared to other film forming methods, and is suitable for forming a large-scale (large area) array.

However, as a problem in the case of using anodization, the following (1) and (2) are mentioned.

(1) If there is a place where current does not flow due to foreign matter or the like adhering to the surface, the failure of insulation breakdown of time zero is caused.

(2) In the MIM electron source, a thick oxide film (interlayer insulating film 14) and a thin oxide film (tunnel insulating film 12) are formed by using a method of local oxidation. In this case, transition regions having intermediate properties are interposed at both boundaries, resulting in weak spots that cause dielectric breakdown over time in the tunnel insulating film.

The above (1) and (2) cause so-called pixel defects and lower the reliability of the cold cathode flat panel display. It was a problem to solve these problems.

An object of the present invention is to provide a cold cathode flat panel display which solves the problems of the prior art, reduces the occurrence of pixel defects, and improves reliability.

<Start of invention>

In order to achieve the above object, the present invention is formed of an electron acceleration layer such as a lower electrode and an upper electrode, and an insulating layer sandwiched therebetween, and from the upper electrode side by applying a voltage between the lower electrode and the upper electrode. A cold-cathode flat panel display having a substrate formed by forming an array of thin film-type electron sources emitting electrons and a fluorescent surface,

In the thin film type electron source array, a first interlayer insulating layer for limiting an area of an electron acceleration layer and an upper electrode feeding wiring serving as a feeding line to the upper electrode are provided, and the upper electrode feeding wiring and the first interlayer insulation are provided. By forming the second interlayer insulating layer between the layers, failure of dielectric breakdown at time zero was suppressed.

In addition, the present invention avoids the occurrence of weak spots that cause the dielectric breakdown over time by forming an opening of the second interlayer insulating layer inside the electron acceleration layer region to limit the electron emission region.

The present invention is particularly effective when the first interlayer insulating layer is an anodic oxide film and the second interlayer insulating layer is formed by a deposition process. In the case where the lower electrode is Al or an Al alloy, the first interlayer insulating layer is an anodic oxide film, and the second interlayer insulating layer is an insulating material capable of selectively etching the lower electrode and the anodic oxide film. Valid.

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the operating principle of a thin film type electron source.

2 is a schematic cross-sectional view illustrating a device structure of a conventional thin electron source.

3 is a schematic cross-sectional view of a device of a thin film type electron source of a first embodiment of a cold cathode flat panel display according to the present invention;

4 is a schematic view for explaining a method for manufacturing a thin film type electron source in a first embodiment of the present invention.

FIG. 5 is a schematic view following FIG. 4 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 6 is a schematic diagram following FIG. 5 illustrating a method of manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 7 is a schematic view following FIG. 6 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 8 is a schematic view following FIG. 7 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 9 is a schematic diagram following FIG. 8 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 10 is a schematic view following FIG. 9 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 11 is a schematic view following FIG. 10 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 12 is a schematic view following FIG. 11 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

FIG. 13 is a schematic diagram following FIG. 12 illustrating a method for manufacturing a thin film type electron source in a first embodiment of the present invention. FIG.

Fig. 14 is an explanatory diagram comparing characteristics of reanode oxidation when using the structure of the first embodiment of the present invention and when using the conventional structure.

Fig. 15 is a schematic cross sectional view of a device of a thin film electron source of a second embodiment of a cold cathode flat panel display according to the present invention;

FIG. 16 is a schematic view for explaining a method for manufacturing a thin film electron source in a second embodiment of the present invention. FIG.

FIG. 17 is a schematic view following FIG. 16 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 18 is a schematic view following FIG. 17 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 19 is a schematic view following FIG. 18 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 20 is a schematic view following FIG. 19 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 21 is a schematic view following FIG. 20 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 22 is a schematic view following FIG. 21 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 23 is a schematic view following FIG. 22 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 24 is a schematic view following FIG. 23 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

FIG. 25 is a schematic view following FIG. 24 illustrating a method for manufacturing a thin film type electron source in a second embodiment of the present invention. FIG.

Fig. 26 is an explanatory diagram comparing operation life characteristics in the case of using the structure of the second embodiment of the present invention and in the case of using the structure of the first embodiment;

Fig. 27 is a schematic diagram for explaining the method for manufacturing a thin film electron source in a third embodiment of the present invention.

FIG. 28 is a schematic view following FIG. 27 illustrating a method for manufacturing a thin film type electron source in a third embodiment of the present invention. FIG.

FIG. 29 is a schematic diagram following FIG. 28 illustrating a method for manufacturing a thin film type electron source in a third embodiment of the present invention. FIG.

FIG. 30 is a schematic view following FIG. 29 illustrating a method for manufacturing a thin film type electron source in a third embodiment of the present invention. FIG.

FIG. 31 is a schematic diagram following FIG. 30 illustrating a method for manufacturing a thin film type electron source in a third embodiment of the present invention. FIG.

FIG. 32 is a schematic view following FIG. 31 illustrating a method for manufacturing a thin film type electron source in a third embodiment of the present invention. FIG.

FIG. 33 is a schematic diagram following FIG. 32 illustrating a method for manufacturing a thin film type electron source in a third embodiment of the present invention. FIG.

FIG. 34 is a schematic view following FIG. 33 illustrating a method of manufacturing a thin film type electron source in a third embodiment of the present invention. FIG.

Fig. 35 is a schematic diagram for explaining a method for manufacturing a thin film electron source in a fourth embodiment of the present invention.

FIG. 36 is a schematic view following FIG. 35 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

FIG. 37 is a schematic diagram following FIG. 36 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

FIG. 38 is a schematic diagram following FIG. 37 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

FIG. 39 is a schematic diagram following FIG. 38 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

FIG. 40 is a schematic diagram following FIG. 39 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

FIG. 41 is a schematic view following FIG. 40 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

FIG. 42 is a schematic diagram following FIG. 41 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

FIG. 43 is a schematic view following FIG. 42 illustrating a method for manufacturing a thin film type electron source in a fourth embodiment of the present invention. FIG.

Fig. 44 is a schematic diagram illustrating a structure of an electron source substrate of a cold cathode flat panel display using the thin film type electron source of the second embodiment of the present invention.

It is a schematic diagram explaining an example of the fluorescent surface board | substrate which comprises the cold cathode type flat panel display of this invention.

FIG. 46 is a schematic sectional view corresponding to a cross section A-A 'and B-B' in FIG. 45 illustrating a configuration of a cold cathode flat panel display in which the electron source substrate of FIG. 44 and the fluorescent surface substrate of FIG. 45 are bonded together.

Fig. 47 is a circuit connection diagram illustrating a drive system of a cold cathode flat panel display according to the present invention.

48 is a waveform diagram of driving voltages in the driving system of FIG. 47;

Fig. 49 is a sectional view of principal parts, schematically illustrating an electron emitting portion of an electron source substrate for explaining a fifth embodiment of a cold cathode flat panel display according to the present invention.

Fig. 50 is a schematic diagram illustrating the manufacturing method of the thin film type electron source in the fifth embodiment of the present invention.

FIG. 51 is a schematic view following FIG. 50 illustrating a method for manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

FIG. 52 is a schematic view following FIG. 51 illustrating a method of manufacturing a thin film type electron source in a fifth embodiment of the present invention.

FIG. 53 is a schematic view following FIG. 52 illustrating a method for manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

FIG. 54 is a schematic view following FIG. 53 illustrating a method of manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

FIG. 55 is a schematic view following FIG. 54 illustrating a method for manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

FIG. 56 is a schematic view following FIG. 55 illustrating a method for manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

FIG. 57 is a schematic view following FIG. 56 illustrating a method for manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

FIG. 58 is a schematic view following FIG. 57 illustrating a method for manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

FIG. 59 is a schematic view following FIG. 58 illustrating a method for manufacturing a thin film type electron source in a fifth embodiment of the present invention. FIG.

Fig. 60 is a schematic illustration of the electron source substrate of the fifth embodiment of the present invention.

FIG. 61 is a schematic explanatory diagram of a fluorescent surface substrate in combination with the electron source substrate shown in FIG. 60;

FIG. 62 is a cross-sectional view showing a configuration of a cold cathode flat panel display in which an electron source substrate shown in FIG. 60 and a fluorescent surface substrate shown in FIG. 61 are bonded together.

<Best mode for carrying out the invention>

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail according to an accompanying drawing. 3 is an essential part cross-sectional view schematically illustrating the electron emission portion of the electron source substrate of the first embodiment of the cold cathode flat panel display according to the present invention, and FIGS. 4 to 14 are manufacturing methods of the electron source substrate shown in FIG. Is an explanatory diagram.

The electron emission portion of the electron source substrate of this embodiment is composed of a MIM type electron source element. In Fig. 3, reference numeral 10 denotes an insulating substrate of which glass is preferable, reference numeral 11 denotes a lower electrode, reference numeral 12 denotes a tunnel insulating film, reference numeral 13 denotes an upper electrode, reference numeral 14 denotes a first interlayer insulating layer, and reference numeral 16 denotes an upper electrode. The feed wiring is shown. Reference numeral 17 is a surface protective layer, reference numeral 17a is a lower surface protective film layer, and reference numeral 17b is an upper surface protective film layer.                 

As shown in FIG. 3, in the MIM type electron source element of this embodiment, the upper electrode 13 is electrically connected with the tapered end part of the upper electrode feeding wiring 16. As shown in FIG. Hereinafter, the manufacturing method of the MIM type electron source element of this structure is demonstrated with reference to FIGS.

First, as shown in FIG. 4, the metal film for lower electrode 11 is formed into a film on insulating board | substrates 10, such as glass. As the material of the lower electrode 11, Al (aluminum) or Al alloy is used. Here, the Al-Nd alloy which doped 2 atomic% of Nd (neodymium) is used.

For film formation of this Al-Nd alloy, the film thickness was 300 nm using the sputtering method, for example. After the film formation, a stripe lower electrode 11 as shown in Fig. 4 is formed by a photolithography step and an etching step. For etching, wet etching is applied using, for example, a mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid as a treatment liquid.

Next, a method of forming the first interlayer insulating layer 14 and the tunnel insulating film 12 will be described with reference to FIGS. 5 and 6. First, a portion of the lower electrode 11 serving as an electron emission portion is covered with a resist film 19, and the other portion is selectively thickly anodized to be the first interlayer insulating layer 14. When the chemical conversion voltage of this anodic oxidation process is 100V, the 1st interlayer insulation layer 14 with a thickness of about 136 nm is formed.

Next, the resist film 19 is removed and the surface of the remaining lower electrode 11 is anodized. If the formation voltage at this time is, for example, 6 V, a tunnel insulating layer 12 having a thickness of about 10 nm is formed on the lower electrode 11 (see FIG. 6).                 

In FIG. 8, the upper electrode feed wiring 16 and the second interlayer insulating layer 15 are formed. As a material of the upper electrode feed wiring 16, Al or an Al alloy is preferable, and Al-Nd alloy which doped 2 atomic% of Nd is especially preferable. Here, an Al-Nd alloy was formed into a film by 500 nm thickness by the sputtering method. At this time, the temperature of the board | substrate 10 was set higher than room temperature, the particle diameter of Al alloy was enlarged, and the resistivity was further reduced.

As the material of the second interlayer insulating layer 15, an insulating film material capable of selective etching with respect to Al or its anodic oxide film is particularly preferable. For example, it is preferable to use an insulating material such as a dry etching capable of Si oxide and Si nitride using CF _4. In the dry etching method using a fluoride etching gas such as CF ₄ , Si oxide or Si nitride can be etched at a high selectivity to Al, an Al alloy of the lower electrode, and the anodized film thereof.

Here, Si oxide is used as the second interlayer insulating layer 15, and the film thickness is the driving voltage Vd (5 to 10V in this embodiment) of the thin film type electron source or the formation voltage VA of the tunnel insulating layer 12 (main In Example, it was set as sufficient film thickness (40 nm in this example: withstand voltage is about 40 V) which is not broken at 6V.

Next, as shown in FIG. 8, the upper electrode feed wiring 16 is processed into a stripe shape in a direction orthogonal to the lower electrode 11 by a photolithography process and an etching process. For wet etching, for example, a mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid is used as the treatment liquid. At this time, since the second interlayer insulating layer 15 plays the role of an etching stopper, damage to the first interlayer insulating layer 14 by the wet etching solution can be ignored.

In FIG. 9, the surface protective film 17 is formed. The surface protective film 17 is formed of the lower surface protective film 17a and the upper surface protective film 17b. For example, those commonly used as insulating films in semiconductor devices and the like can be used. That is, as the material can be used SiO, SiO _2, phosphorus acid glass, a glass flow, such as borosilicate _{glass, Si 3 N 4, Al 2} O 3, polyimide or the like.

As the film forming method, a sputtering method, a vacuum vapor deposition method, a chemical vapor deposition method, a coating method, or the like can be used. For example, sputtering or chemical vapor deposition is used for film formation such as SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, and glass or polyimide such as vacuum vapor deposition, phosphoric silicate glass or borosilicate glass is applied to film formation of SiO ₂ . Law and the like.

In this embodiment, using the multi-layered film made of SiO ₂ to Si ₃ N ₄ on the surface protective film lower layer (17a), the upper surface of the protective film (17b), and the film thickness was in each 300㎚.

The surface protective film 17 separates the upper electrode for each pixel, and serves to protect the electron source element from atmospheric pressure applied to the strut in the stage where the panel is completed.

In FIG. 10, a part of the surface protective film 17 is opened by photolithography and dry etching to open the electron emission section. As a gas of dry etching, a mixed gas of CF ₄ and O ₂ is preferable. The dry etching method using a fluoride-based etching gas such as CF ₄ etches the SiO ₂ film or Si ₃ N ₄ film of the surface protective film 17 with a high selectivity to the Al alloy of the upper electrode feed wiring 16, so that the upper electrode It is possible to process only the surface protection film 17 using the power supply wiring 16 as a stopper film.

In addition, in this embodiment, since the two films constituting the surface protective film 17 (the lower surface protective film 17a and the upper surface protective film 17b) are etched at different speeds, respectively, the interlayer insulating film lower layer 17a is etched. In response to this larger side etching, the lower surface protective film layer 17a retreats from the upper surface protective film layer 17b, and a "shade" structure is formed in this portion.

In FIG. 11, a resist pattern is given by a photolithography, and the upper electrode feed wiring 16 of the electron emission part is removed using the above-mentioned mixed aqueous solution (PAN) of phosphoric acid, acetic acid, and nitric acid. At this time, in order to achieve electrical connection with the upper electrode 13 formed later in the electron emission section, the curing temperature of the resist was lowered than usual so that the etching proceeded with peeling, and the adhesion strength was lowered.

As a result, a net inclined shape, i.e., a very gentle taper (taper angle of 10 degrees or less), was formed at the end portion of the upper electrode feed wiring 16.

In FIG. 12, SiO ₂ of the second interlayer insulating layer 15 is removed by a photolithography process and a dry etching process using a mixed gas of CF ₄ and O ₂ , and the electron emission portion is opened to surround the tunnel insulating film 12. do.

In the dry etching method using a fluoride etching gas such as CF ₄ , a tunnel insulating film 12 made of SiO ₂ of the second interlayer insulating layer 15, and an anodized film of an Al alloy, and the first interlayer insulating layer 14 are used. Since the etching is performed at a high selectivity with respect to this, damage to the tunnel insulating film 12 can be reduced.

At this time, the etching conditions were adjusted to adjust the resist mask to be etched faster than the SiO ₂ of the second interlayer insulating layer 15 to give a gentle inclined shape to the ends. Thereby, the coating | cover failure of the upper electrode in this part was prevented. The exposed tunnel insulating film 12 is subjected to anodization again to repair damage caused by processing.

Finally, as shown in FIG. 13, the upper electrode film 13 is formed to complete the electron source substrate. The upper electrode film 13 is formed by sputtering. As the upper electrode 13, each film thickness is several nm using the laminated film of Ir, Pt, Au, for example. At this time, the upper electrode 13 causes a coating failure in the above-described "shade" part and is separated for each pixel. Thereby, incidental contamination and processing damage to the upper electrode and the tunnel insulating film 12 due to photolithography or the like can be avoided.

The effect of the present embodiment can be confirmed directly by performing image display, but can also be confirmed by viewing the re-anodization characteristic described above.

Fig. 14 is an explanatory diagram comparing the characteristics of the reanode oxidation when using the structure according to the first embodiment of the present invention and using the conventional structure, and the present invention in the constant voltage application state when the chemical conversion voltage VA = 6V; (A) shows the formation current characteristic of the reanode oxidation of the structure of Example 1, and (b) shows the conversion current characteristic of the reanode oxidation of the conventional structure which does not have the 2nd interlayer insulation layer 15. FIG.

As shown in Fig. 14A, in the conventional structure without the second interlayer insulating layer 15, dielectric breakdown occurs frequently in the first interlayer insulating layer 14 during oxidation, so that an increase in the chemical current is achieved. Is observed. In contrast, in the structure of this embodiment having the second interlayer insulating layer 15, as shown in Fig. 14A, the formation current decreases monotonously with the progress of oxidation. This indicates that the structure of the present invention protects the defect even if the first interlayer insulating layer 14 has a defect and ensures sufficient insulation resistance against the formation voltage VA. This is because the possibility that the defect of the second interlayer insulating layer 15 overlaps with the defect position of the first interlayer insulating layer 14 is very rare.

In addition, in this embodiment, the tunnel insulating film 12 is formed by anodization in advance before the upper electrode feed wiring 16 is formed, and after the processing of the upper electrode feed wiring 16 or the like, the property of the tunnel insulating film 12 is reduced. Anger was done to repair the damage. On the other hand, after processing of the upper electrode feed wiring 16 etc., it is also possible to anodic-oxidize the tunnel insulation layer 12 only. In this method, since the oxidation forming the tunnel insulating film 12 is completed once, the process can be shortened.

As a result of bonding the electron source substrate and the fluorescent surface substrate having the structure of this embodiment to form a cold cathode flat panel display, a cold cathode flat panel display having reduced generation of pixel defects and improved reliability was obtained.                 

Next, a second embodiment of the present invention will be described.

Fig. 15 is a cross sectional view of principal parts schematically illustrating electron emission portions of an electron source substrate of a second embodiment of a cold cathode flat panel display according to the present invention, and Figs. 16 to 25 are manufacturing methods of the electron source substrate shown in Fig. 15. Is an explanatory diagram.

As shown in Fig. 15, the electron emission portion of the electron source substrate of the present embodiment is characterized in that the opening region of the second interlayer insulating layer 15 is formed inside the region of the tunnel insulating film 12, The other configuration is the same as that described in FIG.

With reference to FIGS. 16-25, the manufacturing method of the electron emission part which has a cross-sectional structure shown in FIG. 15 is demonstrated. The electron emission unit according to the present embodiment not only reduces the initial short circuit defect between the lower electrode and the upper electrode feed wiring due to the defect of the interlayer insulating film, but also improves the film quality of the tunnel insulating film 12, thereby preventing the dielectric breakdown over time. It has a suppressing effect.

In FIG. 16, a metal film for the lower electrode 11 is formed on an insulating substrate 10 such as glass. Al or an Al alloy is used as a constituent material of the lower electrode 11. Here, the Al-Nd alloy which doped 2 atomic% of Nd was used. For this film formation, the sputtering method was used, for example, and the film thickness was 300 nm. After the film formation, a stripe lower electrode 11 as shown in FIG. 3 is formed by a photolithography process and an etching process. Etching applies wet etching by the mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid, for example.

Next, the formation method of the protective insulating film 14 and the tunnel insulating film 12 is demonstrated using FIG. 17 and FIG. First, a portion of the lower electrode 11 serving as an electron emission portion is covered with a resist film 19, and the other portion is selectively thickly anodized to be the first interlayer insulating layer 14. When the formation voltage is 100 V, the first interlayer insulating layer 14 having a thickness of about 136 nm is formed.

Next, the resist film 19 is removed and the surface of the remaining lower electrode 11 is anodized. In this anodic oxidation, for example, when the chemical conversion voltage is 6 V, the tunnel insulating layer 12 having a thickness of about 10 nm is formed on the lower electrode 11. As the chemical solution used for the anodic oxidation here, when the non-aqueous chemical solution described in Japanese Patent Application Laid-Open No. 11-135316 is used, the film quality of the tunnel insulating film 12 can be expected to be improved.

In Japanese Unexamined Patent Publication No. 11-135316, it is disclosed that the tunnel insulating film anodized with these chemical liquids is resistant to breakdown over time.

In FIG. 19, the upper electrode feed wiring 16 and the second interlayer insulating layer 15 are formed. As a material of the upper electrode feed wiring 16, Al or an Al alloy is preferable, and Al-Nd alloy which doped 2 atomic% of Nd is especially preferable. Here, an Al-Nd alloy was formed into a film by 500 nm thickness by the sputtering method. At this time, the temperature of the board | substrate 10 was set higher than room temperature, the particle diameter of Al alloy was enlarged, and the resistivity was further reduced.

As the material of the second interlayer insulating layer 15, an insulating film material which can be selectively etched against Al or its anodization film is particularly preferable. For example, it is preferable to use wind the insulating material such as Si oxides, Si nitrides to dry etching using CF _4.

In the dry etching method using a fluoride etching gas such as CF ₄ , Si oxide or Si nitride can be etched at a high selectivity to Al, an Al alloy of the lower electrode, and the anodized film thereof.

Here, Si oxide is used as the second interlayer insulating layer 15, and the film thickness thereof is the driving voltage Vd (5-10V in this embodiment) of the thin film type electron source or the formation voltage VA of the insulating layer 12 (this embodiment). In the example, it was set to a sufficient film thickness (40 nm in this embodiment: withstand voltage is about 40 V) that is not broken at 6 V).

In FIG. 20, the upper electrode feed wiring 16 is processed into a stripe shape in a direction orthogonal to the lower electrode 11 by a photolithography process and an etching process. For wet etching, for example, a mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid is used. At this time, since the second interlayer insulating layer 15 plays the role of an etching stopper, damage to the first interlayer insulating layer 14 by the wet etching liquid can be ignored.

In FIG. 21, a surface protective film 17 is formed. The surface protective film 17 consists of the lower surface protective film 17a and the upper surface protective film 17b. For this surface protective film 17, for example, those commonly used as insulating films in semiconductor devices and the like can be used. That is, as the material can be used SiO, SiO _2, phosphorus acid glass, a glass flow, such as borosilicate _{glass, Si 3 N 4, Al 2} O 3, polyimide or the like. As the film forming method, a sputtering method, a vacuum vapor deposition method, a chemical vapor deposition method, a coating method, or the like can be used.

For example, sputtering or chemical vapor deposition is used for film formation such as SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, and glass or polyimide such as vacuum vapor deposition, phosphoric silicate glass or borosilicate glass is applied to film formation of SiO ₂ . Law and the like. In this embodiment, a multilayer film made of Si ₃ N ₄ is used as the lower surface protective film 17a and SiO ₂ is used as the upper surface protective film 17b, and the film thickness is 300 nm.

The surface protective film 17 separates the upper electrode 11 from pixel to pixel, and at the stage where the panel display is completed, the surface protection film 17 separates the electron source element from the atmospheric pressure applied to the post which defines the bonding interval between the electron source substrate and the fluorescent surface substrate. There is a role to protect.

In FIG. 22, a part of the surface protective film 17 is opened by photolithography and dry etching to open the electron emission section. As a gas of dry etching, a mixed gas of CF ₄ and O ₂ is preferable. The dry etching method using a fluoride-based etching gas such as CF ₄ etches the SiO ₂ or Si ₃ N ₄ film of the surface protective film 17 with a high selectivity to the Al alloy of the upper electrode feeding wiring 16, so that the upper electrode feeding It is possible to process only the surface protection film 17 using the wiring 16 as a stopper film. In addition, in the present embodiment, the two films constituting the surface protective film 17 (the lower surface protective film 17a and the upper surface protective film 17b) are etched at different speeds, respectively, so that the interlayer insulating film lower layer 17a is etched. ) Is subjected to larger side etching, the lower surface protective film 17a retreats than the upper surface protective film 17b, and a "shade" structure is formed in this portion.

In Fig. 23, a resist pattern is applied by photolithography, and the upper electrode feed wiring 16 of the electron emission portion is removed using the above-described mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid. At this time, in order to achieve electrical connection with the upper electrode 13 formed later in the electron emission section, the curing temperature of the resist was lowered than usual so that the etching proceeded with peeling, and the adhesion strength was lowered. As a result, a net inclined shape, i.e., a very gentle taper (taper angle of 10 degrees or less), was formed at the end portion of the upper electrode feed wiring 16.

In FIG. 24, the electron emission portion is formed to dry-etch SiO ₂ of the second interlayer insulating layer 15 by a photolithography process and a dry etching process using a mixed gas of CF ₄ and O ₂ to surround the tunnel insulating film 12. Open. In the dry etching method using a fluoride etching gas such as CF ₄ , SiO ₂ of the second interlayer insulating layer 15 is applied to the tunnel insulating film 12 made of an Al alloy anodized film and the first interlayer insulating layer 14. Since etching is performed at a high selectivity, the damage to the tunnel insulating film 12 can be reduced.

At this time, the etching conditions were adjusted to adjust the resist mask to be etched faster than the SiO ₂ of the second interlayer insulating layer 15, thereby providing a gentle inclined shape to the ends. This prevented disconnection caused by poor coating of the upper electrode at this portion. The exposed tunnel insulating film 12 is subjected to anodization again to repair damage caused by processing.

Finally, as shown in FIG. 25, the upper electrode film 13 is formed to complete the electron source substrate. The upper electrode film 13 is formed by sputtering. As the upper electrode 13, for example, a laminated film of Ir, Pt, Au is used, and each film thickness is several nm. At this time, the upper electrode 13 causes poor coating in the above-described "shade" portion, and is separated for each pixel. As a result, incidental contamination and processing damage to the upper electrode film 13 and the tunnel insulating film 12 due to photolithography or the like can be avoided.

Fig. 26 is an explanatory diagram comparing operation life characteristics in the case of using the structure of the second embodiment of the present invention and in the case of using the structure of the first embodiment. FIG. 26 is a plot of the increase in diode voltage required to flow a constant current through a diode measured with respect to operating time.

In the tunnel diode, electrons injected into the insulating film are subjected to inelastic scattering while traveling the conduction band, and part of them are trapped in the insulating film. The trapped electrons increase the thickness of the barrier to mitigate the electric field in the insulating film. Thereby, electron injection is suppressed. Therefore, in order to maintain a constant diode current, it is necessary to increase the voltage to apply. In our experience, it is known that when this voltage increase reaches 0.5V, the insulating film tends to intrinsic breakdown.

In the case of the MIM type electron emission structure described in the first embodiment of the present invention, the rise of the diode voltage reached breakdown at 0.3V at 3,000 hours and then at 10,000 hours. In contrast, in the case of the structure of the second embodiment of the present invention, it was confirmed that the voltage rise was 0.2V at the time of 20,000 hours elapsed, which did not lead to breakdown.                 

This reason is still unclear, but the present inventors consider as follows.

The difference between the first embodiment and the second embodiment lies in the manner of determining the electron emission region. In the first embodiment, the boundary is formed by the first interlayer insulating layer. In the first interlayer insulating layer, since the non-oxidized region is formed, a method of local oxidation using a resist pattern as a mask is used. In this case, oxidation is not completely inhibited at the edge of the resist pattern.

In practice, oxidation proceeds to the inner side in the transverse direction by about 1 μm. By the progress of oxidation in the lateral direction, an intermediate region in which the oxide film thickness is continuously changed from zero (or a natural oxide film) to 140 nm (100 V oxidation) is formed. In this state, the process proceeds to the next step, and when a tunnel oxide film is formed by anodic oxidation, up to a portion having a film thickness equivalent to 6 V in this intermediate region is subjected to oxidation again. This region subjected to so-called double oxidation shows intermediate properties between the tunnel oxide film and the interlayer insulating film. Compared with the normal tunnel insulating film region, it is estimated that this region contains a large number of trap ranks and defects, and when operated as a tunnel diode, deterioration with time is expected to be remarkable with respect to electron injection.

In contrast, in the second embodiment, since the intermediate region is covered with the second interlayer insulating layer, it does not contribute to the operation of the tunnel diode. This is considered to be the reason which can suppress the dielectric breakdown mode with time.

As a result of bonding the electron source substrate and the fluorescent surface substrate having the structure of this embodiment to form a cold cathode flat panel display, a cold cathode flat panel display with reduced occurrence of pixel defects and improved reliability was obtained.

Next, a third embodiment of the present invention will be described in detail with reference to Figs. This embodiment has a structure similar to that of the second embodiment in that the opening region of the second interlayer insulating layer 15 is formed inside the region of the tunnel insulating film 12. However, this embodiment is characterized by having a thin film electrode for connection instead of using a tapered bus wiring. This structure has the advantage that it is easier to cope with thickening of the bus wiring since the tapering process is unnecessary as compared with the second embodiment.

Since this embodiment is the same as FIGS. 16 to 18 for explaining the second embodiment until the tunnel insulating film 12 is formed on the electron source substrate, the description of the repetition is omitted and the description will be made from the formation of the bus electrode. .

In FIG. 27, the upper electrode feed wiring 16 and the second interlayer insulating film 15 are formed on the tunnel insulating film 12. In the present embodiment, the upper electrode feed wiring 16 has a two-layer structure of the upper electrode feed wiring lower layer 16a and the upper electrode feed wiring upper layer 16b.

As a material of the upper electrode feed wiring lower layer 16a, a high melting point metal, for example, Ti, Cr, W, etc., Mo, Nb, or a silicon compound (silicide) thereof is preferable. In particular, Cr and W are preferable because wet etching can be selectively performed with respect to the second interlayer insulating layer 15. As a material of the upper electrode feed wiring upper layer 16b, Al or an Al alloy is preferable, and Al-Nd alloy which doped 2 atomic% of Nd is especially preferable. Here, Cr and an Al-Nd alloy were formed into a film by 20 nm and 500 nm thickness by sputtering method, respectively. At this time, it is also possible to set the substrate temperature higher than room temperature to increase the particle diameter of the Al alloy to lower the resistivity.

As the second interlayer insulating layer 15, an insulating film material which can be selectively etched against Al or its anodization film is particularly preferable. For example, it is preferable to use an insulating material such as Si oxides, Si nitrides to dry etching using CF _4.

In the dry etching method using a fluoride etching gas such as CF ₄ , Si oxide or Si nitride can be etched at a high selectivity to Al, an Al alloy of the lower electrode, and the anodized film thereof.

Here, Si oxide is used as the second interlayer insulating layer 15, and the film thickness is the driving voltage Vd (5 to 10V in this embodiment) of the thin film type electron source or the formation voltage VA of the insulating layer 12 (this embodiment). 6V), the film thickness (40 nm in this example: withstand voltage of about 40 V) is not sufficient.

In FIG. 28, the upper electrode feed wirings 16a and 16b are processed into stripes in a direction orthogonal to the lower electrodes 11 by a photolithography step and an etching step. For wet etching, for example, a mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid is used for the Al alloy, and a cerium nitrate diammonium nitrate aqueous solution is used for Cr. At this time, since the second interlayer insulating layer 15 plays the role of an etching stopper, damage to the first interlayer insulating layer 14 by the wet etching liquid can be ignored.

In Fig. 29, a surface protective film is formed. As the surface protective film 17, for example, those commonly used as insulating films in semiconductor devices and the like can be used. That is, as the material of the surface protective film 17, glass such as SiO, SiO ₂ , phosphic silicate glass, borosilicate glass, Si ₃ N ₄ , Al ₂ O ₃ , polyimide, or the like can be used.

As the film forming method, a sputtering method, a vacuum vapor deposition method, a chemical vapor deposition method, a coating method, or the like can be used. For example, sputtering or chemical vapor deposition is used for film formation such as SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, and glass or polyimide such as vacuum vapor deposition, phosphoric silicate glass or borosilicate glass is applied to film formation of SiO ₂ . Law and the like.

In this embodiment, a multilayer film made of Si ₃ N ₄ is used as the lower surface protective film 17a and SiO ₂ is used as the upper surface protective film 17b, and the film thickness is 300 nm. The surface protective film 17 separates the upper electrode 13 from pixel to pixel, and at the stage where the panel display is completed, the surface protection film 17 separates the electron source element from the atmospheric pressure applied to the post which defines the bonding interval between the electron source substrate and the fluorescent surface substrate. There is a role to protect.

In FIG. 30, a part of the surface protective film 17 is opened by photolithography and dry etching to open the electron emission section. As a gas of dry etching, a mixed gas of CF ₄ and O ₂ is preferable. The dry etching method using a fluoride-based etching gas such as CF ₄ etches the SiO ₂ or Si ₃ N ₄ film of the surface protective film 17 with a high selectivity with respect to the Al alloy of the upper electrode feed wiring 16, so that the upper electrode It is possible to process only the surface protection film 17 by using the feeder wiring upper layer 16b as a stopper film.

In addition, in this embodiment, since the two films constituting the surface protective film 17 (the lower surface protective film 17a and the upper surface protective film 17b) are etched at different rates, respectively, the interlayer insulating film lower layer ( 17a) is subjected to larger side etching, and the lower surface protective film layer 17a retreats from the upper surface protective film layer 17b, and a "shade" structure is formed in this portion.

In Fig. 31, a resist pattern is applied by photolithography, and the upper electrode feed wiring upper layer 16b of the electron emission portion is removed using the above-described mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid.

Then, as shown in FIG. 32, the resist pattern is given by photolithography and the upper electrode feed wiring lower layer 16a of the electron emission part is removed using the above-mentioned cerium nitrate ammonium aqueous solution. At this time, in order to achieve electrical connection with the upper electrode 13 formed later in the electron emission section, the upper electrode feed wiring lower layer 16a is patterned so as to protrude from the upper electrode feed wiring upper layer 16b. Since the thickness of the lower layer 16a of the upper electrode feed wiring is only tens of nm, electrical connection with the upper electrode 13 can be made without causing a break in this portion.

In FIG. 33, SiO ₂ of the second interlayer insulating layer 15 is dry etched by a photolithography step and a dry etching step using a mixed gas of CF ₄ and O ₂ to form an electron emission portion inside the tunnel insulating film 12. Open.

In the dry etching method using a fluoride etching gas such as CF ₄ , SiO ₂ of the second interlayer insulating layer 15 is applied to the tunnel insulating film 12 made of an Al alloy anodized film and the first interlayer insulating layer 14. Since etching is performed at a high selectivity, the damage to the tunnel insulating film 12 can be reduced.

At this time, the etching conditions were adjusted to adjust the resist mask to be etched faster than the SiO ₂ of the second interlayer insulating layer 15, thereby providing a gentle inclined shape to the ends. Thereby, the disconnection caused by the covering failure of the upper electrode 13 in this part can be prevented. The exposed tunnel insulating film 12 is again anodized to repair damage caused by processing.

Finally, as shown in FIG. 34, the upper electrode film 13 is formed to complete the electron source substrate. The upper electrode film 13 is formed by sputtering. As the upper electrode 13, for example, a laminated film of Ir, Pt, Au is used, and each film thickness is several nm. At this time, the upper electrode 13 causes poor coating in the above-described "shade" portion, and is separated for each pixel. As a result, incidental contamination or processing damage to the upper electrode 13 or the tunnel insulating film 12 due to photolithography or the like can be avoided.

In this embodiment, it is not necessary to give the upper electrode feed wiring 16 a taper process for connection with the upper electrode 13. This means that the film thickness of the upper electrode feed wiring 16 can be set irrespective of the selectivity with the resist, and it can be said to be an element structure which is advantageous for reducing the resistance of the feed wiring 16.                 

As a result of bonding the electron source substrate and the fluorescent surface substrate having the structure of the present example to a cold cathode flat panel display, a cold cathode flat panel display was obtained in which the occurrence of pixel defects was reduced and the reliability was improved.

Next, a fourth embodiment of the present invention will be described with reference to Figs.

This embodiment is the same as the second embodiment described above in that the opening region of the second interlayer insulating layer 15 is formed inside the region of the tunnel insulating film 12. However, in the present embodiment, instead of using a thick anodic oxide film for the second interlayer insulating layer, the first interlayer insulating layer also serves as a second interlayer insulating layer. This structure has the advantage that the manufacturing process can be simplified because there is no treatment for locally thick anodic oxidation as compared with the second embodiment.

First, as shown in FIG. 35, the lower electrode wiring 11 is formed on the board | substrate 10 similarly to 2nd Example.

Next, in Fig. 36, the lower electrode wiring 11 is anodized to form a tunnel insulating film 12 on the entire surface. This formation condition is based on the conditions disclosed in the second embodiment.

In FIG. 37, the upper electrode feed wiring 16, the second interlayer insulating film lower layer 14a, and the second interlayer insulating film upper layer 14b are formed.

In this embodiment, the second interlayer insulating layer 14 has a two-layer structure. This is because the upper electrode 13 has a net inclined shape, that is, a gentle inclined shape, so that the upper electrode 13 does not cause a coating failure at the end of the second interlayer insulating layer 14 and causes disconnection. What is necessary is just to make the speed ratio of a mask material and a to-be-etched material larger than 1 for this inclined process.

Here, the inclined structure was introduced using the etching rate difference using the second interlayer insulating film upper layer 14b as a mask material. However, of course, instead of the second interlayer insulating film upper layer 14b, it is also possible to use a common resist pattern as a mask material, and to adjust the etching conditions (gas composition and the like) to achieve the same purpose.

As the second interlayer insulating layer 14, an insulating film material that can be selectively etched against Al or its anodization film is particularly preferable. For example, to use a dry etching insulating material such as Si oxides, Si nitrides capable of using CF ₄ is preferred. In the dry etching method using a fluoride etching gas such as CF ₄ , Si oxide or Si nitride can be etched at a high selectivity to Al, an Al alloy of the lower electrode, and the anodized film thereof.

Here, Si oxide is used as the second interlayer insulating layer lower layer 14a, and the film thickness is the driving voltage Vd (5 to 10V in this embodiment) of the thin film type electron source or the formation voltage VA of the insulating layer 12 (main In the embodiment, the film thickness is sufficient to prevent breakdown at 6V). In the present Example, it was set to 200 nm (withstand voltage of about 200 V). As the second interlayer insulating layer upper layer 14b, silicon nitride SiN _x is preferable. Here, SiO _x , SiN _x , and Al alloys were formed into a film by 200 nm, 20 nm, and 500 nm, respectively, by a sputtering method. In forming the Al alloy, it is also possible to set the substrate temperature higher than room temperature to increase the particle diameter of the Al alloy to lower the resistivity.

In FIG. 38, the upper electrode feeding wiring 16 is processed into a stripe shape in a direction orthogonal to the lower electrode 11 by a photolithography step and an etching step. For wet etching, for example, a mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid is used for the Al alloy. At this time, since the second interlayer insulating layer 14 plays the role of an etching stopper, damage to the lower electrode 11 by the wet etching liquid can be ignored.

In FIG. 39, a surface protective film 17 is formed. As the surface protective film 17, what is generally used as an insulating film in a semiconductor element etc. can be used, for example. That is, as the material of the surface protective film 17, it is possible to use a SiO, SiO _2, phosphorus acid such as a glass or borosilicate glass stream of _{glass, Si 3 N 4, Al 2} O 3, polyimide or the like.

As the film forming method, a sputtering method, a vacuum vapor deposition method, a chemical vapor deposition method, a coating method, or the like can be used. For example, sputtering or chemical vapor deposition is used for film formation such as SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, and glass or polyimide such as vacuum vapor deposition, phosphoric silicate glass or borosilicate glass is applied to film formation of SiO ₂ . Law and the like.

In this embodiment, a multilayer film made of Si ₃ N ₄ is used as the lower surface protective film 17a and SiO ₂ is used as the upper surface protective film 17b, and the film thickness is 300 nm. The surface protective film 17 separates the upper electrode 13 from pixel to pixel, and at the stage where the panel display is completed, the surface protection film 17 separates the electron source element from the atmospheric pressure applied to the post which defines the bonding interval between the electron source substrate and the fluorescent surface substrate. There is a role to protect.

In FIG. 40, a part of the surface protective film 17 is opened by photolithography and dry etching to open the electron emission section. As a gas of dry etching, a mixed gas of CF ₄ and O ₂ is preferable. The dry etching method using a fluoride-based etching gas such as CF ₄ etches the SiO ₂ or Si ₃ N ₄ film of the surface protective film 17 with a high selectivity with respect to the Al alloy of the upper electrode feed wiring 16, so that the upper electrode It is possible to process only the surface protection film 17 by using the feeder wiring upper layer 16b as a stopper film.

In addition, in this embodiment, since the two films constituting the surface protective film 17 (the lower surface protective film 17a and the upper surface protective film 17b) are etched at different rates, respectively, the interlayer insulating film lower layer ( 17a) is subjected to a larger side etch so that a "shade" structure is formed in this portion.

In FIG. 41, a resist pattern is applied by photolithography, and the upper electrode feed wiring upper layer 16 of the electron emission portion is removed using the above-described mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid. At this time, in order to achieve electrical connection with the upper electrode 13 formed later in the electron emission section, the curing temperature of the resist was lowered than usual so that the etching proceeded with peeling, and the adhesion strength was lowered. As a result, a net inclined shape, i.e., a very gentle taper (taper angle of 10 degrees or less), was formed at the end portion of the upper electrode feed wiring 16.

In Figure 42, the photolithography process, CF ₄ and SiN _x in the second interlayer insulating film upper layer (14b) by the called process to dry using a mixed gas of O _2, a second dry-etching the SiO _x of the interlayer insulating film lower layer (14a) To open the electron emission section. In the dry etching method using a fluoride etching gas such as CF ₄ , the second insulating interlayer 14 is etched at a high selectivity with respect to the tunnel insulating film 12 made of an Al alloy anodized film. You can reduce the damage to.

Further, under normal conditions, since the SiN _x of the second interlayer insulating film 14b is etched faster than SiO _x of the second interlayer insulating film 14a, a gentle inclined shape is provided. The exposed tunnel insulating film 12 is again anodized to repair damage caused by processing.

Finally, in FIG. 43, the upper electrode film 13 is formed to complete the electron source substrate. The upper electrode film 13 is formed by sputtering. As the upper electrode 13, for example, a laminated film of Ir, Pt, Au is used, and each film thickness is several nm. At this time, the upper electrode 13 causes poor coating in the above-mentioned "shade" portion, and is separated for each pixel. As a result, incidental contamination or processing damage to the upper electrode or the tunnel insulating film 12 due to photolithography or the like can be avoided.

In the structure of this embodiment, there is no first interlayer insulating layer made of a thick anodized film in the first to third embodiments described above. In order to reduce the anodic oxide film forming process, it can be said to be an element structure that is advantageous for the simplification of the manufacturing process.

As a result of bonding the electron source substrate and the fluorescent surface substrate having the structure of this embodiment to form a cold cathode flat panel display, a cold cathode flat panel display with reduced occurrence of pixel defects and improved reliability was obtained.

Next, another structural example of the cold cathode flat panel display according to the present invention will be described with reference to FIGS. 44 to 48.

Fig. 44 is a schematic diagram illustrating the structure of an electron source substrate of a cold cathode flat panel display using the thin film type electron source of the second embodiment of the present invention. The thin film type electron source of an electron source substrate is a MIM type electron source. The same applies to the electron source substrate having the thin film type electron source described in the second to fourth embodiments.

In Fig. 44, the same reference numerals as those in the above embodiments correspond to the same functional parts.

First, a MIM electron source is fabricated on the substrate 10 according to the method of the second embodiment. Here, the plan and the cross-sectional view of the MIM type electron source substrate of (3x3) dots will be described. In practice, however, a number of MIM type electron source matrices corresponding to the number of display dots are formed. Although not described in the first to fourth embodiments, when the MIM type electron source matrix is used in the display device, the electrode ends of the lower electrode 11 and the upper electrode feed wiring 16 are connected to the driving circuit described later. The electrode surface must be exposed for the connection.

It is a schematic diagram explaining an example of the fluorescent surface board | substrate which comprises the cold cathode flat panel display of this invention. Reference numeral 110 denotes a face plate constituting a fluorescent surface substrate, reference numeral 111 denotes a red phosphor, reference numeral 112 a green phosphor, reference numeral 113 a blue phosphor, reference numeral 114 a metal back, and reference numeral 120 a black matrix. The manufacturing method of the fluorescent surface substrate shown in FIG. 45 is demonstrated.

Translucent glass or the like is used for the face plate 110. First, the black matrix 120 is formed on the face plate 110 for the purpose of improving the contrast of the panel display. This black matrix 120 is formed as follows. The surface plate 110 is coated with a solution containing a mixture of PVA (polyvinyl alcohol) and ammonium dichromate on the surface plate 110, and irradiated with ultraviolet light in addition to the portion to form the black matrix 120, the unsensitized portion is It removes, and apply | coats the solution which melt | dissolved graphite powder there, and forms by lifting-off (peeling) PVA.

Next, the red phosphor 111 is formed. An aqueous solution obtained by mixing PVA and ammonium bichromate in red phosphor particles is applied onto the face plate 110, and irradiated with ultraviolet rays to a portion forming the red phosphor, and then the unsensed portion is removed with running water.

In this way, the red phosphor 111 is patterned. This pattern is patterned into a stripe shape as shown in FIG. Similarly, the green phosphor 112 and the blue phosphor 113 are formed.

As the phosphor, for example, Y ₂ O ₂ S: Eu (P22-R) in red, ZnS: Cu, Al (P22-G) in green, and ZnS: Ag (P22-B) in blue can be used. .

After forming three-color phosphors, the phosphors were coated to form nitrocellulose or the like to form a film, and then the Al was deposited on the entire face plate 110 to a thickness of about 75 nm. A metal bag 114 is used. This metal back 114 functions as an acceleration electrode (anode). Thereafter, the face plate 110 is heated to about 400 ° C. in the air to thermally decompose organic substances such as a film or PVA. In this manner, the fluorescent surface substrate, that is, the display side substrate, is completed.

Fig. 46 is an explanatory diagram of a configuration of a cold cathode flat panel display in which the electron source substrate shown in Fig. 44 and the fluorescent surface substrate shown in Fig. 45 are bonded, and Fig. 46 (a) corresponds to the AA ′ cross section of Fig. 45. 46B is a schematic sectional view corresponding to the cross-sectional view taken along line BB 'of FIG. 45.

The fluorescent surface substrate 110 and the electron source substrate 10 described with reference to FIG. 45 are sealed and attached to the surrounding frame 116 using an adhesive such as a frit glass 115 through the spacer 30. The height of the spacer 30 is set so that the distance between the face plate 110 of the fluorescent surface substrate and the substrate 10 of the electron source substrate is about 1 to 3 mm. The spacer 30 uses a glass plate or a ceramic plate, for example, and arranges this on the upper electrode feeding wiring 16.

By arranging the spacer 30 under the black matrix 120 having the fluorescent surface substrate 110, the spacer 3 does not inhibit the light emission of the phosphor.

Here, for the sake of explanation, the spacer 30 is placed for each dot which emits red, green, and blue light, i.e., above all the upper electrode feed wirings 16, but the spacer 30 is actually in a range that withstands mechanical strength. What is necessary is just to reduce the number (density) of and to make it stand about 1 cm apart.                 

In FIG. 46, the spacer 30 is shown as a plate-shaped spacer provided in one direction. Instead, the fluorescent surface substrate 110 and the electron source substrate 10 can be assembled using a post-shaped spacer or a lattice-shaped spacer. Can be. An exhaust pipe (not shown) is provided in the fluorescent surface substrate 110, the electron source substrate 10, or the frame 116, and the getter material is accommodated in a position avoiding the display area.

The fluorescent surface substrate 110 and the electron source substrate 10 are hermetically attached to the frame 116. It is preferable to use the frit glass 115 for this sealing adhesion. After sealing is attached, the sealed inside is evacuated to a vacuum of about 10 ⁻⁷ Torr through an exhaust pipe (not shown) and completely sealed. After the complete sealing, the getter material is activated to maintain the sealed interior at high vacuum. For example, in the case of an evaporation type getter material containing Ba as a main component, the getter material is evaporated by high frequency induction heating to form a getter film. Moreover, you may use the non-evaporable getter material which has Zr as a main component. In this manner, a cold cathode flat panel display using a MIM electron source is completed.

In the above-mentioned cold cathode flat panel display, since the distance between the face plate 110 and the board | substrate 10 is about 1-3 mm long, the acceleration voltage applied to the metal back 114 can be made into high voltage at 1-10KV. Therefore, the phosphor for cathode ray tube (CRT) as described above can be used as the phosphor.

FIG. 47 is a circuit connection diagram illustrating an example of a drive system of a cold cathode flat panel display according to the present invention, and FIG. 48 is a drive voltage waveform diagram in the drive system of FIG. 47. In FIG. 47, the lower electrode 11 is connected to the scan line driver circuit 40, and the upper electrode feed wiring 16 is connected to the signal line driver circuit 50. For simplicity of explanation, the display area of the cold cathode flat panel display is shown as (3 × 3) pixels in FIG. 47, and the scan line driver circuit 40 has the scan line feed circuits S1, S2, and S3, and the signal line driver circuit. Reference numeral 50 has signal line power supply circuits D1, D2, and D3.

Therefore, here, it is composed of (m × n) pixels with m = 3 and n = 3, and the scan line driver circuit 40 is the scan line feed circuit Sm (m = 1, 2, 3), and the signal line driver circuit 50 is It consists of a signal line power supply circuit Dn (n = 1, 2, 3).

The pixel is located at the intersection of the scan line power supply circuit Sm connected to the mth upper electrode power supply wiring 16 and the signal line power supply circuit Dn connected to the nth lower electrode 11 by coordinates (m, n). . A DC acceleration voltage of about 1 to 10 KV is always applied to the metal back 114 from the power supply circuit 60.

An example of the voltage waveform generated in the circuit of FIG. 47 will be described with reference to FIG. 48. At time t0, since neither electrode has voltage zero, electrons are not emitted and the phosphor does not emit light. At time t = t1, the voltage of -V1 is applied only to the scan line power supply circuit S1 connected to the lower electrode wiring 11, and the voltage of V2 is applied to the signal line power supply circuits D2 and D3 connected to the upper electrode power supply wiring 16. Is authorized.

In the pixel at the coordinates (1, 2) and the pixel at the coordinates (1, 3), a voltage of (V1 + V2) is applied between the lower electrode 11 and the upper electrode feeding wiring 16, so that (V1 + V2). ) Is set above the electron emission start voltage, electrons are released into the vacuum from these MIM type electron sources. The emitted electrons are accelerated by an acceleration voltage of about 1 to 10 KV applied to the metal back 114 of the fluorescent surface substrate, and then enter the phosphor, excite it, emit light, and light it.

Similarly, at time t = t2, only the scan line power supply circuit S2 connected to the lower electrode wiring 11 is energized to -V1, and the voltage line V2 is applied to the signal line power supply circuit D3 connected to the upper electrode power supply wiring 16. When applied, the pixels at coordinates (2, 3) light up.

In this way, the so-called linear sequence which selects a desired scanning line by changing the voltage signal applied to the lower electrode wiring 11 and performs gradation expression by appropriately changing the magnitude of the applied voltage V2 to the upper electrode feeding wiring 16 is performed. Image display of the driving method is enabled.

At time t = t5, an inversion voltage for applying the charge accumulated in the tunnel insulating film 12 is applied. That is, voltage V3 is applied to all the lower electrode wirings 11, and 0V is applied to all the upper electrode feeding wirings 16 at the same time.

In addition, the above-described argument can also be applied directly to other electron sources not disclosed herein, for example, thermal electron electron sources such as MIS type or ballistic conduction (BSD) type.

That is, in order to prevent the insulation failure of time zero of an upper electrode feeding wiring and a lower electrode wiring, it is effective to arrange | position the interlayer insulation film which laminated | stacked several insulating films from which film-forming methods, such as thermal oxidation and a deposition method, differ.

In addition, defining the electron emission region as the opening of the insulating film formed by the deposition method in the plurality of insulating films can avoid dangling bonds or crystal defects occurring in the semiconductor due to local oxidation. It is possible to provide a reliable flat panel display having excellent resistance to breakdown of the tunnel over time to hot electron injection.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. 49 to 62. FIG. Fig. 49 is a sectional view of principal parts, schematically illustrating an electron emitting portion of an electron source substrate for explaining a fifth embodiment of a cold cathode flat panel display according to the present invention. In the drawings, reference numeral 10 denotes a substrate, reference numeral 11 denotes a lower electrode, reference numeral 12 denotes a tunnel insulating film, reference numeral 13 denotes an upper electrode, reference numeral 14 denotes a first interlayer insulating layer, reference numeral 15 denotes a second interlayer insulating layer, Reference numeral 16 denotes an upper electrode feed wiring, reference numeral 16a denotes an upper layer of the upper electrode feed wiring, and reference numeral 16b denote an upper layer of the upper electrode feed wiring. Reference numeral 17 is a surface protective layer.

In this embodiment, the second interlayer insulating layer 15 is formed under the upper electrode feed wiring 16, and the voltage resistance is ensured even when the first interlayer insulating layer 14 is defective. . The second interlayer insulating layer 15 can prevent dielectric breakdown of the first interlayer insulating layer 14 due to the chemical conversion voltage VA applied during the anodic oxidation performed after the driving voltage Vd or the upper electrode feed wiring 16 is formed. I would have to.

The manufacturing method of the electron source substrate of this embodiment is demonstrated with reference to FIGS. 50-59, (a) is a top view, (b) is A-A 'sectional drawing of (a), (c) is B-B' sectional drawing of (a).                 

First, as shown in FIG. 50, the metal film used as the lower electrode 11 is formed on insulating substrate 10, such as glass. Al or Al alloy is used as a material of this metal film. The use of Al or an Al alloy for the metal film serving as the lower electrode 11 is because a good insulating film can be formed by anodization. Here, the Al-Nd alloy which doped 2 atomic% of Nd was used.

For this film formation, the film thickness was 300 nm using the sputtering method, for example. After the film formation, the stripe lower electrode 11 is formed by a photolithography step or an etching step. For example, a mixed aqueous solution (PAN) of phosphoric acid, acetic acid and nitric acid is used for the etching treatment.

Next, the first interlayer insulating layer 14 and the tunnel insulating layer 12 are formed. As shown in FIG. 51, the portion which becomes the electron emission part on the lower electrode 11 is covered with the resist film 19, and the other part is selectively thickly anodized to be the first interlayer insulating layer 14. . If the formation voltage at this time is 100 V, the first interlayer insulating layer 14 having a thickness of about 136 nm is formed. Next, as shown in FIG. 52, the resist film 19 is removed and the surface of the remaining lower electrode 11 is anodized. At this time, if the formation voltage is 6 V, the tunnel insulation layer 12 having a thickness of about 10 nm is formed on the lower electrode 11.

In FIG. 53, the upper electrode feed wiring lower layer 16a and the second interlayer insulating layer 15 serving as feed lines to the upper electrode 13 are formed by, for example, a sputtering method. As the second interlayer insulating layer 15, an insulating material which can be selectively etched with respect to Al or its anodization film is particularly preferable. For example, the dry etching method using a fluoride etching gas such as CF ₄ can etch Si oxide or Si nitride at a high selectivity to Al, an Al alloy of the lower electrode 11, and an anodized film thereof. .

Here, Si oxide (SiO _{2 in} this case) is used as the second interlayer insulating layer 15, and the film thickness is the driving voltage Vd (5-10V in this embodiment) of the thin film electron source or the tunnel insulating layer 12. It was set as sufficient film thickness (40 nm in this Example, withstand voltage about 40V) which is not broken by the formation voltage VA (6V in this Example).

In addition, a laminated film was used for the upper electrode feed wiring layer 16. In this embodiment, tungsten (W) was used as the material of the upper electrode feed wiring lower layer 16a, and Al-Nd alloy was used as the material of the upper electrode feed wiring upper layer 16b. The film thickness of the upper electrode feed wiring lower layer 16a is made thin so that the upper electrode 13 is not broken by the step | step of the said upper electrode feed wiring lower layer 16a, about several nm-several 10 nm, and the upper electrode feed wiring upper layer The film 16b is thickly formed at about 100 nm in order to sufficiently secure the power supply and to form a stopper film during the etching of the surface protective layer 17.

Subsequently, as shown in FIG. 54, the upper electrode feed wiring upper layer 16b and the upper electrode feed wiring lower layer 16a are processed and orthogonal to the lower electrode 11 by a photo etching process. This etching performs wet etching using the above-mentioned mixed aqueous solution (PAN) of phosphoric acid, acetic acid, and nitric acid with respect to the Al-Nd alloy of the upper electrode feed wiring upper layer 16b. In addition, wet etching in a mixed aqueous solution of ammonia and hydrogen peroxide, plasma etching using CF ₄ + O ₂ gas, or the like can be used for W of the lower layer 16a of the upper electrode feed wiring.

In plasma etching using CF ₄ + O ₂ gas, SiO ₂ of the second interlayer insulating layer 15 is also etched to some extent, but in order to achieve the object of the present invention, the second interlayer insulating layer 15 is provided with an upper electrode feed. Since it only needs to be under the wiring 16, there is no problem. 54 shows a case where plasma etching is performed.

Next, as shown in FIG. 55, the insulating film used as the surface protection layer 17 is formed into a film. As this surface protection layer 17, what is generally used as an insulating film in semiconductor elements etc. can be used, for example. That is, as the material, glass such as SiO, SiO ₂ , phosphoric silicate glass, borosilicate glass, Si ₃ N ₄ , Al ₂ O ₃ , polyimide and the like can be used.

As the film forming method, a sputtering method, a vacuum vapor deposition method, a chemical vapor deposition method, a coating method, or the like can be used. For example, sputtering or chemical vapor deposition is used for film formation such as SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, and glass or polyimide such as vacuum vapor deposition, phosphoric silicate glass or borosilicate glass is applied to film formation of SiO ₂ . Law and the like. In this embodiment, the Si ₃ N ₄ was deposited so thick 0.3~1㎛ by sputtering.

56, the area | region containing an electron emission part is opened in the surface protection layer 17 in a photoetch process. As the processing, for example, a dry etching method using CF ₄ is used. In the dry etching method using a fluoride-based etching gas such as CF ₄ , the Si ₃ N ₄ film of the surface protection layer 17 is etched at a high selectivity with respect to the Al alloy of the upper electrode feeding wiring upper layer 16b, so that the upper electrode feeding It is possible to process only the surface protection layer 17 using the upper wiring layer 16b as a stopper film.

In FIG. 57, wet etching using a mixed aqueous solution (PAN) of phosphoric acid, acetic acid, and nitric acid is performed on the upper electrode feed wiring upper layer 16b of the electron emission unit. The Si ₃ N ₄ film used for the surface protective layer 17, the W of the upper electrode feed wiring lower layer 16a and the SiO ₂ of the second interlayer insulating layer 15 are hardly etched. Therefore, only the upper electrode feed wiring upper layer 16b is etched at a high selectivity. Therefore, with respect to the surface protection layer 17, the upper electrode feed wiring upper layer 16b retreats inward, and the opening part becomes a "shade" state.

Next, as shown in Fig. 58, photo-etching process, CF ₄ + O by dry etching process using a _second gas, the upper electrode power supply wiring lower layer (16a) W and the second interlayer insulating layer 15 of SiO ₂ is dry-etched collectively and an electron emission part is opened. At this time, the W of the lower electrode feed wiring lower layer 16a is processed to extend from the upper electrode feed wiring upper layer 16b and the surface protection layer 17 to the electron emitting portion side, thereby making contact with the upper electrode 13 formed later. Can be taken.

In the dry etching method using a fluoride etching gas such as CF ₄ , a tunnel insulating layer 12 including W of the upper electrode feed wiring lower layer 16a and SiO ₂ of the surface protection layer 17 is formed of an anodized film of an Al alloy. ) And the first interlayer insulating layer 14 at high selectivity, so that damage to the tunnel insulating layer 12 can be reduced.

In addition, as in the present embodiment, dry using a fluoride etching gas such as CF ₄ is used as the second interlayer insulating layer 15 and the upper electrode feed wiring lower layer 16a in contact with the second interlayer insulating layer 15. By using SiO ₂ , Si ₃ N ₄ , W, or the like, which can be processed by etching, the second interlayer insulating layer 15 is formed self-coherently by batch etching under the upper electrode feed wiring lower layer 16a. In addition, there is an advantage that the process is simplified.

Next, the tunnel insulating layer 12 is again anodized to repair the damage. In the present embodiment, since the second interlayer insulating layer 15 is provided under the upper electrode feed wiring lower layer 16a, re-anodization can be performed normally.

In FIG. 59, after repair of damage by re-anodization of the tunnel insulation layer 12, the upper electrode 13 is finally formed. For this film formation, for example, a sputtering method is used. As the upper electrode 13, for example, a laminated film of Ir, Pt, and Au was used, and the film thickness thereof was several nm (here, 5 nm). The thin upper electrode 13 formed into a film is cut | disconnected by the "shade" shape step of the opening part of the surface protection layer 17, is isolate | separated for each electron source, and the upper electrode supply wiring upper layer 16b and the surface protection layer ( It becomes a structure which it feeds in contact with W of the upper electrode feed wiring lower layer 16a extended from 17) to the electron emission part side.

In the present embodiment, the tunnel insulation layer 12 is formed by anodization in advance before formation of the upper electrode feed wiring 16, and after the upper electrode feed wiring 16 is processed, Although the anodic oxidation was performed to repair the damage, it is also possible to anodic oxidize the tunnel insulating layer 12 only after the upper electrode feed wiring 16 and the like are processed. In this method, since the anodic oxidation is performed only once, the process can be shortened. In particular, in the structure of the present embodiment, during wet etching of the upper electrode feed wiring upper layer 16b, the upper electrode feed wiring upper layer 16b and the second interlayer insulating layer 15 double to protect the lower electrode 11. Therefore, the surface of the electrode of the lower electrode 11 is hard to be rough, and the tunnel insulating layer 12 of good quality can be formed.

Fig. 60 is a schematic explanatory diagram of an electron source substrate according to a fifth embodiment of the present invention, in which Fig. 60 (a) is a plan view, Fig. 60 (b) is a sectional view taken along line AA ′ of Fig. 60 (a), and Fig. 60 (c) shows BB 'sectional drawing of FIG. 60 (a). 61 is a schematic explanatory view of a fluorescent surface substrate combined with the electron source substrate shown in FIG. 60, in which FIG. 61 (a) is a plan view, and FIG. 61 (b) is AA 'of FIG. 61 (a). Sectional drawing, FIG. 61 (c) shows sectional drawing BB 'of FIG. 61 (a). In addition, here, only (3x3) pixel is shown for description.

The fluorescent surface substrate is produced as follows. As shown in FIG. 61, the black matrix 120 is formed in the faceplate 110 in which transparent glass is preferable for the purpose of improving the contrast of a display image. This black matrix 120 applies the solution which mixed PVA (polyvinyl alcohol) and sodium dichromate to the faceplate 110, and dries to form a PVA coating film. The PVA coating film is irradiated with ultraviolet rays to a portion other than a portion forming the black matrix 120 through a predetermined exposure mask.                 

Then, the PVA coating film of the unsensitive portion is removed to leave the PVA coating film of the photosensitive portion. The black matrix 120 is formed by applying the solution which melt | dissolved graphite powder in the said removal part of this PVA coating film, drying, and peeling (lifting off) a PVA coating film.

Next, the aqueous solution which mixed PVA and sodium dichromate with the red fluorescent substance material is apply | coated to the faceplate 110 in which the black matrix 120 was formed. A portion of the phosphor is irradiated with ultraviolet rays, the photosensitive portion is irradiated, and the unsensed portion is removed with running water to form a red phosphor 111. In this embodiment, a stripe pattern was used. Similarly, the green phosphor 112 and the blue phosphor 113 are formed.

As the red phosphor material, for _{example, Y 2 O 2 S: Eu} (P22-R), as the green phosphor material, for example, ZnS: Cu, Al (P22-G), as the blue phosphor material, e.g. , ZnS: Ag, Cl (P22-B) can be used.

Subsequently, the phosphor is coated and filmed with a film such as nitrocellulose, and then Al is deposited on the entire surface of the face plate 110 by about 75 nm to form a metal back 114. This metal back 114 functions as an acceleration electrode (anode). Thereafter, the face plate 110 is heated to about 400 ° C. in the air to thermally decompose organic substances such as a film or PVA. In this way, the fluorescent surface substrate which is a display side substrate is completed.

FIG. 62 is a cross-sectional view illustrating a configuration of a cold cathode flat panel display in which the electron source substrate shown in FIG. 60 and the fluorescent surface substrate shown in FIG. 61 are bonded together, and FIG. 62A is a cross-sectional view taken along line AA ′ of FIG. 61. And FIG. 62 (b) corresponds to the BB 'cross section of FIG.                 

The electron source substrate and the fluorescent surface substrate are bonded together with the peripheral frame 116 with an adhesive suitable for frit glass through a spacer 30 therebetween, and are sealed. The height of the spacer 30 is set such that the distance between the electron source substrate and the fluorescent surface substrate is about 1 to 3 mm. The spacer 30 stands on the surface protective layer 17 of the electron source substrate. Here, the spacer 30 is provided for each pixel of red, green, and blue for the purpose of explanation, but in practice, the installation density of the spacer may be selected within a range capable of withstanding mechanical strength, for example, at intervals of 1 cm. . Since the process after sealing is the same as that described with reference to FIG. 46 and the driving circuit system is the same as that described with reference to FIG. 47 and FIG. 48 above, repeated description is omitted.

Also in this embodiment, since a dangling bond or crystal defect occurring in a semiconductor due to local oxidation can be avoided, a reliable flat panel display excellent in resistance to breakdown of the tunnel insulating film over time to hot electron injection can be obtained. Can provide.

As described above, according to the present invention, a high reliability cold cathode which prevents initial (time zero) dielectric breakdown failure, improves the production yield, and suppresses failure breakdown over time and secures operating life. Type flat panel display can be provided.

Claims (9)

A lower electrode and an upper electrode, and an electron acceleration layer sandwiched between the lower electrode and the upper electrode, A first substrate in which an array of thin film type electron sources for emitting electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode is arranged; A second substrate having a fluorescent surface arranged with a plurality of phosphors excited by electrons emitted from the first substrate side A cold cathode flat panel display comprising The array of thin film type electron sources has a first electrode insulating wiring and an upper electrode feeding wiring serving as a feeding line to the upper electrode, And a second interlayer insulating layer between the first interlayer insulating layer and the upper electrode feeding wiring. The method of claim 1, The lower electrode is made of aluminum or aluminum alloy, The electron acceleration layer and the first interlayer insulating layer are anodized films of aluminum or aluminum alloy constituting the lower electrode, And said second interlayer insulating layer is an insulating film material for selectively etching said anodic oxide film of aluminum or aluminum alloy constituting said lower electrode and said lower electrode. The method of claim 2, An end portion of the second interlayer insulating layer surrounding the electron acceleration region is a net inclined shape, characterized in that the cold cathode flat panel display. The method of claim 2, The second interlayer insulating layer forms a multilayer structure, And a net inclined shape formed at an end portion surrounding the electron emission region by using an etching rate difference of each layer. A lower electrode and an upper electrode and an electron acceleration layer sandwiched between the lower electrode and the upper electrode, A cold-cathode flat panel display having a substrate and a fluorescent surface arranged with an array of thin film-type electron sources emitting electrons from the upper electrode side by applying a voltage between the lower electrode and the upper electrode. The thin film type electron source array has a first interlayer insulating layer and an upper electrode feed wiring serving as a feed line to the upper electrode, A second interlayer insulating layer having an opening between the first interlayer insulating layer and the upper electrode feed wiring; The area | region which performs electron emission is prescribed | regulated as the said opening area | region of the said 2nd interlayer insulation layer, The cold cathode type flat panel display characterized by the above-mentioned. The method of claim 5, The lower electrode is made of aluminum or aluminum alloy, The electron acceleration layer and the first interlayer insulating layer are anodized films of aluminum or aluminum alloy constituting the lower electrode, And said second interlayer insulating layer is an insulating film material for selectively etching said anodized film of aluminum or aluminum alloy constituting said lower electrode and said lower electrode. The method of claim 5, An end portion of the second interlayer insulating layer surrounding the electron emission region is inclined forward shape, characterized in that the cold cathode flat panel display. The method of claim 5, And the second interlayer insulating layer has a multi-layer structure, and has a net inclination shape formed at an end portion surrounding the electron emission region by using an etching rate difference of each layer. The method of claim 1, The second interlayer insulating layer forms a multilayer structure, And a net inclined shape formed at an end portion surrounding the electron emission region by using an etching rate difference of each layer.

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