KR100669793B1 - CMOS TFT and flat panel display therewith - Google Patents

Abstract

The present invention adjusts the arrangement of the active channels of the P-type thin film transistor and the N-type thin film transistor while maintaining the same channel length, so that the difference between the absolute value of the current mobility and the threshold voltage of the P-type thin film transistor and the N-type thin film transistor is substantially reduced. In addition, it is for the purpose of simple flexibility, and has an N-type active layer in which a channel is formed, wherein the N-type active layer is an N-type thin film transistor having at least one or more N-type nanoparticles, and a P-type active layer in which a channel is formed And the P-type active layer includes a P-type thin film transistor having at least one or more P-type nanoparticles, and at least channels of the N-type thin film transistor and channels of the P-type thin film transistor have different directions. A CMOS thin film transistor and a flat panel display device having the same are provided.

Description

CMOS thin film transistor and flat panel display device having same {CMOS TFT and flat panel display therewith}

1 is a plan view schematically illustrating a structure of an active matrix organic electroluminescent display device according to an exemplary embodiment of the present invention;

2 is a circuit diagram illustrating an example of a circuit of a pixel area and a circuit area of FIG. 1;

3 is a cross-sectional view of a CMOS TFT according to an embodiment of the present invention;

4 is a partial perspective view illustrating nanoparticles forming an active layer;

5A and 5B are plan views of an N-type active layer and a P-type active layer, respectively;

6 is a plan view showing a state in which nanoparticles are arranged on a substrate;

7A to 7C are cross-sectional views illustrating examples of the LITI method as a method for forming the nanofilm according to FIG. 6.

8 and 9 are cross-sectional and plan views of a donor sheet used in the method of FIGS. 7A-7C, respectively;

10A and 10B illustrate an example of a method of manufacturing the donor sheet of FIGS. 8 and 9;

11 to 15 are views showing another example of a method of manufacturing the donor sheet of FIGS. 8 and 9,

16 is a partial perspective view showing nanoparticles forming an active layer according to another embodiment of the present invention;

17 is a plan view schematically showing an active layer structure of a CMOS TFT according to another embodiment of the present invention, having the active layer according to FIG. 16;

18 is a cross-sectional view of a CMOS TFT according to another embodiment of the present invention having an active layer according to FIG. 16;

 19 is a cross-sectional view illustrating an exemplary embodiment of any one of subpixels of the pixel area of FIG. 1.

The present invention relates to a CMOS thin film transistor and a flat panel display device using the same, and more particularly, a CMOS thin film transistor having almost no difference in absolute value between current mobility and threshold voltage of a P-type thin film transistor and an N-type thin film transistor, and the same. A flat panel display device to be used.

In general, circuits using a CMOS metal thin film transistor (CMOS TFT) are used to drive an active matrix LCD, an organic EL device, an image sensor, and the like. However, in general, the absolute value of the threshold voltage of the TFT is larger than the absolute value of the threshold voltage of the MOS transistor using a single crystal semiconductor. Moreover, the absolute value of the threshold voltage of the N-type thin film transistor is very different from the absolute value of the P-type thin film transistor. For example, when the threshold voltage of the N-type thin film transistor is 2V, it is -4V in the P-type thin film transistor.

Therefore, it is not desirable to operate the circuit that the absolute value of the threshold voltage of the P-type thin film transistor and the N-type thin film transistor is very different, and in particular, it serves as a large barrier to reducing the driving voltage. For example, a P-type thin film transistor having a large absolute value of a threshold voltage generally does not operate properly at a low driving voltage.

That is, the P-type thin film transistor merely functions as a passive element such as a resistor and does not operate fast enough. To operate the P-type thin film transistor like a passive device, the driving voltage needs to be high enough.

In particular, when the gate electrode is made of a material having a work function of 5 eV or less, such as aluminum, the difference in work function between the gate electrode and the intrinsic silicon semiconductor is reduced by -0.6 eV. As a result, the threshold voltage of the P-channel TFT becomes as shifted to the negative value, and the threshold voltage of the N-channel TFT becomes close to 0V. Therefore, the N-type thin film transistor is generally made to be on-state.

In the above state, it is preferable that the absolute values of the threshold voltages of the N-type thin film transistor and the P-type thin film transistor are almost the same. In conventional single crystal semiconductor integrated circuit technology, the threshold voltage has been controlled using N or P type impurity doping at very small concentrations of up to 1018 atoms / cm 3. In other words, the threshold voltage has been controlled with an accuracy of 0.1 V or less by impurity doping at a concentration of 1015 to 1018 atoms / cm 3.

However, when using a semiconductor other than a single crystal semiconductor, no shift in the gate voltage is observed even if impurities are added at a concentration of 1018 atoms / cm 3 or less. Furthermore, when the concentration of the impurity is 1018 atoms / cm 3 or more, the threshold voltage changes rapidly, and the conductivity becomes p-type or n-type. This is because polycrystalline silicon has many defects. Since the defect concentration is 1018 atoms / cm 3, the added impurities cannot be trapped and activated by this defect. Moreover, the concentration of impurities is greater than the concentration of defects and excess impurities are activated and the conductivity type is changed to n or p type.

In order to solve this problem, in US Patent Nos. 6,492,268, 6,124,603 and 5,615,935, the channel length of the P-type thin film transistor is made smaller than that of the N-type thin film transistor by varying the channel length. However, this patent also has a problem in that the manufacturing process is complicated because the channel length must be manufactured differently.

On the other hand, the recent flat panel display devices are flexed by applying a predetermined tension to secure a sufficient viewing angle, or to be adopted in portable products such as arm bands, wallets, and notebook computers. The demand for is rising.

However, when the polycrystalline silicon TFT is formed by the conventional method, it is difficult to obtain a flexible flat panel display. That is, in order to process flexible products, acrylic, polyimide, polycarbonate, polyester, mylar and other plastic materials should be employed as materials that can bend easily to most of the components including the substrate. These plastic materials are heat resistant.

 Therefore, in particular, in order to process TFTs of flat panel displays employed in flexible products, a structure and method that can be manufactured below a temperature that the plastic material can withstand are needed.

In order to manufacture a TFT employed in such a flexible product, a method of employing a nanostructure as a channel of a TFT is disclosed recently, as can be seen in Japanese Patent 2004-048062.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and an object of the present invention is to adjust the arrangement of active channels of the P-type thin film transistor and the N-type thin film transistor while maintaining the same channel length, The present invention provides a CMOS thin film transistor having almost no difference in the absolute value of current mobility and threshold voltage of an N-type thin film transistor and a flat panel display using the same.

Another object of the present invention is to provide a flat panel display device which can simply implement flexible characteristics.

In order to achieve the above object, the present invention, the N-type active layer having a channel is formed, the N-type active layer is an N-type thin film transistor having at least one or more N-type nanoparticles, and the channel is formed P A P-type active layer, wherein the P-type active layer includes a P-type thin film transistor having at least one or more P-type nanoparticles, and at least channels of the N-type thin film transistor and channels of the P-type thin film transistor have different directions. A CMOS thin film transistor is provided.

In order to achieve the above object, the present invention also includes an N-type active layer in which a channel is formed, and the N-type active layer includes an N-type thin film transistor having at least one or more P-type nanoparticles, and a P-type active layer in which a channel is formed. Wherein, the N-type active layer comprises a P-type thin film transistor having at least one or more P-type nanoparticles, and the angle between the channel direction of the N-type active layer and the longitudinal direction of the N-type nanoparticles in the N-type thin film transistor In the P-type thin film transistor, an angle formed between the channel direction of the P-type active layer and the length direction of the P-type nanoparticles is provided.

The present invention also provides a flat panel display having such a CMOS thin film transistor.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a plan view schematically showing an active matrix organic electroluminescent display device according to a preferred embodiment of the flat panel display device according to the present invention. As shown in FIG. 1, the organic light emitting display device includes a pixel region P and a circuit region C at an edge of the pixel region P. In FIG.

The pixel area P includes a plurality of pixels, and each pixel includes a plurality of sub-pixels each having an organic EL device. In the case of a full color organic light emitting display, subpixels of red (R), green (G), and blue (B) are arranged in various patterns such as lines, mosaics, and lattices to form pixels. It may be a mono color flat panel display instead of a display.

The circuit region C connects a power source for driving the pixel region P, and controls an image signal input to the pixel region P. FIG.

FIG. 2 shows a circuit diagram of the selection driving circuit SC of a unit pixel of the pixel region P and a schematic circuit diagram of the CMOS TFT 50 of the circuit region P in the organic electroluminescent display. The circuit diagram is not necessarily limited thereto, and the present invention, which will be described below, may be applied to various circuit structures.

Referring to FIG. 2, the selection driving circuit SC in each unit pixel includes a switching TFT 10, a driving TFT 20, and a storage capacitor 30, and the CMOS TFT 50 includes an N-type TFT 51. ) And the P-type TFT 52 are combined.

The switching TFT 10 of the selection driving circuit SC is driven by a scan signal applied to the scan line Scan to transfer the data signal applied to the data line Data to the driving TFT 20 and the storage capacitor 30. It serves to convey. The driving TFT 20 determines the amount of current flowing into the EL element 40 in accordance with the data signal transmitted through the switching TFT 10. The storage capacitor 30 stores a data signal transmitted through the switching TFT 10 for one frame.

The CMOS TFT 50 may be located in the vertical driver VD, but is not limited thereto, and may be applied to various circuit units.

In the present invention, the CMOS TFT 50 may be provided as shown in FIG. 3.

First, N type and P type active layers 511 and 521 are formed on the substrate 1. In this case, the buffer layer 1a may be further provided on the substrate 1. The N-type and P-type active layers 511 and 521 are made of nanoparticles, as described below.

After the gate insulating film 12 is formed to cover the N-type and P-type active layers 511 and 521, the gate electrodes 512 and 522 and the interlayer insulating film 13 are sequentially formed, and then contact holes ( 514) 524.

Source / drain electrodes 513 and 523 are disposed on the interlayer insulating layer 13, and the source / drain electrodes 513 and 523 are N-type and P through contact holes 514 and 524, respectively. It is connected to the nanoparticles of the type active layers 511 and 521. By this formation, the CMOS TFT 50 having the N-type TFT 51 and the P-type TFT 52 according to the present invention is formed.

A planarization layer 14 is formed on the source / drain electrodes 513 and 523 as an insulator, and the planarization layer 14 is formed of an inorganic layer such as silicon nitride and / or acrylic, BCB, or polyimide. It may be formed of an organic film such as de.

On the other hand, the N-type active layer 511 of the N-type TFT 51 and the P-type active layer 521 of the P-type TFT 52 respectively form channels as described later.

According to a preferred embodiment of the present invention, the N-type active layer 511 and the P-type active layer 521 may be each provided with at least one nanoparticle, according to a preferred embodiment of the present invention, FIG. As can be seen at 4, a plurality of nanoparticles 60 can be arranged side by side, they can be arranged parallel to each other.

These nanoparticles 60 may have the form of nanotubes of nanowires, nanoribbons, nanorods, monolayer walls or multilayer walls.

4 illustrates a state in which the nanowires are arranged in one direction, the boundary 61 is provided between the nanoparticles 60 as shown in FIG. 4.

According to an exemplary embodiment of the present invention, as shown in FIGS. 5A and 5B, the nanoparticles 60 form an N-type active layer 511 and a P-type active layer 521.

5A and 5B, in the N-type active layer 511 and the P-type active layer 521, the nanoparticles 60 are arranged in a direction substantially parallel to the longitudinal direction thereof. Thus, the nanoparticles 60 The lengthwise direction of) is the direction N.

Meanwhile, in the N-type active layer 511 and the P-type active layer 521, the channels C1 and C2 correspond to regions between the source region and the drain region, and become flow paths of carriers such as electrons and holes. .

These channels C1 and C2 are formed in a predetermined direction, as shown in Figs. 5A and 5B, and the channel formation direction is the direction C. Figs. Herein, the formation direction of the channel may be regarded as a direction in which carriers move through the channel, that is, a general flow direction of carriers in the channel.

In the present invention, the N-type active layer 511 and the P-type active layer 521 are disposed to have different directions, respectively. At this time, it is sufficient that the channels C1 and C2, which are the central portions of the N-type active layer 511 and the P-type active layer 521, have such different directions, but due to the complexity of the structural design, the N-type active layer The entirety of 511 and the P-type active layer 521 have different directions. Therefore, hereinafter, the direction of the channels of the active layer of the thin film transistor will be described in the direction of the active layer, which means that only the direction of the channels is sufficient, and this fact is equally applied to all the embodiments described below.

As described above, in order to improve the electrical characteristics of the CMOS TFT, it is desirable to reduce the difference between the absolute value of the threshold voltage and the current mobility of the N-type TFT and the P-type TFT.

In the present invention, in order to reduce the difference between the absolute value of the threshold voltage and the current mobility of the N-type TFT and the P-type TFT, the electrical characteristics of the P-type thin film transistor are arranged to be excellent, and the electrical characteristics of the N-type thin film transistor are Try to be placed relatively badly.

Accordingly, the direction of the N-type active layer 511 of the N-type TFT 51 and the direction of the P-type active layer 521 of the P-type TFT 52 may be determined according to the current mobility in the channel of each active layer. have. That is, the N-type active layer 511 of the N-type TFT 51 is in a direction in which the current mobility in the channel is lowered, and the P-type active layer 521 of the P-type TFT 52 is increased in the current mobility in the channel. Direction is determined. Accordingly, in the N-type and P-type TFTs, the threshold voltage values are shifted to the left, respectively, so that the threshold voltage value of the N-type TFT 51 becomes high, and the threshold voltage values of the P-type TFT 52 also have their absolute values. It becomes small.

This difference in electrical characteristics, in particular, the difference in current mobility, can be seen in FIGS. 5A and 5B, in the direction N of the nanoparticles 60 forming the respective active layers and the respective active layers 511, 521. This can be obtained by changing the angle with the direction C which is the channel formation direction of. This will be described in more detail below.

As described above, the nanoparticles 60 forming the respective active layers are arranged to be substantially parallel to each other along a predetermined direction, for example, the N direction, and a boundary 61 is formed between each of the nanoparticles 60. .

Thus, in the active layer structure in which the nanoparticles 60 are arranged side by side in one direction, the anisotropy can be exhibited in the TFT characteristics according to the direction of the channel of the active layer. That is, the current mobility in the channel varies depending on which direction the channel of the active layer is formed in the arrangement of the nanoparticles as described above.

The nanoparticles 60 are themselves provided with a semiconductor material, thereby becoming a layer through which a carrier can move. However, the boundary 61 between the nanoparticles 60 serves as a resistance component to the movement of the carrier in the channel.

Thus, how much of the boundary 61 between the nanoparticles 60 is in the channel and at what angle to the carrier's path of travel may affect the current mobility.

That is, when the channel direction of the active layer is approximately 0 ° with the direction in which the nanoparticles 60 are aligned, for example, the length direction of the nanoparticles 60, the channel direction has a large number of boundaries 61. When the carrier is moved in parallel with the carrier, the boundary 61 which is a resistance component to the carrier's movement is reduced, resulting in a large current mobility.

On the contrary, when the channel direction of the active layer is approximately 90 ° with the longitudinal direction of the nanoparticles 60, the channel direction is disposed substantially perpendicular to a large number of boundaries 61 so that when the carrier moves, The boundaries 61, which are resistance components to the movement of the carriers, are lessened, resulting in less current mobility.

In other words, how much the boundary of the nanoparticles acting as a resistance component in the direction of movement of the carrier can be seen as a difference in the current mobility.

Therefore, as the angle of the alignment direction of the nanoparticles increases with respect to the channel direction of the active layer, the current mobility increases, and the current mobility decreases as the angle of the alignment direction of the nanoparticles decreases with respect to the channel direction of the active layer. Means that.

Therefore, the angle formed by the longitudinal direction of the nanoparticles forming the channel with respect to the channel direction of the N-type TFT, which should lower the electrical characteristics, forms the channel with respect to the channel direction of the P-type TFT, which should increase the electrical characteristics. It is preferable that the length of the nanoparticles be greater than the angle formed.

At this time, since the nanoparticles may not all be arranged in a straight line, and some may be formed in a slightly oblique direction, as shown in FIG. 5A, the N-type active layer 511 of the N-type TFT is located in the channel direction C thereof. It is preferable that the angle formed by the longitudinal direction N of the nanoparticles 60 is 45 ° to 135 °. More preferably, the N-type TFT preferably has an angle formed by the longitudinal direction N of the nanoparticles 60 with respect to the channel direction C of approximately 90 °.

As shown in FIG. 5B, the P-type TFT preferably has an angle formed by the longitudinal direction N of the nanoparticles 60 with respect to the channel direction C of the P-type active layer 521 at -45 ° to 45 °. More preferably, it is about 0 degrees.

5A and 5B described above conceptually show a relationship between a channel and nanoparticles constituting the active layer, and are not necessarily designed at the angles described above. However, in the case of the N-type active layer 511 of the N-type TFT, it is sufficient that the angle formed between the direction N and the direction C is larger than that of the P-type TFT.

As described above, when the active layers of the N-type TFT and the P-type TFT are constituted, even if the lengths of the channels C1 and C2 are the same, desired electrical characteristics can be obtained.

The N-type active layer 511 and the P-type active layer 521 arrange the nanoparticles 60 on the substrate 1 in substantially the same direction as shown in FIG. 6, and then the N-type active layer 511 at each subpixel. And patterning the P-type active layer 521 to have the arrangement as shown in FIG. At this time, the substrate 1 is preferably formed of a flexible material, acrylic, polyimide, polycarbonate, polyester, mylar and other plastic materials may be used, thin glass, surface-insulated Metal materials can also be used.

In this case, as described above, the nanoparticles may have the form of nanowires of nanowires, nanoribbons, nanorods, monolayer walls, or multilayer walls.

As examples of the method of manufacturing such nanoparticles, there may be further methods as follows.

(a) P-type Si nanowires

P-type Si nanowires with a thickness of 20-40 nm were synthesized by thermal evaporation of SiH4 and B2H6 using a commercially available mono-dispersed gold colloid particle (British Biocell International Ltd) as a catalyst. Lose. The temperature is then used between 420-480 ° C and the reactor is controlled to allow computer-controlled growth in an 8-inch tube furnace. When the total pressure is 30 torr, the silane partial pressure is about 2 torr and the reaction time is 40 minutes. The ratio of SiH4 and B2H6 is adjusted to 6400: 1 in consideration of the doping level. At this time, the doping concentration of the nanowire is estimated to be about ~ 4x10E + 17 cm-3. The higher the doping level, the lower the contact resistance is without the high temperature annealing process.

(b) N-type Si nanowires

N-type Si nanowires are synthesized by laser-assisted catalytic growth (LCG). In brief, a method of ablation of a gold target is adopted using a laser beam of an Nd: YAG laser (532 nm; 8 ns pulse width, 300 mJ / pulse, 10 Hz). At this time, the gold nanocluster catalyst particles generated are reacted with SiH4 gas in the reaction vessel to grow into Si nanowires. In the case of doping, Au-P target (99.5: 0.5 wt%, Alfa Aesar) and supplemental red phosphorus (99% Alfa Aesar) are formed at the gas inlet of the reaction vessel.

(c) N-type GaN nanowires

Ammonia gas (99.99%, Matheson), gallium metal (99.9999%, Alfa Aesar) and magnesium nitride (Mg3N2, 99.6%, Alfa Aesar) are used as sources of N, Ga, and Mg, respectively. catalyzed CVD). The substrate used at this time is preferably c-plane sapphire (c-plane sapphire). Mg3N2 thermally decomposes to form MgN2 (s) = 3Mg (g) + N2 (g), producing Mg dopants and placing them upstream of the Ga-source. GaN nanowires are formed at a temperature of 950 ° C., and nickel is used as a catalyst. Most of them have a distribution of 10 ~ 40 um.

(d) N-type CdS Nano Ribbon

CdS nanoribbons (nano-ribbon) are synthesized by the vacuum capour transport (vacuum capour transport) method. In particular, place a small amount of CdS powder (~ 100mg) on one end of the tube and seal it. While heating the tube to keep the temperature of the CdS powder at 900C, keep the other end lower than 50C. Within two hours, most of the CdS will migrate to the cold side and stick to the tube wall. The materials obtained in this way are predominantly nanoribbons with a thickness between 30-150 nm, with a width of 0.5-5 um and a length of 10-200 um.

(e) Ge nanowires

In a 2.5 cm diameter furnace reactor (total pressure = 1 atm), H2 was flowed at a flow rate of 100 sccm while maintaining a flow rate of GeH4 (10% in He) at 10 sccm (standard cubic centimeters) at 275C. Obtained by CVD for a minute. The reaction substrate is a substrate in which Au nanocrystals (average 20 nm diameter) are evenly dispersed on the surface of SiO 2 substrate.

(f) InP nanowires

InP nanowires are formed by LCG method. The LCG target is generally composed of 94% InP, 5% Au as catalyst, 1% Te or Zn as doping element. The furnace temperature is maintained at (intermediate) 800C during growth and the target is located at the upstream end rather than in the middle of the furnace. The laser condition irradiates the pulse of an Nd-YAG laser (wavelength 1064 nm) for 10 minutes, at which time the nanowires are captured downstream of the cold short side of the furnace.

(g) ZnO nanorods

ZnO nanorods are approximately 29.5 g (0.13 mol) of zinc acetate dihydrate (ZnOCOCH3-2H2O) dissolved in 125 mL of methanol at 60C and then 14.8g (0.23 mol) in 65 mL of methanol. Is prepared by adding a solution of potassium hydroxide (KOH). The reaction mixture is stirred for several days at 60C. If nanorods precipitate within a few days, the precipitates are washed with methanol and centrifuged at 5500 rpm for 30 minutes. The obtained nanoparticles are diluted with a solvent of ethylene glycol / water 2: 1 to form a solution. When aged for 3 days, nanorods of 15-30 nm in diameter and 200-300 nm in length can be obtained. Alternatively, nanowires can be obtained using the CVD method.

These nanoparticles 60 may be formed on the substrate 1 by various methods.

For example, there is a laser induced thermal imaging method (hereinafter referred to as "LITI method").

7A to 7C show a method of forming nanoparticles 60 on the substrate 1 by the LITI method, and FIG. 8 shows a cross section of a donor sheet at this time, and FIG. 9 shows the plane of the donor sheet.

First, in the present invention, a method of forming active layers having nanoparticles according to the LITI method uses a donor sheet 70 as shown in FIGS. 8 and 9.

The donor sheet 70 forms the transfer layer 72 by arranging the nanowires 60 in the film 71 in parallel to the longitudinal direction thereof.

The film 71 includes a base film 73 serving as a substrate and a light to heat conversion layer (LTHC layer) 74. The base film 73 may be a polyolefin resin. In addition, the light-to-heat conversion layer 74 may be coated on the base film 73 by stirring carbon in acryl, but is not necessarily limited thereto, and converts the light of the laser into heat to heat the transfer layer 72. May be applied to transfer the transfer layer 340 or cause a laser ablation phenomenon.

As shown in FIG. 9, the donor sheet 70 has nanowires 60 aligned in one direction.

As shown in FIG. 7A, the donor sheet 70 is seated on the substrate 1 on which the buffer layer 1a is formed, and as shown in FIG. 7B, the donor sheet 70 is laminated and temporarily bonded to each other. In this state, when the laser beam is irradiated to a predetermined site where the pattern is to be formed, and the donor sheet 70 and the substrate 1 are separated, as shown in FIG. 7C, the nanoparticles 60 are formed on the substrate 1. Is formed.

The donor sheet 70 in which the nanowires 60 are aligned in one direction may be manufactured by various methods. 10A and 10B illustrate an example.

First, as shown in FIG. 10A, a plurality of nanowires 60 are mixed in a water tank 80 in which a solution 81 such as water is stored. At this time, the nanowires 60 may be the above-described P-type nanowires or N-type nanowires, which are arranged in an irregular direction while floating on the solution 81.

Then, when the nanowires 60 on the surface of the solution 81 are pushed to one side using the alignment bar 82, the nanowires 60 are pushed to the alignment bar 82 to be concentrated to one side. In the case of a conventional nanowire, since its diameter or thickness is about 30 nm and the length is 40-50 micrometers, the aspect ratio is very large. Therefore, the nanowires 60 that are concentrated on one side are aligned in one direction, and the alignment direction is parallel to the longitudinal direction of the nanowires 60.

The water tank 80 is provided with a plurality of rollers 83, and the rollers 83 allow the film 71 to penetrate the water tank 80. In this case, as shown in FIG. 8, the film 71 has a light-heat conversion layer 74 formed on the base film 73 so that the nanowires 60 are bonded to the light-heat conversion layer 74. The light-heat conversion layer 74 passes through the water tank 80 so as to be in the direction of the nanowire 60.

When the nano wires 60 are bonded to the light-heat conversion layer 74 by passing through the water tank 80, the nano wires 60 are densely arranged on one side of the water tank 80, so that the nano wires 60 are aligned in one direction. do. The nanowires 60 may be aligned as they are bonded to the light-heat conversion layer 74 of the film 71. When the film 71 in which the nanowires 60 are aligned is dried and cut into a predetermined length, as shown in FIG. 9, the donor sheet 70 in which the nanowires 60 are aligned in one direction may be obtained.

In the method of forming the donor sheet 70, since the film 71 is continuously supplied in an inline shape, a roll-to-roll method is possible, and thus, a large number of donor sheets 70 can be continuously formed. do. Therefore, productivity can be further increased.

The donor sheet 70 may be manufactured by the method shown in FIGS. 11 to 15. This will be described in more detail as follows.

First, the first fiber and the second fiber are formed of a polymeric material. As shown in FIGS. 12 and 13, the first fiber 63 may be either a weft or a warp yarn when forming a woven fabric, and may be made of only a polymer material, and may not include nanoparticles 60. The second fiber 64 is a warp or weft that crosses the first fiber 63 at approximately right angles, and as shown in FIG. 14, the plurality of nanoparticles 60 are substantially parallel to each other. Are arranged.

The first fibers 63 and the second fibers 64 may be manufactured using an electrospinning method as shown in FIG. 11, but are not necessarily limited thereto, and may be manufactured by various methods. Can be. Hereinafter, the manufacturing method of the 1st fiber 63 and the 2nd fiber 64 using the electro spinning method is demonstrated in more detail.

The electrospinning apparatus 90 as shown in FIG. 11 includes an injector 91 having a nozzle 411, a power supply 95 for applying high frequency power to the injector 91, and an injection from the nozzle 91. And a collector 94 for forming nano-sized fibers with the polymer solution.

A predetermined polymer solution 93 is injected into the injector 91, and the polymer solution 93 is injected into the collector 94 which rotates while applying a high frequency power to the polymer solution 93. Then, the collector 94 is stretched and wound.

The polymer solution 93 is a polymer solution in which nanoparticles are not mixed when the first fibers 63 are formed, and a polymer solution in which nanoparticles are mixed when the second fibers 64 is formed. use. The method for producing nanoparticles is as described above.

When the second fiber 64 is formed of the polymer solution including the nanoparticles, the nanoparticles 60 included in the second fiber 64 may be formed of the second fiber 64, as shown in FIG. 14. Aligned in the stretching direction. Therefore, the nanoparticles 60 arranged in parallel with each other can be obtained.

Next, the woven fabric 62 is formed such that the first fiber 63 not including the nanoparticles and the second fiber 64 including the nanoparticles cross each other as shown in FIG. 12 or FIG. 13. Since the woven fabric 62 contains nanoparticles only in the second fiber 64, the nanoparticles are arranged in parallel to the direction in which the second fiber 64 is arranged.

Therefore, as shown in FIG. 15, when the woven fabric 62 is laminated on the film 71 in which the light-heat conversion layer 74 is formed, as shown in FIG. 9, the nanoparticles 60 are separated from each other. The donor sheet 70 arrange | positioned substantially parallel can be obtained. At the time of laminating, the woven fabric 62 proceeds in a state of being in close contact with the light-heat conversion layer 74 of the film 71.

In the method of forming the donor sheet 70, since the woven fabric 62 is manufactured in a roll shape, many donor sheets 70 may be continuously formed using the woven fabric 62, and thus productivity may be further increased.

On the other hand, the woven fabric 62 may be directly laminated on the substrate, without directly making the donor sheet 70, to directly coat the nanoparticles 60 on the substrate.

Although the above has described the laser transfer method as an example, the present invention is not necessarily limited thereto, and the transfer layer of the donor sheet may be transferred by an external pressure rather than a laser. In this case, the general transfer method can be applied as it is.

On the other hand, according to the laser transfer method as described above, as shown in Figure 6, without having to form the nanoparticles 60 over the entire area on the substrate 1, using the mask directly to the nanoparticles as shown in Figure 1 The active layer pattern provided with 60 can be formed.

That is, as described above, after the donor sheet 70 as shown in Fig. 9 is aligned on the substrate, a mask having an opening having a pattern as shown in Fig. 1 is prepared, and the laser transfer is performed through the mask. The active layer pattern as shown in FIG. 1 can be obtained immediately.

On the other hand, the active layer pattern made of nanoparticles is not necessarily limited to the above.

For example, as shown in FIG. 16, nanoparticle layers 60p and 60n are formed to have different arrangements of nanoparticles 60, and through this, as shown in FIG. 17, the N-type active layer 511 and the P-type The active layer 521 may be patterned to have the same direction.

Referring to FIG. 16, the P-type nanoparticle layer 60p is formed by arranging the nanoparticles 60 in one direction, and an insulating film 65 is formed to cover the N-type nanoparticles again on the insulating film 65. The particle layer 60n is arranged such that the nanoparticles 60 are orthogonal to the nanoparticles 60 of the P-type nanoparticle layer 60p.

After arranging the nanoparticle layers, all active layers are patterned to have the same direction as shown in FIG. 17.

Then, as shown in FIG. 18, by controlling the nanoparticle layers to which the source / drain electrodes of the N-type TFT 51 and the P-type TFT 52 are connected, the above-described effect can be obtained. In this case, all of the N-type active layer 511 and the P-type active layers 521 have a P-type nanoparticle layer 60p and an N-type nanoparticle layer 60n.

That is, as shown in FIG. 18, the N-type TFT 51 includes an N-type active layer 511 having both a P-type nanoparticle layer 60p and an N-type nanoparticle layer 60n. In this case, the contact hole 514 is formed to only contact the N-type nanoparticle layer 60n so that the source / drain electrode 513 contacts the N-type nanoparticle layer 60n. In this case, the directions of the nanoparticles of the N-type nanoparticle layer 60n and the channel direction of the N-type active layer 511 become substantially parallel.

The P-type active layer 521 of the P-type TFT 52 also has both a P-type nanoparticle layer 60p and an N-type nanoparticle layer 60n. At this time, the contact hole 524 is formed to contact the P-type nanoparticle layer 60p so that the source / drain electrode 523 is in contact with the P-type nanoparticle layer 60p, so that the P-type nanoparticle layer 60p The direction of the nanoparticles and the channel direction in the P-type active layer 521 are approximately perpendicular.

Accordingly, it is possible to obtain all the characteristics of the CMOS TFT of the present invention described above.

On the other hand, the CMOS TFT as described above can be applied to the organic electroluminescent display device which is a preferred embodiment of the present invention as shown in Figure 1, thereby further increasing the efficiency of the display device.

19 illustrates an example of a structure of a unit pixel of the pixel area P of FIG. 1, which will be described in more detail as follows.

First, the active layer 21 of the driving TFT 20 is formed on the substrate 1. In this case, the buffer layer 11 may be further provided on the substrate 1. The active layer 21 of the driving TFT 20 may also be composed of nanoparticles, as described above.

After the gate insulating film 23 is formed to cover the active layer 21, the gate electrode 24 and the interlayer insulating film 25 are sequentially formed, and then contact holes 26a are formed.

A source / drain electrode 26 is disposed on the interlayer insulating layer 25, and the source / drain electrode 26 is connected to the active layer 21 through the contact hole 26a.

Meanwhile, when the gate electrode 24 and the source / drain electrode 26 are formed, the storage capacitor 30 may be formed of the same material. That is, the lower electrode 31 of the storage capacitor 30 is formed of the same material as the gate electrode 24, and the upper electrode 32 of the storage capacitor 30 is formed of the same material as the source / drain electrode 26. do.

A planarization layer 27 is formed on the source / drain electrode 26 as an insulator, and the planarization layer 27 is an inorganic layer such as silicon nitride and / or an organic layer such as acrylic, BCB, polyimide, etc. It can be formed as.

Via holes are formed in the planarization film 27 so that any one of the source and drain electrodes 26 of the driving TFT 20 is exposed. The pixel electrode 41, which is a lower electrode layer of the organic light emitting diode 40, is formed on the planarization layer 27. The pixel electrode 41 is connected to one of the source and drain electrodes 26 through a via hole.

The pixel defining layer 15 is formed on the pixel electrode 41 by an organic material such as acrylic, BCB, polyimide, and / or an inorganic material such as silicon oxide or silicon nitride. 19, the pixel defining layer 15 is formed to have an opening so that a predetermined portion of the pixel electrode 41 is exposed.

And the organic film 42 provided with the light emitting layer is apply | coated on the opening part which the pixel electrode 41 was exposed at least. The organic layer 42 may be formed on the entire surface of the pixel defining layer 28. In this case, the emission layer of the organic layer 42 may be patterned in red, green, and blue for each pixel to implement full color.

After the organic film 42 is formed, the counter electrode 43, which is the other electrode of the organic EL device 40, is formed. The counter electrode 43 may be formed to cover all the pixels, but is not limited thereto, and may be patterned.

The pixel electrode 41 and the counter electrode 43 are insulated from each other by the organic layer 42, and apply light to the organic layer 42 to emit light in the organic layer 42. .

On the other hand, the pixel electrode 41 functions as an anode electrode, and the counter electrode 43 functions as a cathode electrode. Of course, the polarities of these pixel electrodes 41 and the counter electrode 43 may be reversed.

The pixel electrode 41 may be provided as a transparent electrode or a reflective electrode. When the pixel electrode 41 is used as a transparent electrode, the pixel electrode 41 may be provided as ITO, IZO, ZnO, or In 2 O 3. After forming a reflective film with Pt, Pd, Au, Ni, Nd, Ir, Cr, a compound thereof, or the like, ITO, IZO, ZnO, or In 2 O 3 can be formed thereon.

On the other hand, the counter electrode 43 may also be provided as a transparent electrode or a reflective electrode. When the counter electrode 43 is used as a transparent electrode, the counter electrode 43 is used as a cathode, and thus a metal having a small work function, that is, Li, Ca, or LiF. / Ca, LiF / Al, Al, Mg, and a compound thereof are deposited to face the organic film 42, and then assisted with a material for forming a transparent electrode such as ITO, IZO, ZnO, or In2O3 thereon. An electrode layer and a bus electrode line can be formed. When used as a reflective electrode, Li, Ca, LiF / Ca, LiF / Al, Al, Mg, and compounds thereof are formed by depositing the entire surface.

The organic layer 42 may be a low molecular or high molecular organic layer. When the low molecular organic layer is used, a hole injection layer (HIL), a hole transport layer (HTL), and an organic emission layer (EML) may be used. ), An electron transport layer (ETL), an electron injection layer (EIL), and the like may be formed by stacking a single or a complex structure, and the usable organic material may be copper phthalocyanine (CuPc). , N, N-di (naphthalen-1-yl) -N, N'-diphenyl-benzidine (N, N'-Di (naphthalene-1-yl) -N, N'-diphenyl-benzidine: NPB), Various applications are possible, including tris-8-hydroxyquinoline aluminum (Alq3). These low molecular weight organic layers are formed by the vacuum deposition method.

In the case of the polymer organic layer, the structure may include a hole transporting layer (HTL) and a light emitting layer (EML). In this case, PEDOT is used as the hole transporting layer, and polyvinylvinylene (PPV) and polyfluorene are used as the light emitting layer. Polymer organic materials such as (Polyfluorene) are used and can be formed by screen printing or inkjet printing.

 The structure of the pixel area as described above is not necessarily limited thereto, and may be variously applied. In addition, the thin film transistor may further include a plurality of thin film transistors for implementing various circuits connected to the driving thin film transistor in addition to the driving thin film transistor, and the capacitor may also exist in various ways depending on the circuit to be implemented.

As described above, the present invention is applied to an organic electroluminescent display, but the present invention is not limited thereto, and the present invention can be applied to any structure that can use a TFT such as a liquid crystal display or an inorganic electroluminescent display. .

According to the present invention as described above, the following effects can be obtained.

First, it is possible to efficiently drive the CMOS thin film transistor without changing the size of the active layer of the TFT.

Second, by utilizing the characteristics of the nanoparticles, a CMOS thin film transistor having efficient driving characteristics can be obtained.

Third, by using nanoparticles in the channel of the thin film transistor, a thin film transistor and a flat panel display device, particularly an organic light emitting display device, can be manufactured at room temperature or low temperature without undergoing a high temperature process.

Fourth, accordingly, a plastic material vulnerable to high temperature heat treatment can be used for the flat panel display. Therefore, it is more advantageous to manufacture a flexible flat panel display.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (26)

An N-type thin film transistor having an N-type active layer in which a channel is formed, the N-type active layer having a plurality of N-type nanoparticles arranged in parallel with each other; And And a P-type thin film transistor having a P-type active layer in which a channel is formed, wherein the P-type active layer has a plurality of P-type nanoparticles arranged in parallel with each other. At least the channel of the N-type thin film transistor and the channel of the P-type thin film transistor have different directions, The direction of the channels of the N-type thin film transistor and the P-type thin film transistor is determined in a direction in which current mobility in the channel of the N-type thin film transistor is decreased or a threshold voltage of the N-type thin film transistor is increased. And the current mobility in the channel of the P-type thin film transistor is increased or the absolute value of the threshold voltage of the P-type thin film transistor is decreased. delete delete delete delete The method of claim 1, At least one of the N-type and P-type nanoparticles is a CMOS thin film transistor, characterized in that the nanowires, nanorods, or nanoribbons. The method of claim 1, The angle formed by the channel direction of the N-type active layer and the length direction of the N-type nanoparticles in the N-type thin film transistor and the angle formed by the channel direction of the P-type active layer and the length direction of the P-type nanoparticles in the P-type thin film transistor CMOS thin film transistor, characterized in that the other. The method of claim 7, wherein The angle formed by the channel direction of the N-type active layer and the length direction of the N-type nanoparticles in the N-type thin film transistor is greater than the angle formed by the channel direction of the P-type active layer and the length direction of the P-type nanoparticles in the P-type thin film transistor. CMOS thin film transistor, characterized in that. The method of claim 7, wherein And the angle formed between the channel direction of the N-type active layer and the length direction of the N-type nanoparticles in the N-type thin film transistor is 45 ° to 135 °. The method of claim 9, And the angle formed between the channel direction of the N-type active layer and the length direction of the N-type nanoparticles in the N-type thin film transistor is 90 °. The method of claim 7, wherein And the angle formed between the channel direction of the P-type active layer and the length direction of the P-type nanoparticles in the P-type thin film transistor is -45 ° to 45 °. The method of claim 11, And the angle formed between the channel direction of the P-type active layer and the length direction of the P-type nanoparticles in the P-type thin film transistor is 0 °. The method of claim 1, And the channel of the N-type active layer in the N-type thin film transistor and the channel of the P-type active layer in the P-type thin film transistor have the same length. An N-type thin film transistor having an N-type active layer in which a channel is formed, the N-type active layer having a plurality of N-type nanoparticles arranged in parallel with each other; And And a P-type thin film transistor having a P-type active layer in which a channel is formed, wherein the P-type active layer has a plurality of P-type nanoparticles arranged in parallel with each other. The angle formed by the channel direction of the N-type active layer and the length direction of the N-type nanoparticles in the N-type thin film transistor is greater than the angle formed by the channel direction of the P-type active layer and the length direction of the P-type nanoparticles in the P-type thin film transistor. CMOS thin film transistor, characterized in that. delete delete delete delete The method of claim 14, At least one of the N-type and P-type nanoparticles is a CMOS thin film transistor, characterized in that the nanowires, nanorods, or nanoribbons. delete The method of claim 14, And the angle formed between the channel direction of the N-type active layer and the length direction of the N-type nanoparticles in the N-type thin film transistor is 45 ° to 135 °. The method of claim 21, And the angle formed between the channel direction of the N-type active layer and the length direction of the N-type nanoparticles in the N-type thin film transistor is 90 °. The method of claim 14, And the angle formed between the channel direction of the P-type active layer and the length direction of the P-type nanoparticles in the P-type thin film transistor is -45 ° to 45 °. The method of claim 23, wherein And the angle formed between the channel direction of the P-type active layer and the length direction of the P-type nanoparticles in the P-type thin film transistor is 0 °. The method of claim 14, And the channel of the N-type active layer in the N-type thin film transistor and the channel of the P-type active layer in the P-type thin film transistor have the same length. 26. A flat panel display comprising at least one CMOS thin film transistor according to any one of claims 1, 6, 14, 19, and 21-25.

Images