KR100669396B1 - Plasma display panel and method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel that realizes brightness enhancement, low voltage driving, and high efficiency by increasing the amount of secondary electron emission into a discharge cell using carbon nanotubes.

According to the present invention, a plasma display panel includes a first substrate and a second substrate, partition walls disposed in a space between the first substrate and the second substrate to form discharge cells, and a phosphor layer formed in each discharge cell. Address electrodes formed corresponding to the respective discharge cells, display electrodes formed on the first substrate in a direction crossing the address electrodes, a dielectric layer covering the display electrodes, and a dielectric layer in the dielectric layer. And (iii) a carbon nanotube layer formed with a pattern.

Plasma Display, Dielectric Layer, Carbon Nanotube Layer, Bus Electrode, Pattern

Description

Plasma Display Panel and Manufacturing Method Thereof {PLASMA DISPLAY PANEL AND METHOD OF THE SAME}

1 is an exploded perspective view schematically illustrating a plasma display panel according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line A-A of FIG. 1.

3A to 3D are cross-sectional views illustrating a process of manufacturing a first substrate in a method of manufacturing a plasma display panel according to an embodiment of the present invention.

The present invention relates to a plasma display panel (PDP, hereinafter referred to as PDP) for displaying an image.

In general, PDP uses an image of red (R), green (G), and blue (B) visible light generated by vacuum ultraviolet (VUV: Vacuum Ultra-Violet) emitted from a plasma obtained by gas discharge to excite the phosphor. It is a display element to implement. The PDP can realize a 60-inch or larger screen with a thickness of only 10 cm or less, and since it is a self-luminous display device such as a CRT, it has no characteristic of distortion due to color reproduction and viewing angle, and also has a simple manufacturing method compared to LCD. As a result, it is gaining popularity as a TV and an industrial flat panel display having strength in terms of productivity and cost.

In a typical AC PDP, address electrodes are formed in one direction on a rear substrate, and a dielectric layer is formed on the front surface of the rear substrate while covering the address electrodes. Stripe-shaped barrier ribs are formed on the dielectric layer between the address electrodes, and phosphor layers of red (R), green (G), and blue (B) colors are formed between the barrier ribs.

In addition, a sustain electrode and a scan electrode are formed on one surface of the front substrate facing the rear substrate, each of which comprises a pair of transparent electrodes arranged in a direction crossing the address electrodes and causing a surface discharge, and a bus electrode applying a discharge voltage thereto. For example, display electrodes are formed, and a dielectric layer and an MgO protective film are sequentially formed on the entire front substrate while covering the sustain electrodes and the scan electrodes.

The point where the address electrodes on the rear substrate and the pair of sustain electrodes and the scan electrodes on the front substrate cross each other constitutes a discharge cell.

In the PDP configured as described above, millions of unit discharge cells are arranged in a matrix form. In order to simultaneously drive the discharge cells of the AC PDP arranged in a matrix form, driving using the memory characteristic is performed.

In more detail, in order to cause a discharge between the sustain electrode and the scan electrode constituting the pair of display electrodes, a potential difference of more than a specific voltage is required, and the voltage at this boundary is called a firing voltage (Vf). At this time, when an address voltage is applied between the scan electrode and the address electrode, the discharge is started to form a plasma in the discharge cell, and the electrons and ions in the plasma move toward the electrode having the opposite polarity, so that a current flows.

On the other hand, a dielectric layer is applied to each electrode of the AC PDP so that most of the transferred space charges are stacked on the dielectric layer having the opposite polarity, so that the net space potential between the scan electrode and the address electrode is originally applied to the address voltage. It becomes smaller than Va, the discharge is weakened, and the address discharge is extinguished. At this time, a relatively small amount of electrons accumulates on the sustain electrode side, and a relatively large amount of ions accumulates on the scan electrode side. The space voltage formed between the sustain electrode and the scan electrode by these wall charges is referred to as wall voltage (Vw).

Subsequently, when a constant voltage (Vs: discharge sustain voltage) is applied between the sustain electrode and the scan electrode, the sum of the magnitudes of the discharge sustain voltage Vs and the wall voltage Vw (Vs + Vw) is the discharge start voltage. If it is higher than (Vf), the discharge occurs in the discharge cell, and the vacuum ultraviolet light (VUV) generated at this time excites the phosphor layer and emits visible light through the transparent front substrate so that the PDP realizes an image.

The PDP is required to improve the luminance by increasing the emission amount of secondary electrons when ionized ions collide in the discharge cell, and for this purpose, many technologies using carbon nanotubes have been developed.

Disclosure of Invention An object of the present invention is to provide a plasma display panel and a method of manufacturing the same, which realize brightness enhancement, low voltage driving, and high efficiency by increasing the amount of secondary electrons emitted into a discharge cell using carbon nanotubes.

According to the present invention, a plasma display panel includes a first substrate and a second substrate, partition walls disposed in a space between the first substrate and the second substrate to form discharge cells, and a phosphor layer formed in each discharge cell. Address electrodes formed corresponding to the respective discharge cells, display electrodes formed on the first substrate in a direction crossing the address electrodes, a dielectric layer covering the display electrodes, and a dielectric layer in the dielectric layer. And (iii) a carbon nanotube layer formed with a pattern.

The dielectric layer includes first and second dielectric layers formed in a multilayer structure with a carbon nanotube layer interposed therebetween.

The second dielectric layer is formed with a pattern on the carbon nanotube layer. In other words, the carbon nanotube layer can cover the entire surface of the first dielectric layer.

The carbon nanotube layer has a portion covered with the second dielectric layer and a portion exposed out of the second dielectric layer by an opening pattern of the second dielectric layer. The exposed portion of the carbon nanotube layer may be formed to correspond to an end portion facing the center of the discharge cell of the display electrode. The exposed portion of the carbon nanotube layer and the second dielectric layer are covered with a protective layer.

The first dielectric layer may be formed to a thickness of 10 to 20㎛. On the other hand, the plasma display panel manufacturing method according to the present invention, forming a display electrode on the first substrate;

Forming a first dielectric layer to cover the display electrode, and forming a carbon nanotube layer on the first dielectric layer; And

Forming a second dielectric layer to cover the carbon nanotube layer. In this case, in the forming of the second dielectric layer, the carbon nanotube layer may be partially exposed by patterning the dielectric layer.

And forming a passivation layer to cover the patterned second dielectric layer and the exposed carbon nanotube layer.

The second dielectric layer may be patterned by a printing method using a screen mask, a dielectric coating layer may be formed of a photosensitive dielectric, and may be formed by patterning by an exposure developing method.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view schematically illustrating a plasma display panel according to an embodiment of the present invention.

Referring to this figure, the PDP is schematically described. The PDP seals the first substrate (1, hereinafter referred to as front substrate) and the second substrate (3, hereinafter referred to as back substrate) to face each other. It is formed by filling an inert gas between the front substrate 1 and the back substrate 3. In the space formed between the front substrate 1 and the back substrate 3, a plurality of partition walls 5 are arranged to form a plurality of discharge cells 7R, 7G, 7B. In the discharge cells 7R, 7G, and 7B, phosphors of red (R), green (G), and blue (B) colors are formed.

On the front substrate 1, display electrodes 9 and 11 are formed to extend along the x-axis direction of the drawing, and the display electrodes 9 and 11 are formed in the discharge cells 7R, 7G, and 7B in the y-axis direction. Are arranged at corresponding intervals. In addition, address electrodes 13 are formed on the rear substrate 3 in a direction intersecting the display electrodes 9 and 11 (the y-axis direction of the drawing). In the x-axis direction of the figure, the discharge cells 7R, 7G, and 7B are arranged at intervals corresponding to each other. That is, the display electrodes 9 and 11 and the address electrodes 13 are arranged in a corresponding structure while crossing the discharge cells 7R, 7G, and 7B.

The partition walls 5 provided between the front substrate 1 and the rear substrate 3 are arranged in parallel with the other partition walls 5 adjacent to each other, thereby defining the front substrate 1 and the rear substrate 3. Discharge cells 7R, 7G, and 7B, which are required for plasma discharge, are arranged in the spaces between them to form partitions. The present embodiment illustrates a stripe-type partition wall structure formed only of partition walls 5 extending in parallel with the address electrodes 13 (in the y-axis direction of the drawing).

In addition, the barrier rib structure of the present invention is not limited to the barrier rib structure, and the barrier ribs 5 formed in the direction parallel to the address electrodes 13 (the y-axis direction in the drawing) intersect the barrier ribs 5 with the barrier ribs 5. And a closed barrier rib structure that individually closes and partitions the discharge cells 7R, 7G, and 7B by barrier ribs (not shown) formed in a direction (x-axis direction of the drawing). In addition, the barrier rib structure of the present invention includes a closed barrier rib structure that forms the discharge cells 7R, 7G, and 7B in four angles and a closed barrier rib structure that is formed in six and eight angles.

Since the address electrodes 13 are typically formed on the rear substrate 3, the present embodiment exemplifies a configuration in which the address electrodes 13 are formed on the rear substrate 3, but the present invention is not limited thereto. (13) includes all of the configuration formed on the front substrate (1), the partition (5) or the like. Referring to the present embodiment, the address electrodes 13 are covered with the dielectric layer 15 to form wall charges in the discharge cells 7R, 7G, and 7B to cause address discharge, and the partition 5 is covered by the dielectric layer ( 15) is formed on.

The display electrodes 9 and 11 include sustain electrodes and scan electrodes 11 and 13 corresponding to both sides of the discharge cells 7R, 7G, and 7B, and are formed on the front substrate 1. In addition, the present embodiment exemplarily includes the sustain electrode and the scanning electrodes 9 and 11 on the front substrate 1, but the present invention shows the display electrode 9 described above on the front substrate 1 for scanning and addressing. And 11) and an intermediate electrode (not shown), which is further provided between the sustain electrode and the scan electrodes 9 and 11.

The sustain electrodes and the scan electrodes 9 and 11 may be formed of the transparent electrodes 9a and 11a and the bus electrodes 9b and 11b, respectively, as shown in this embodiment. It may be formed only of the bus electrodes 9b and 11b, respectively. When an intermediate electrode (not shown) is provided, the intermediate electrode is preferably formed of the same material as the sustain electrode and the scan electrodes 9 and 11 so as to simplify the fabrication process.

The transparent electrodes 9a and 11a are formed in a stripe type extending in the direction crossing the address electrode 13 (the x-axis direction in the drawing), and partially protrude toward the center of the discharge cells 7R, 7G and 7B. It may be formed into a protrusion. In addition, since the transparent electrodes 9a and 11a block surface areas of the discharge cells 7R, 7G and 7B as part of causing surface discharge inside the discharge cells 7R, 7G and 7B, the blocking of visible light is minimized. It is preferably formed of a transparent material so as to secure the brightness, it may be formed of an indium tin oxide (ITO) electrode.

In addition, the bus electrodes 9b and 11b compensate for the high resistance of the transparent electrodes 9a and 11a to ensure the electrical conductivity of the transparent electrodes 9a and 11a. Preferably, it may be formed of an Al electrode. The bus electrodes 9b and 11b are formed in a stacked structure on the transparent electrodes 9a and 11a formed on the front substrate 1 to extend in the direction crossing the address electrode 13 (the x-axis direction in the drawing). do.

In addition, since the bus electrodes 9b and 11b are formed of an opaque material, the bus electrodes 9b and 11b are disposed corresponding to the partition walls 5, and are formed to have a width smaller than that of the partition walls 5 to emit light from the discharge cells 7R, 7G, and 7B. It is desirable to minimize the blocking of visible light.

The display electrodes 9 and 11 formed as described above are covered with a stacked structure of the dielectric layer 17 and the MgO protective film 19 to accumulate wall charges. This dielectric layer 17 is preferably formed of a transparent dielectric so as to improve the transmittance of visible light. The MgO protective film 19 prevents ions of the ionized atoms from colliding with the dielectric layer 17 and damaging the dielectric layer 17, and improves the emission of secondary electrons when the ions collide.

FIG. 2 is a cross-sectional view taken along the line A-A of FIG. 1.

Referring to this figure, the dielectric layer 17 will be described. The dielectric layer 17 has a carbon nanotube layer 21 therein. The carbon nanotube layer 21 may be formed with a specific pattern in the dielectric layer 17. The carbon nanotube layer 21 emits secondary electrons without disturbing the addressing between the sustain electrode and the scan electrodes 9 and 11 (usually the scan electrode) and the address electrode 13 and the emission of visible light. Is further increased to improve the ratio of the luminance to the power consumption, that is, the efficiency, thereby improving the luminance.

The pattern of the carbon nanotube layer 21 can be realized by patterning the dielectric layer 17.

In this case, the dielectric layer 17 includes first and second dielectric layers 17a and 17b forming a multilayer structure with the carbon nanotube layer 21 interposed therebetween. That is, the first dielectric layer 17a is formed on the display electrodes 9 and 11, and the carbon nanotube layer 21 is formed on the first dielectric layer 17a, and the carbon nanotube layer 21 is formed on the display electrodes 9 and 11. On the top, a second dielectric layer 17b is patterned to expose a portion of the carbon nanotube layer 21. Therefore, one side of the carbon nanotube layer 21 is applied to the entire surface of the first dielectric layer 17a, and the other side forms the same pattern as the opening pattern of the second dielectric layer 17b.

In other words, according to the pattern of the second dielectric layer 17b, the carbon nanotube layer 21 is formed by the opening pattern of the portion 21a and the second dielectric layer 17b covered with the second dielectric layer 17b. It has a portion 21b exposed out of the dielectric layer 17b. As described above, the portion 21b exposed to increase the emission of the secondary electrons and to drive the low voltage is preferably formed to correspond to an end portion of the display electrodes 9 and 11 facing the center of the discharge cell 7G. That is, the exposed portion 21b of the carbon nanotube layer 21 is formed in a pattern corresponding to opposite ends of each of the transparent electrodes 9a and 11a.

The first dielectric layer 17a is preferably formed to a thickness of about 10 to 20 μm. When the carbon nanotube layer 21 is applied thereon, the second dielectric layer 17b is applied, and then the second dielectric layer 17b is patterned, the dielectric layer thicknesses of the patterned portion and the non-patterned portion are relatively different. While being formed, the carbon nanotube layer 21 may have an effect of patterning the pattern.

The portion 21b of the carbon nanotube layer 21 exposed by the opening pattern of the second dielectric layer 17b is covered by the second dielectric layer 17b because it is separated from the second dielectric layer 21b. Although it has a larger upright than), since the exposed portion 21b is covered with the MgO protective film 19, there is no problem caused by the uprightness of the carbon nanotubes. That is, the MgO passivation layer 19 covers a portion of the second dielectric layer 17b and the carbon nanotube layer 21 of the portion 21b exposed thereto.

3A to 3D are cross-sectional views illustrating a process of manufacturing a first substrate in a method of manufacturing a plasma display panel according to an embodiment of the present invention.

The plasma display panel as described above may be manufactured by a manufacturing method including a process as shown in FIG. 3.

Referring to the drawings, the manufacturing method of the PDP will be described. In this method, the display electrodes 9 and 11 are formed on the first substrate 1, and the address electrode 13 is formed on the second substrate 3. And forming partition walls 5 for partitioning the discharge cells 7R, 7G, and 7B, and forming the phosphor layers 8R, 8G, and 8B in the discharge cells 7R, 7G, and 7B. Sealing each of the first and second substrates 1 and 3, and exhausting air between the sealed first and second substrates 1 and 3, injecting an inert gas, and sealing the same.

Since all methods except for forming the display electrodes 9 and 11 on the first substrate 1 may be applied, a detailed description thereof will be omitted, and the display electrode (1) on the first substrate 1 will be omitted. The steps of forming 9 and 11 and the steps of forming the carbon nanotube layer 21 and the dielectric layer 21 thereon will be described only.

In addition, even in the step of forming the display electrodes 9 and 11 on the first substrate 1, a known method may be applied to the step of forming the transparent electrodes 9a and 11a and the bus electrodes 9b and 11b. The description thereof will be omitted, and a method of patterning the carbon nanotube layer 21 on the dielectric layer 17 will be described.

First, the display electrodes 9 and 11 including the transparent electrodes 9a and 11a and the bus electrodes 9b and 11b are formed on the first substrate 1, and then the first electrodes are formed on the display electrodes 9 and 11. The dielectric layer 17a is formed (see FIG. 3A). The first dielectric layer 17a may be formed to a thickness corresponding to a portion of the entire thickness of the dielectric layer 17, that is, a thickness of 10 to 20 μm.

Next, the carbon nanotube layer 21 is formed on the first dielectric layer 17a. (See FIG. 3B.) The carbon nanotube layer 21 may be applied to the entire surface of the first dielectric layer 17a. have.

Next, a second dielectric layer 17b is formed on the carbon nanotube layer 21 (see FIG. 3C). At this time, the dielectric layer applied on the carbon nanotube layer 21 is apertured and patterned. 21 can be formed to be partially exposed.

 In order to pattern the second dielectric layer 17b, a printing method using the screen mask 23 may be applied. Alternatively, an exposure developing method may be applied. When the exposure developing method is applied, the second dielectric layer 17b or the dielectric layer 17 is preferably formed of a photosensitive dielectric.

After patterning the second dielectric layer 17b, an MgO passivation layer 19 is formed thereon (see FIG. 3D). The MgO passivation layer 19 is patterned to expose the carbon nanotube layer 21 of the exposed portion 21b. ) And the second dielectric layer 17b covering the same to cover the second dielectric layer 17b to protect the dielectric layer 17 and the carbon nanotube layer 21.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to the scope of the invention.

As described above, according to the plasma display panel according to the present invention, the first dielectric layer and the carbon nanotube layer are formed on the display electrode of the first substrate, and the second dielectric layer is formed on the carbon nanotube layer in a pattern corresponding to the bus electrode. By forming, the carbon nanotube layer has an effect of patterning the carbon nanotube layer. The carbon nanotube layer increases the emission of secondary electrons in the discharge cell, thereby improving the discharge efficiency (ratio of luminance to power consumption). There is an effect of improving luminance and realizing low voltage driving.

Claims (13)

A first substrate and a second substrate; Barrier ribs disposed in a space between the first substrate and the second substrate to form discharge cells; Phosphor layers formed in the discharge cells; Address electrodes formed corresponding to the discharge cells; Display electrodes formed on the first substrate in a direction crossing the address electrodes; A dielectric layer covering the display electrodes; And And a carbon nanotube layer forming a layer in the dielectric layer and partially exposed by the opening pattern of the dielectric layer. The method of claim 1, The dielectric layer includes a first dielectric layer and a second dielectric layer formed in a multilayer structure with a carbon nanotube layer interposed therebetween. The method of claim 2, And the second dielectric layer has a pattern on the carbon nanotube layer. The method of claim 2, And the carbon nanotube layer covers the entire surface of the first dielectric layer. The method of claim 2, And the carbon nanotube layer has a portion covered with the second dielectric layer and a portion exposed out of the second dielectric layer by an opening pattern of the second dielectric layer. The method of claim 5, The exposed portion of the carbon nanotube layer is formed so as to correspond to an end portion facing the center of the discharge cell of the display electrode. The method of claim 5, The exposed portion of the carbon nanotube layer and the second dielectric layer is covered with a protective layer. The method of claim 2, The first dielectric layer is formed of a plasma display panel 10 to 20㎛ thickness. Forming a display electrode on the first substrate; Forming a first dielectric layer to cover the display electrode; Forming a carbon nanotube layer on the first dielectric layer; And And forming a second dielectric layer to cover the carbon nanotube layer. The method of claim 9, And patterning the dielectric layer to partially expose the carbon nanotube layer in the forming of the second dielectric layer. The method of claim 10, And forming a passivation layer to cover the patterned second dielectric layer and the exposed carbon nanotube layer. The method of claim 10, And the second dielectric layer is patterned by a printing method using a screen mask. The method of claim 10, And the second dielectric layer is formed of a photosensitive dielectric, and a dielectric coating layer is patterned by an exposure developing method.

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