KR100668664B1 - Module and method for encryption/decryption by using aes rijndael block algorithm - Google Patents

Abstract

A module and method for encryption/decryption by using AES rijndael block algorithm are provided to facilitate a module design process by composing equally an encryption process and a decryption process. A sub-byte block unit(420) performs a substitutional operation for a plaintext and recovers the operated plaintext. A shift row block unit(430) shifts rows of a data matrix processed by the sub-byte block unit or recovers the shifted rows. A mix column block unit(450) converts linearly or inversely the data processed by the shift row block unit. A first MUX(440) receives selectively the data processed by the shift row block unit. A second MUX(460) receives selectively the plaintext or the encryption text, the data processed by the mix column block unit or the data transmitted from the first MUX. A third MUX(490) selects a round key. A round key processing block unit(470) receives the selected data from the second MUX and the selected round key from the third MUX and encrypts or decrypts the data.

Description

Device and method for encrypting / decrypting using AES Linedal Block Algorithm {Adule and Method for Encryption / Decryption by Using AES Rijndael Block Algorithm}

1 is a hardware configuration diagram illustrating a conventional AES linedal encryption algorithm;

2 is a hardware configuration diagram for explaining a conventional AES linedal decoding algorithm;

3 is a conventional hardware block diagram combining AES linedal encryption and decryption blocks;

4 is a hardware block diagram combining AES linedal encryption and decryption blocks according to an embodiment of the present invention;

5 is a table illustrating a setting value of each mux during encryption and decryption in the AES linedal encryption and decryption block according to the present invention;

6 is a diagram for describing an encryption process in hardware combining AES line-dal encryption and decryption block according to an embodiment of the present invention;

7 is a diagram illustrating a decryption process in hardware combining AES line-dal encryption and decryption blocks according to an embodiment of the present invention.

The present invention relates to an encryption / decryption apparatus and method using the Advanced Encryption Standard (AES) Rijndael block algorithm. More specifically, in the AES linedal block algorithm for encrypting and decrypting transmission data, encryption / decryption using the AES linedal block algorithm that simplifies hardware design and modification by making hardware block arrangements necessary for the encryption process and the decryption process the same. An apparatus and method are provided.

As electronic payments using the Internet and mobile communication networks become active, security of personal information is considered to be very important. Accordingly, encryption and decryption processes are required for security of personal information, and DES (Data Encryption Standard), which is an encryption method using 56 bits, is used.

However, with the technological development of the Internet and mobile communication networks, hacking techniques for impure purposes such as personal information leakage have also developed, which threatens the safety of the DES method using 56 bits. Accordingly, a more secure encryption algorithm is required, and an AES linedal block algorithm using a key of 128 bits or more has been proposed.

1 is a hardware configuration diagram illustrating a conventional AES linedal encryption algorithm.

The AES line moon encryption algorithm is composed of an encryption initial round processing unit 110, an encryption repeat round processing unit 120, and an encryption last round processing unit 130.

The encryption initial round processing unit 110 is composed of a round key processing (AddRoundKey) block for processing a round key for encryption, and the encryption repetition round processing unit 120 performs subbytes for performing a substitution operation on each byte. Block 122, in the matrix of each data component of the AES, a ShiftRows block 124 for moving rows, and a mixed column for performing additional linear transformation of the matrix moved by the shift row block 124 (MixColums) block 126 and round key processing (AddRoundKey) block 128. In addition, the encryption last round processor 130 includes a subbyte block, a shift row block, and a round key processing block.

Here, the round key processing blocks included in the encryption initial round processing unit 110, the encryption repeat round processing unit 120, and the encryption last round processing unit 130 respectively receive the input encryption round key (Round KEY) for encryption. Do the work.

When the plain text for the encryption operation is input to the AES linedal encryption algorithm configured as described above, the encryption algorithm of the encryption initial round processing unit 110, the encryption repeat round processing unit 120, and the encryption last round processing unit 130 passes through the encryption algorithm. Is output.

When the encrypted data is transmitted as described above, a decryption algorithm for interpreting the received cipher text is required to restore it to the original plain text.

2 is a hardware configuration diagram illustrating a conventional AES linedal decoding algorithm.

The hardware configuration of the decryption algorithm in the AES linedal algorithm is also composed of the decryption initial round processing unit 210, the decryption repeat round processing unit 220, and the decryption last round processing unit 230, like the encryption algorithm.

The decryption initial round processing unit 210 includes a round key processing (AddRoudnKey) block that performs a round key processing operation for decryption. The decryption repetition round processing unit 220 may include an InvShiftRows block 222 for returning the shifted row back to the original position, an InvSubBytes block 224 for returning the cipher text on which the substitution operation was performed, A round key processing (AddRoudnKey) block 226 for performing round key processing for decryption and an InvMixColums block 228 for inversely performing an additional linear transformation. The decryption last round processor 230 includes an inverse shift row block, an inverse subbyte block, and a round key processing block.

Here, similarly to the encryption algorithm, the round key processing blocks included in the decryption initial round processing unit 210, the decryption repeat round processing unit 220, and the decryption last round processing unit 230, respectively, are encrypted in advance in the encryption data receiving device. Receives round key and performs round key processing for decryption. In this case, the encrypted data receiving apparatus may separately receive the encrypted round key from the encrypted data through a communication network, and perform a round key processing operation for decryption using the received encrypted round key.

Looking at the encryption iteration round processing unit 120 and the decryption iteration round processing unit 220 of the AES linedal block algorithm as described above, in the encryption process, after the sub-byte processing, the process proceeds to the shift row process, while in the decryption process inverse shift processing Afterwards, it can be confirmed that the reverse subbyte process is performed. In addition, in the encryption process, after the process of the mix column process, the process proceeds to the round key process, while in the decryption process, after the process of the round key process, it can be seen that proceeds to the reverse mix column process.

The encryption last round processing unit 130 and the decryption last round processing unit 230 also proceed to shift after the subbyte processing of the encryption process, whereas in the decryption process, the reverse shift process is performed to the reverse subbyte process.

Such an AES linedal encryption block and decryption block may be configured as one hardware.

3 is a conventional hardware block diagram combining AES linedal encryption and decryption blocks.

In the hardware block diagram of the AES linedal algorithm configured as shown in FIG. 3, iterative round processing in the encryption process is performed by subbyte block 122, shift row block 124, mix column block 126, and first mux. 312 and the round key processing block 128. On the other hand, the iterative round processing in the decoding process is performed by the reverse shift block 222, the reverse subbyte block 224, the second mux 322, the round key processing block 226, the inverse mix column block 228 and the first. Three stages of the mux 324 is to go through. As the steps for encryption and decryption are different in this way, the output time for input data is different, and it is difficult to modularize similar blocks, and commonly used data buffers 310 and 320 and round keys. The processing blocks 128 and 226 are also required for the encryption block and the decryption block, respectively.

That is, in the case of implementing the conventional AES linedal block algorithm in hardware, the block order of the encryption process and the decryption process is different, making it difficult to modularize, and the data buffer and the round key processing block that can be commonly used in hardware design. Each design requires a separate design, which complicates the design, and separates data buffers, which wastes hardware resources. In addition, when designing an integrated circuit to which the AES linedal block algorithm is applied due to the asymmetrical output time and performance of the input, each path time delay must be taken into consideration. Effort is required.

Korea Patent Publication No. 2002-0087331 'AES Rijndael cipher and decryption circuit using partial round-to-round pipeline technique' (2002.11.22) and Korea Patent Publication No. 2004-0045517 'block data real time encryption and decryption apparatus using Rijndael cipher and Method '(2004.06.02) provides an efficient encryption circuit and a decryption circuit, but since the encryption process and the decryption process are different from each other, it is difficult to modularize to simultaneously process the encryption and decryption, and the hardware design There is still a conventional problem in that each design is required and resources are wasted.

In order to solve this problem, the present invention changes the order of decryption algorithms in the AES linedal block algorithm for encrypting and decrypting transmission data so that the encryption and decryption processes are the same, and then performs a block performing a similar function. Provided are an encryption / decryption apparatus and method using an AES linedal block algorithm that blocks and improves performance.

In order to achieve the above technical problem, the present invention provides a device for encrypting and decrypting an AES linedal algorithm. In an apparatus for encrypting and decrypting data according to the AES linedal algorithm, an alternate operation of plain text input for encryption is performed. A SubBytes block unit for performing or returning a substituted cipher text; A ShiftRows block unit for shifting rows in the matrix of data processed by the subbyte block unit or returning the shifted rows to their original positions; A MixColums block unit for further linearly changing or inversely transforming data processed by the shift block unit; A first mux for selectively receiving data processed by the shift block unit according to encryption or decryption; A second mux for selectively receiving plain text or cipher text input for encryption, data processed through the mix column block unit, or data transmitted from the first mux; A third mux for selecting a round key used in a round key processing operation for encryption or decryption; And a round key processing (AddRoundKey) block for receiving the selected data from the second mux, receiving the round key selected through the third mux, and encrypting or decrypting the data through a round key processing operation.

In addition, in order to achieve the second technical problem, the present invention provides a method for encrypting plain text data input according to an AES linedal algorithm as an encryption method of an AES linedal algorithm, which includes (a) plaintext input for encryption. Key processing the initial data of the type using an encryption round key; (b) performing an iterative rounding process by shifting rows in the matrix of initial data components and then performing additional linear transformations after the keyed initial data is substituted; (c) key processing the repeatedly rounded data using an encryption round key; (d) performing a substitution operation on the keyed iterative rounded data and then performing a final rounded process of moving rows in the matrix of the iterative rounded data elements; And (e) outputting a cipher text generated by performing key processing using an encryption round key on the last round processed data.

In addition, in order to achieve the third technical problem, the present invention provides a decryption method of the AES linedal algorithm, and in the method of decrypting ciphertext data input according to the AES linedal algorithm, (a) a ciphertext input for decryption. Key-processing initial data of a format using a decryption round key; (b) executing an iterative round process of processing the sub-bytes, reverse shifts, and reverse mix columns of the keyed initial data; (c) key processing the repeatedly rounded data using a decryption round key; (d) executing a final round processing of reverse subbytes and reverse shift processing of the keyed repetitive round processing data; And (e) outputting the plain text generated by performing key processing using the decryption round key on the last round processed data.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

In addition, when a part is said to "include" a certain component, it means that it may further include other components, without excluding other components unless otherwise stated.

In addition, the term module described herein refers to a unit for processing a specific function or operation, which may be implemented in hardware or software, or a combination of hardware and software.

4 is a hardware block diagram combining AES linedal encryption and decryption blocks according to an embodiment of the present invention.

If the AES linedal encryption and decryption block algorithm according to the present invention is configured in hardware, it is configured as shown in FIG. The encryption and decryption block algorithm according to the present invention includes a data buffer 410, a subbyte block unit 420, a shift row block unit 430, a first mux 440, a mixed column block unit 450, and a second block. The mux 460 includes a round key processing block 470, an inverse mix column block 480, and a third mux 490.

Here, the subbyte block unit 420 includes a subbyte block 422 for encryption and an inverse subbyte block 424 for decryption, and the shift row block unit 430 includes a shift row block 432 for encryption. ), And an inverse shift row block 434 for decryption, and the mix column block unit 450 includes a mix column block 452 for encryption and an inverse mix column block 454 for decryption.

In addition, the first mux 440, the second mux 460, and the third mux 490 play a role of selecting a next step to be performed according to a situation in the encryption and decryption process.

Here, in the AES line moon encryption and decryption block algorithm according to the present invention, it can be seen that the positions of the reverse shift block 434 and the reverse subbyte block 424 for decryption are different from those in the conventional decryption process. . That is, in the related art, the inverse shift block 434 calculation result is performed first, and the inverse subbyte block 424 is calculated. However, in the AES line moon encryption and decryption block algorithm according to the present invention, the inverse subbyte block 424 is used. Is calculated first, followed by the inverse shift block 434.

This is because the calculation through the inverse subbyte block 424 and the calculation through the inverse shift block 434 do not affect each other, so that the result of the calculation becomes the same even if the blocks are rearranged in a reversed order. Here, the sub station when the operation performed on the block of bytes 424, the operation _{f-byte sub-station,} the low reverse shift block 434 performed in the display is called _{reverse shift} f _low, and is expressed by equation (1).

f _{reverse shift} {f _{reverse subbyte} (Data)} = f _{reverse subbyte} {f _{reverse shift} (Data)}

In the decoding process, the round key processing block 470 and the inverse mix column block 454 are described. In the conventional decoding block algorithm, the calculation using the round key processing block 470 is performed first, and then the inverse mix column block 454. The round key processing block 470 is located in front of the inverse mix column block 454 so that the calculation by.

The inverse mix column block 454 is a block consisting of several XOR operations on two inputs, and the round key processing block 470 is a block that executes a simple XOR operation processing on two inputs, and thus the inverse mix column block 454. If the operation performed at f denotes an _{inverse mix column} and the round key processing block 434 as the f round key processing, the operation of the inverse mix column block 454 and the round key processing block 470 is expressed as: As shown in 2, it can be expressed as a simple XOR expression.

f _{Inverse Mix Column} {f _{Round Key Processing} (A, B)} = f _{Inverse Mix Column} (A XOR B)

According to Equation 2, after the round key processing of the state input A and the round key input B, the result of calculating through the inverse mix column block 454 is the result of XOR operation of the state input A and the round key input B. It can be seen that it is the same as the result calculated by the mix column block 454. The result is mathematically identical to the result of the XOR operation after calculating the state input A and the round key input B through the inverse mix column block 454, respectively.

That is, the round key processing block 470 for the state input A and the round key input B may be expressed as 'A XOR B', and the inverse mix column processing for the 'A XOR B' may be performed inversely with respect to A and B. It is the same as the XOR operation on the mixed column processing result, and in the XOR math operation, it can be expressed as Equation 3 according to the exchange law.

f _{Inverse mix column} (A XOR B) = f _{Inverse mix column} (A) XOR f _{Inverse mix column} (B)

= f _{inverse mix column} (B) XOR f _{inverse mix column} (A)

Accordingly, the inverse mix column process for the state may be preceded first, the inverse mix column block 454 may be disposed first, and the round key processing block 470 may be disposed later. However, as the arrangement order of the inverse mix column block 454 and the round key processing block 470 is changed, the decryption round key input to the round key processing block 470 during decryption also requires an inverse mix column process. For this purpose, the inverse mix column block 480 is additionally included in the key management unit.

Through Equation 1, Equation 2, and Equation 3, the AES linedal decryption blocks may also be arranged in the same order as the encryption block, and the subbyte block 422 and the inverse subbyte block 424 having similar characteristics may be arranged. The shift row block 432 and the reverse shift block 434, the mix column block 452, and the inverse mix column block 454 may be modularized. This modularization simplifies the data path and eliminates the need for a data buffer for decryption.

5 is a table illustrating a setting value of each mux during encryption and decryption in the AES line-dal encryption and decryption block according to the present invention.

In the hardware block diagram combining the AES linedal encryption and decryption block according to the present invention, the first mux 440, the second mux 460, and the third mux 490 are encrypted blocks or decryptions to proceed to the next step according to the situation. You need to select a block.

The first mux 440 is located between the shift row block unit 430 and the mix column block unit 450, and when an encryption operation is performed, selects 0 to mix the value received from the shift row block 432. When the decoding operation is performed, the block unit 450 transmits the value received from the reverse shift block 434 to the mix column block unit 450.

The second mux 460 is a data input from the data input unit (Input data), the mixed column processed value from the mix column block unit 450 or the reverse mixed column processed value and the shift-processed from the first mux 440 Select a value or reverse shifted value to receive it.

The second mux 460 selects a value to be received according to the round processing step and proceeds to the next step. That is, in the encryption initial round processing or decryption initial round processing step, 0 is selected to receive the data transmitted from the data input unit and transmitted to the round key processing block 470, and in the encryption iteration round processing step, 2 is selected to mix column block. The value transmitted from 452 is transmitted to the round key processing block 470, and in the decryption iteration round processing step, 1 is selected and the value transmitted from the inverse mix column block 454 is transmitted to the round key processing block 470. do. In the encryption final round processing or the decryption final round processing step, 3 is selected to transmit a value received from the first mux 440 to the round key processing block 470.

The third mux 490 is included in the key management unit to receive an encryption round key or receive an inverse mix column value for decryption received from the inverse mix column block 480. That is, the third mux 490 selects '0' to receive an encryption round key when performing an encryption operation, and selects '1' to receive an inverse mix column value when performing a decryption operation. Passed to key processing block 470.

Here, the values set in the first mux 440, the second mux 460, and the third mux 490 may be variously modified according to the method of configuring the AES linedal encryption and decryption block.

FIG. 6 is a diagram for describing an encryption process in hardware combining AES linedal encryption and decryption blocks according to an embodiment of the present invention.

The encryption process in the AES linedal encryption and decryption block according to the present invention is classified into an encryption initial round processing step, an encryption iteration round processing step, and an encryption last round processing step.

In the encryption initial round processing step, the initial data in the form of plain text transmitted from the data input unit is input to the second mux 460. The second mux 460 selects a setting value 0 for initial data input, receives initial data transmitted from the data input unit, and transmits the initial data to the round key processing block 470. The encryption round key is selected by the third mux 490 and transferred to the round key processing block 470.

In the round key processing block 470, the key is processed using the input initial data and the encryption round key, and then stored in the data buffer 410. When the keyed initial data is input to the data buffer 410, the process proceeds to the encryption iteration round processing step.

In the encryption iteration round processing step, a value stored in the data buffer 410 through the subbyte block 422 and the shift row block 432 is selected as an input by the first mux 440.

Then, the value selected by the first mux 440 is mixed column processed by the mix column block 452, and the result value is selected by the second mux 460.

The value selected by the second mux 460 serves as an input of the round key processing block 470, and the result of the round key processing is again stored in the data buffer 410. At this time, the round key used in each round key processing process is generated by the key management unit, is selected by the third mux 490 and input to the round key processing block 470.

After this repeated round processing step, the encryption last round processing step is performed. In the encryption final round processing step, the value stored in the data buffer 410 is input to the subbyte block 422 and the shift row block 432 through an iterative round processing step. The result values processed by the subbyte block 422 and the shift block 432 are selected by the first mux 440, and the second mux 460 selects the value selected by the first mux 440 again. The output value of the first mux 440 is directly input to the round key processing block 470 without passing through the mix column block 452. The encryption is completed by outputting the value passed through the round key processing block 470. At this time, the round key used in the round key processing is selected by the third mux 490.

Through this process, encryption is performed in the AES linedal block algorithm according to the present invention.

7 is a diagram illustrating a decryption process in hardware combining AES line-dal encryption and decryption blocks according to an embodiment of the present invention.

The decryption process in the AES linedal encryption and decryption block according to the present invention is classified into a decryption initial round processing step, a decryption repeat round processing step, and a decryption last round processing step.

In the decryption initial round processing step, the initial data in the form of a cipher text transmitted from the data input unit is input to the second mux 460. The second mux 460 selects a setting value 0 for initial data input, receives initial data transmitted from the data input unit, and transmits the initial data to the round key processing block 470. The decryption round key is selected by the third mux 490 and transmitted to the round key processing block 470. Here, the decryption round key has a key value in which the encryption round key is processed by the inverse mix column block 480.

The initial data and the decryption round key input to the round key processing block 470 are keyed at the round key processing block 470 and stored in the data buffer 410. When the keyed initial data is input to the data buffer 410, the process proceeds to the decoding iteration round processing step.

In the decoding iteration round processing step, the first mux 440 selects a result value of the value stored in the data buffer 410 through the reverse subbyte block 424 and the reverse shift block 434.

In addition, the value selected by the first mux 440 is reverse mixed by the inverse mix column block 454, and the result value is selected by the second mux 460.

The value selected by the second mux 460 serves as an input of the round key processing block 470, and the result of the round key processing is again stored in the data buffer 410. At this time, the round key used in each round key processing process is generated by the key management unit, is selected by the third mux 490 and input to the round key processing block 470. At this time, the decryption round key used is a value in which the encryption round key is processed by the inverse mix column block 480.

After the decryption iteration round processing step, the encryption final round processing step is performed. In the decoding final round processing step, the value stored in the data buffer 410 is input to the reverse subbyte block 424 and the reverse shift block 434 through the iterative round processing step. The resultant values processed in the inverse subbyte block 424 and the inverse shift block 434 are selected by the first mux 440, and the second mux 460 returns the values selected in the first mux 440. In this case, the output value of the first mux 440 is directly input to the round key processing block 470 without passing through the inverse mix column block 454. The decryption is completed by outputting the value passed through the round key processing block 470. At this time, the round key used in the round key processing is selected by the third mux 490.

Through this process, decoding is performed in the AES linedal block algorithm according to the present invention.

The embodiments of the present invention described above are not implemented only through the apparatus and the method, but may be implemented through a program for realizing a function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded. Implementation may be easily implemented by those skilled in the art from the description of the above-described embodiments.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the above-described configuration, by configuring the hardware so that the encryption process and the decryption process are the same, the modularity becomes easy, the design period can be shortened, the modification in the circuit for encryption and decryption is simplified, and the system can be easily ported to the system. You can expect the effect.

In addition, since the output time of the data input during the encryption and decryption process is the same, and the decryption has the same performance as the encryption, and the consideration due to the asymmetric structure is eliminated, it can be expected that the design becomes easy.

Claims (18)

An apparatus for performing encryption and decryption of data in accordance with AES (Advanced Encryption Standard) Rijndael algorithm, A SubBytes block unit which performs a substitution operation of the plain text input for the encryption or returns the substituted encryption text; A ShiftRows block unit for shifting rows in the matrix of data processed by the subbyte block unit or returning the shifted rows to their original positions; A MixColums block unit for further linearly changing or inversely transforming data processed by the shift block unit; A first mux for selectively receiving data processed by the shift block unit according to the encryption or decryption; A second mux for selectively receiving plain text or the cipher text input for the encryption, data processed through the mix column block unit, or data transmitted from the first mux; A third mux for selecting a round key used in the round key processing operation for encryption or decryption; And A round key processing block (AddRoundKey) that receives data selected from the second mux, receives a round key selected through the third mux, encrypts or decrypts the data through the round key processing operation, and outputs the encrypted data. Apparatus for encrypting and decrypting AES linedal algorithm comprising a. The method of claim 1, wherein the sub-byte block unit, A subbyte block for performing the substitution operation of the plain text for the encryption; And InvSubBytes block for returning the substituted ciphertext to the original for decryption Apparatus for encrypting and decrypting an AES linedal algorithm comprising: a. The method of claim 1, wherein the shift block unit, A shift row block for moving rows in a matrix of data processed by the sub-byte block portion for the encryption; And InvShiftRows block to return the shifted row of the ciphertext to the original for decryption Apparatus for encrypting and decrypting an AES linedal algorithm comprising: a. The method of claim 3, wherein the first mux, When the encryption proceeds, the data transmitted from the shift row block is received, and when the decryption is performed, the data transmitted from the reverse shift block is received. Device. The method of claim 1, wherein the mix column block portion, A mix column block for performing further linear transformation of data received by the first mux for the encryption; And InvMixColums block for inverting and returning additional linearly transformed data received by the first mux for decoding Apparatus for encrypting and decrypting an AES linedal algorithm comprising: a. The method according to claim 5, wherein the second mux, In response to the encryption or decryption processing, the input plain text or cipher text, data transmitted from the mix column block according to the encryption progress, data transmitted from the inverse mix column block according to the decryption progress, and the first And encrypting and transmitting one of the data received from the mux to the round key processing block. The method of claim 1, A second reverse mix column block for processing the round key for encryption and performing a reverse mix column to the third mux; Apparatus for encrypting and decrypting AES linedal algorithms further comprising. The method according to claim 7, wherein the third mux, If the encryption is in progress, receives the round key for encryption and delivers to the round key processing block, When the decryption is in progress, the encryption and decryption apparatus of the AES line Dal algorithm, characterized in that for receiving the reverse-mixed column-processed round key delivered from the second inverse mix column block to pass to the round key processing block. In a method of encrypting plain text data input according to AES (Advanced Encryption Standard) Rijndael algorithm, (a) key processing the initial data in plain text format for encryption using an encryption round key; (b) performing an iterative rounding process by performing an alternative operation on the keyed initial data and then further linearly transforming a row in a matrix of the initial data component; (c) key processing the repeated rounded data using the encrypted round key; (d) performing a substitution operation on the keyed iterative rounded data and then performing a final rounded process of moving rows in a matrix of the iterative rounded data elements; And (e) outputting a cipher text generated by performing key processing using the encryption round key on the last round processed data; An encryption method of the AES linedal algorithm, characterized in that it comprises a. The method of claim 9, The initial data keyed through step (a), the repeated rounded data through step (b) and the last rounded data through step (d) are included in the AES linedal algorithm. The encryption method of the AES linedal algorithm, characterized in that the reception is selected from one of the three mux. The method of claim 10, The encryption round key used in the steps (b), (d) and (f) is selected from one of three muxes included in the AES Rindall algorithm. Encryption method of the algorithm. The method of claim 9, Temporarily storing the initial data keyed through the steps (a) and (c) and the repeated round key processing data; The encryption method of the AES line Dal algorithm, characterized in that it further comprises. In the method for decrypting the input cipher text data according to AES (Advanced Encryption Standard) Rijndael algorithm, (a) key processing the ciphertext-format initial data input for decryption using a decryption round key; (b) executing an iterative round process of processing the sub-bytes, reverse shifts, and reverse mix columns of the keyed initial data; (c) key processing the repeated rounded data using the decryption round key; (d) executing a last round process of processing the reverse subbytes and the reverse shift of the keyed repetitive round process data; And (e) outputting plain text generated by performing key processing using the decryption round key on the last rounded data; Decoding method of the AES line Dal algorithm, characterized in that it comprises a. The method of claim 13, wherein step (b) comprises: (b1) the reverse subbyte processing step of returning a substituted operation portion of the cipher text; (b2) the reverse shift processing step of returning a moved row in the matrix of the initial data component; And (b3) the inverse mix column processing step of inversely transforming the additional linearly transformed portion of the cipher text. Decoding method of the AES line Dal algorithm, characterized in that it comprises a. The method of claim 14, The operation to be executed the operation to be executed in the reverse sub-byte process steps _{f-byte sub-station,} in the low-reverse shift processing step if said _{station shifts} f _low, and f _{reverse shift} {f _{reverse subbyte} (Data)} = f _{reverse subbyte} {f _{reverse shift} (Data)} AES linedal algorithm decoding method characterized in that the. The method of claim 13, wherein step (a), step (c) and step (e) A method of decrypting an AES line moon algorithm, characterized in that the round key used for encryption is processed as an inverse mix column and used as the decryption round key. The method of claim 13, The initial data keyed through step (a), the repeated rounded data through step (b) and the last rounded data through step (d) are included in the AES linedal algorithm. A method for decoding an AES line moon algorithm, characterized in that the reception is selectively received from one of the three mux. The method according to claim 16 or 17, The decryption round key used in the step (b), the step (d) and the step (f) is selected from one of three muxes included in the AES linedal algorithm. Decryption method of the algorithm.

Images