KR100666633B1 - Organic electroluminescence device and method for fabricating the same - Google Patents

Abstract

A flat panel display device and a method for manufacturing the same are provided to prevent a lower electrode of a capacitor from being oxidized by not exposing the lower electrode of the capacitor when semiconductor layers are crystallized by an MILC(Metal Induced Lateral Crystallization) scheme. A flat panel display device includes a substrate(200), a thin film transistor(220), a capacitor(230), a second inter layer dielectric, and a contact unit(260). The thin film transistor(220) is formed on the substrate(200), and has a semiconductor layer which is crystallized by the MILC scheme. The capacitor(230) is located on a lower electrode which is located on the same layer with a gate electrode of the thin film transistor(220) and a lower part of the source/drain electrode of the thin film transistor(220). The capacitor(230) has an electric film as a part of a first inter layer dielectric having a first via hole which exposes a part of the lower electrode. The second inter layer dielectric is located on the thin film transistor(220) and the capacitor(230). The second inter layer dielectric has a second via hole which exposes a part of a source/drain electrode of the thin film transistor(220) and a first via hole which exposes a part of the lower electrode of the capacitor(230). The contact unit(260) is located on the second inter layer dielectric. The contact unit(260) is contacted with the lower electrode of the capacitor(230) through the first via hole, and is contacted with the source/drain of the thin film transistor(220) through the second via hole.

Description

Flat panel display device and manufacturing method therefor {Organic electroluminescence device and method for fabricating the same}

1A is a plan view and a cross-sectional view of a flat panel display device according to the prior art;

FIG. 1B is a cross-sectional view of a flat panel display device according to the prior art taken along cut line II ′ of FIG. 1A;

2A is a plan view of a flat panel display device according to an exemplary embodiment of the present disclosure;

FIG. 2B is a cross-sectional view of the flat panel display according to the exemplary embodiment of the present invention taken along the line II ′ of FIG. 2A;

3A to 3E are cross-sectional views illustrating a manufacturing process of a flat panel display device according to an exemplary embodiment of the present disclosure, taken along a cutting line II ′ of FIG. 2A;

4A is a plan view of a flat panel display device according to another exemplary embodiment. FIG. 4B is a cross-sectional view taken along line II-II ′ of FIG. 4A.

 <Description of the symbols for the main parts of the drawings>

200: substrate 211: scan line

212: data line 213: common power line

220: switching thin film transistor 230: capacitor

240: driving thin film transistor 251: first electrode

252: organic film 253: second electrode

380a: first via hole 380b: second via hole

380c: third via hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display and a manufacturing method thereof, and more particularly, to a contact between a source / drain electrode of a switching thin film transistor having a semiconductor layer crystallized by MILC crystallization and a lower electrode of a capacitor.

Recently, a liquid crystal display device, an organic electroluminescence device, or a PDP (plasma display), which solves the shortcomings of the conventional display device, which are heavy and large, such as a cathode ray tube. A flat panel display device, such as a plane, is drawing attention.

At this time, since the liquid crystal display is not a light emitting device but a light receiving device, there is a limit in brightness, contrast, viewing angle, and large area, and although the PDP is a self-light emitting device, it is heavier than other flat panel display devices and consumes more weight. In addition to the high power and complicated manufacturing method, the organic light emitting display device is a self-luminous device, and thus has excellent viewing angle, contrast, etc. Is also advantageous.

In addition, since it is possible to drive a DC low voltage, a fast response speed, and all solid, it is resistant to external shock, wide use temperature range, and has a simple and inexpensive manufacturing method.

1A is a plan view of an organic EL device according to the prior art, and FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A.

Referring to FIG. 1A, a scan line 102, a data line 103 and a common power supply line 104 are positioned on a substrate 101 such as glass or plastic, and the scan line 102 and the data line 103 are located on the substrate 101. And the unit pixel is defined by the common power supply line 104. In this case, the light emitting unit 108 including the switching thin film transistor 105, the capacitor 106, the driving thin film transistor 107 and the first electrode, at least an organic layer including a light emitting layer and a second electrode is located in the unit pixel. have.

Referring to FIG. 1B, the buffer layer 111 is positioned on the substrate 101, and the semiconductor layer 105a of the switching thin film transistor 105 and the driving thin film transistor 107 are disposed in a predetermined region of the buffer layer 111. The semiconductor layer 107a is located. In this case, the semiconductor layers 105a and 107a are polycrystalline silicon layers crystallized by MILC crystallization.

A gate insulating layer 112 is positioned on the semiconductor layers 105a and 107a, and a scan line 102, a gate electrode 105b of the switching thin film transistor 105, and a capacitor are positioned at a predetermined position on the gate insulating layer 112. The lower electrode 106a of the 108 and the gate electrode 107b of the driving thin film transistor 107 are positioned, and the interlayer insulating film 113 is positioned on the element such as the scan line 102.

The data line 103, the source / drain electrodes 105c of the switching thin film transistor 105, the upper electrode 108b of the capacitor 108, and the common power line 104 are disposed on the interlayer insulating layer 113. The passivation layer 114 and the planarization layer 115 are positioned on the device such as the data line 103 and the like, and the first electrode 108a of the light emitting part 108 is disposed on the planarization layer 115. At least the organic layer 108b including the organic emission layer, the second electrode 108c and the pixel defining layer 116 are positioned.

In this case, the semiconductor layers 105a and 107b crystallized by the MILC crystallization method form the interlayer insulating layer 113 and then etch predetermined regions of the interlayer insulating layer 113 and the gate insulating layer 112 to form a contact hole. After forming a metal catalyst, a metal catalyst is applied to predetermined regions of the semiconductor layers 105a and 107b exposed by the contact hole, and then crystallized by heat treatment. In this case, as shown in region A of FIG. 1B, a predetermined region of the lower electrode 106a of the capacitor 106 is a source / drain electrode 105c of the driving thin film transistor 105 of the driving thin film transistor 105. In order to be connected to the semiconductor layer 105a, the contact hole is simultaneously etched and exposed.

Therefore, when the MILC crystallization, that is, during the heat treatment, a problem such as an exposed region of the lower electrode 106a of the capacitor 106 is oxidized, so that the problem of the lower electrode 106a may be solved. The exposed area is protected by a protective film, and then heat treated, and after the heat treatment, a method of performing the process of removing the protective film is performed or first crystallized by MILC crystallization, and then a predetermined region of the lower electrode 106a is exposed. The etching process may be performed separately, but there is a disadvantage in that the process becomes complicated.

Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, having a semiconductor layer that is crystallized by the MILC crystallization method, preventing the problem that the lower electrode of the exposed capacitor is oxidized when the crystallization; It is an object of the present invention to provide a flat panel display and a manufacturing method thereof.

The object of the present invention is a substrate; And a thin film transistor formed on the substrate and including a semiconductor layer crystallized by MILC crystallization. A dielectric layer that is a part of a first interlayer insulating layer including a lower electrode positioned on the same layer as the gate electrode of the thin film transistor and a portion of a first via hole disposed under the source / drain electrode of the thin film transistor and exposing a portion of the lower electrode; A capacitor comprising; A second interlayer insulating layer on the thin film transistor and the capacitor, the second interlayer insulating layer including a second via hole exposing a part of the source / drain electrode of the thin film transistor and a part of the first via hole exposing a part of the lower electrode of the capacitor; And a contact portion disposed on the second interlayer insulating layer, the contact portion contacting a lower electrode of the capacitor through the first via hole and contacting a source / drain of the thin film transistor through the second via hole. do.

In addition, the above object of the present invention comprises the steps of preparing a substrate; Forming an amorphous silicon pattern on the substrate; Forming a gate insulating film on the substrate on which the amorphous silicon pattern is formed; Forming a gate electrode and a lower electrode of the capacitor on the gate insulating film; Forming a first interlayer insulating film on the substrate on which the gate electrode and the lower electrode of the capacitor are formed; Etching the first interlayer insulating film and the gate insulating film to expose a predetermined region of the amorphous silicon pattern; Depositing a metal catalyst on the substrate; Heat treating the substrate to MILC crystallize the amorphous silicon pattern into a polycrystalline silicon pattern; Forming a top electrode of a source / drain electrode and a capacitor on the substrate; Forming a second interlayer insulating film on the substrate; Etching the second interlayer insulating layer to etch a predetermined region of the source / drain electrode and the first interlayer insulating layer and the second interlayer insulating layer to open a predetermined region of the lower electrode of the capacitor; And depositing a first electrode material on the substrate, and patterning the first electrode material to form a contact portion and a first electrode connecting the source / drain electrode and the lower electrode of the capacitor. It is also achieved by a flat panel display device manufacturing method.

The object of the present invention is to prepare a substrate; Forming a gate electrode and a lower electrode of the capacitor on the substrate; Forming a first interlayer insulating film on the substrate on which the gate electrode is formed; Forming an amorphous silicon pattern on the gate insulating film; Depositing a metal catalyst on the substrate on which the amorphous silicon pattern is formed; Heat treating the substrate to crystallize MILC into a polycrystalline silicon pattern; Forming a source / drain electrode and an upper electrode of a capacitor on the substrate on which the polycrystalline silicon layer is formed; Forming a second interlayer insulating film on the substrate on which the source / drain electrodes and the upper electrode of the capacitor are formed; Etching the second interlayer insulating layer to etch a predetermined region of the source / drain electrode and the first interlayer insulating layer and the second interlayer insulating layer to open a predetermined region of the lower electrode of the capacitor; And depositing a first electrode material on the substrate, and patterning the first electrode material to form a contact portion and a first electrode connecting the source / drain electrode and the lower electrode of the capacitor. It is also achieved by a flat panel display device manufacturing method.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention. In the drawings, the length, thickness, etc. of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

FIG. 2A is a plan view of a flat panel display device according to an exemplary embodiment, and FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 2A.

Referring to FIG. 2A, a scan line 211, a data line 212, and a common power line 213 are positioned on a substrate 200 such as glass or plastic, and the scan line 211 and the data line 212 are located therein. And the unit pixel is defined by the common power supply line 213. In this case, the pixel unit 250 including the switching thin film transistor 220, the capacitor 230, the driving thin film transistor 240, and at least a first electrode is positioned in the unit pixel. In this case, when the organic layer including the light emitting layer and the second electrode are disposed on the first electrode, the organic electroluminescent element of the flat panel display device is represented.

In this case, the semiconductor layer 221 of the switching thin film transistor 220 and the semiconductor layer 231 of the driving thin film transistor are composed of polycrystalline silicon layers crystallized by a MILC crystallization method.

At this time, in the present invention, the switching thin film transistor 220 and the lower electrode of the capacitor 230 are connected to the contact portion 260 made of the same material as the first electrode of the light emitting part 250.

Referring to FIG. 2B, a buffer layer 201 is positioned on a substrate 200 such as glass or plastic.

The semiconductor layer 221 of the switching thin film transistor 220 and the semiconductor layer 241 of the driving thin film transistor 240 are positioned on the buffer layer 201 by a metal induced lateral crystallization (MILC) crystallization method.

A gate insulating layer 202 is disposed on the semiconductor layers 221 and 241, a scan line 211, a gate electrode 222 of the switching thin film transistor 220, and a capacitor are disposed on the gate insulating layer 202. The lower electrode 231 of the 230 and the semiconductor layer 242 of the driving thin film transistor 240 are positioned, and the interlayer insulating layer 203, which is a first interlayer insulating layer, is positioned on the gate electrodes 222 and 242.

The data line 212, the source / drain electrode 223 of the switching thin film transistor 220, the upper electrode 232 of the capacitor 230, the common power line 213, and the data line 212 are disposed on the interlayer insulating layer 203. A source / drain electrode 243 of the driving thin film transistor 240 is positioned, and a second interlayer insulating layer such as a passivation layer 204 or a planarization layer 205 is positioned on the source thin film transistor 240.

The contact portion 260 and the first electrode 251 are positioned on the second interlayer insulating layer. In this case, when the flat panel display device of the present invention is an organic electroluminescent device, a pixel defining layer 206 exposing a predetermined region of the first electrode 251 is positioned on the first electrode 251, and the first electrode 251 is positioned. An organic layer 252 and a second electrode 253 including at least an organic emission layer may be disposed on the electrode 251.

In this case, the gate electrode 222 of the switching thin film transistor 220 has the scan line 211, and the source electrode 223a of the switching thin film transistor 220 has the data line 212 and the switching thin film transistor. The drain electrode 223b of 220 is a lower electrode 231 of the capacitor 230, the gate electrode 242 of the driving thin film transistor 240 is a lower electrode 231 of the capacitor 230, The source electrode 243a of the driving thin film transistor 240 includes the upper electrode 232 and the common power line 213 of the capacitor 230, and the drain electrode 243b of the driving thin film transistor 240 includes a first electrode. It is electrically connected to the electrode 251.

In this case, the drain electrode 223b of the switching thin film transistor 220 and the lower electrode 231 of the capacitor 230 are connected by the contact part 260, and the contact part 260 is connected to the first electrode. 251 is formed at the same time. That is, when the first via hole exposing a predetermined region of the lower electrode 231 of the capacitor 230 is formed, the second via hole exposing a predetermined region of the drain electrode 223b of the switching thin film transistor 220; After the third via hole exposing the drain electrode 243b of the driving thin film transistor 240 is formed at the same time, the first electrode material is deposited and patterned to form the contact portion 260 and the first electrode 251. .

Therefore, when the semiconductor layers 221 and 241 are crystallized by the MILC crystallization method, part of the lower electrode 231 of the capacitor 230 is not exposed so that the lower electrode 231 is oxidized by heat treatment. You can prevent it. In this case, the first electrode material is a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

3A to 3E are cross-sectional views illustrating a manufacturing process of a flat panel display device according to an exemplary embodiment.

Referring to FIG. 3A, a buffer layer 301 is formed on a substrate 300 such as glass or plastic using a physical vapor deposition device or a chemical vapor deposition device as a silicon oxide film, a silicon nitride film, or a multilayer thereof. In this case, the buffer layer 201 serves to prevent crystallization of the semiconductor layer by preventing diffusion of moisture or impurities generated from the lower substrate or by controlling the rate of heat transfer during crystallization.

Subsequently, an amorphous silicon layer is deposited on the buffer layer 301 and then patterned to form a first amorphous silicon pattern 321a and a second amorphous silicon pattern 341a.

Subsequently, a gate insulating layer 302 is formed on the substrate 300.

Subsequently, a first conductive layer is deposited on the substrate 300 on which the gate insulating layer 302 is formed, and then patterned and formed on a predetermined region corresponding to the scan line 311 and the first amorphous silicon pattern 321a. A second gate electrode 342 is formed on a predetermined region corresponding to the first gate electrode 322, the lower electrode 331 of the capacitor, and the second amorphous silicon pattern 341a.

Subsequently, an interlayer insulating film 303 that is a first interlayer insulating film is formed over the entire surface of the substrate 300.

Subsequently, the contact holes 370 exposing predetermined regions of the first amorphous silicon pattern 321a and the second amorphous silicon pattern 341a are etched by etching predetermined regions of the interlayer insulating layer 303 and the gate insulating layer 301. Form.

Referring to FIG. 3B, a metal catalyst is deposited on a substrate on which the contact hole 370 is formed, and then heat-treated to form the first amorphous silicon pattern 321a and the second amorphous silicon pattern 341a with a MILC crystallization method. Crystallization is performed to form the first polycrystalline silicon pattern 321b and the second polycrystalline silicon pattern 341b. Conventionally, when the contact hole 370 is formed, a via hole for exposing a predetermined area of the lower electrode 331 of the capacitor is simultaneously formed, but the exposed lower electrode generated when crystallized by the MILC crystallization method ( In order to prevent oxidation of 331, only the contact holes 370 of the first amorphous silicon pattern 321a and the second amorphous silicon pattern 341a are formed and crystallization is performed.

At this time, the metal catalyst uses any one or more of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd or Pt.

Referring to FIG. 3C, after the crystallization process, a second conductor is deposited on the entire surface of the substrate 300, and then patterned to form a scan line 212, a first source / drain electrode 323, and an upper electrode of the capacitor. 332, a common power supply line 313, and a second source / drain electrode 343 are formed.

In this case, the first polycrystalline silicon layer 312b, the first gate electrode 322, and the first source / drain electrode 323 may include the semiconductor layer of the switching thin film transistor 221 described above with reference to FIG. 2A or 2B. 221, a gate electrode 222, and a source / drain electrode 223, and the second polycrystalline silicon layer 341b, the second gate electrode 342, and the second source / drain electrode 343 are illustrated in FIG. The semiconductor layer 241, the gate electrode 242, and the source / drain electrode 243 of the driving thin film transistor 241 described above with reference to FIG. 2A or 2B may correspond to each other.

Subsequently, a second interlayer insulating film such as a passivation layer 304 or a planarization layer 305 is deposited over the entire surface of the substrate. In this case, the passivation layer 304 serves to protect other layers or devices at the bottom, and the planarization layer 305 serves to remove morphology generated by other layers or devices at the bottom.

Subsequently, the second interlayer insulating layer 303 and the interlayer insulating layer 303 such as the passivation layer 304 or the planarization layer 305 are etched to etch a predetermined region of the lower electrode 331 of the capacitor, and the first source / drain electrode ( A first via hole 380a, a second via hole 380b, and a third via hole 380c are formed to expose a predetermined region of the 323 and the predetermined region of the second source / drain electrode 343.

Referring to FIG. 3D, a first electrode material is deposited on the substrate 300 on which the via holes 380a, 380b, and 380c are formed, and the first electrode material is patterned to expose the lower electrode 331. A third via hole exposing a portion of the contact portion 360 and a portion of the second source / drain electrode 343 connecting the first via hole 380a to the second via hole 380b exposing the first source / drain electrode. A first electrode 351 connected to the second source / drain electrode 343 is formed through 380c. Accordingly, the contact connecting the lower electrode of the switching thin film transistor and the capacitor of the present invention is not directly connected to the source / drain electrode of the switching thin film transistor as in the conventional art, but the source / drain electrode of the driving thin film transistor when the first electrode is formed. When the third via hole 280c is formed, the first via hole 380a exposing the lower electrode of the capacitor and the second via hole 380b exposing a part of the source / drain electrode of the switching thin film transistor are simultaneously formed. It is formed by depositing a first electrode material to form the contact portion 360 simultaneously with forming the first electrode.

Referring to FIG. 3E, the pixel defining layer 306 is formed on the substrate 300 on which the contact portion 360 and the first electrode 351 are formed to expose a predetermined region of the first electrode 351. An organic layer 352 including at least a light emitting layer and a second electrode 353 may be formed on the exposed first electrode 351 to complete an organic EL device, which is one of the flat panel display devices.

<Example 2>

4A is a plan view of a flat panel display device according to an exemplary embodiment, and FIG. 4B is a cross-sectional view taken along the line II-II ′ of FIG. 4A.

Referring to FIG. 4A, a scan line 411, a data line 412, and a common power line 413 are positioned on a substrate 400 such as glass or plastic, and the scan line 411 and the data line 412 are located on the substrate 400. And the unit pixel is defined by the common power supply line 413. In this case, the pixel unit 450 including the switching thin film transistor 420, the capacitor 430, the driving thin film transistor 440, and at least a first electrode is positioned in the unit pixel. In this case, when the organic layer including the light emitting layer and the second electrode are disposed on the first electrode, the organic electroluminescent element of the flat panel display device is represented.

In this case, the semiconductor layer 421 of the switching thin film transistor 420 and the semiconductor layer 431 of the driving thin film transistor are composed of polycrystalline silicon layers crystallized by MILC crystallization.

At this time, in the present invention, the switching thin film transistor 420 and the lower electrode of the capacitor 430 are connected to a contact part 460 made of the same material as the first electrode of the light emitting part 450.

In this case, the present embodiment differs from the first embodiment in that the switching thin film transistor 420 and the driving thin film transistor 440 are bottom gate type thin film transistors.

Referring to FIG. 4B, a buffer layer 401 is positioned on a substrate 400 such as glass or plastic.

The scan line 411 on the buffer layer 401, the gate electrode 422 of the switching thin film transistor 420, the lower electrode 431 of the capacitor 430, and the gate electrode of the driving thin film transistor 440 ( 442 is positioned, and a gate insulating layer 402, which is a first interlayer insulating layer, is disposed on the gate electrodes 422 and 442. In this case, a portion of the gate insulating layer 402 disposed on the lower electrode 431 is used as the dielectric layer of the capacitor 430.

The semiconductor layer 421 of the switching thin film transistor 420 and the semiconductor layer 441 of the driving thin film transistor 440 are positioned on the gate insulating layer 402 by crystallization (Metal Induced Lateral Crystallization). . In this case, the semiconductor layers 421 and 441 may be composed of active layers 421a and 441a and ohmic contact layers 421b and 441b. In this case, the semiconductor layers 421 and 441 may be any one of a back channel etched (BCE) structure or an etch stopper (ES) structure. In this embodiment, the BCE structure is illustrated.

The data line 412 on the substrate on which the semiconductor layers 421 and 441 are formed, the source / drain electrode 423 of the switching thin film transistor 420, the upper electrode 432 of the capacitor 430, and a common power source. A line 413 and a source / drain electrode 443 of the driving thin film transistor 440 are positioned, and a second interlayer insulating layer such as a passivation layer 404 or a planarization layer 405 is positioned thereon.

The contact portion 460 and the first electrode 451 are positioned on the second interlayer insulating layer. In this case, when the flat panel display device of the present invention is an organic electroluminescent device, a pixel defining layer 406 exposing a predetermined region of the first electrode 451 is disposed on the first electrode 451, and the first electrode 451 is disposed. An organic layer 452 and a second electrode 453 including at least an organic emission layer may be disposed on the electrode 451.

In this case, the drain electrode 423b of the switching thin film transistor 420 and the lower electrode 431 of the capacitor 430 are connected by the contact part 460, and the contact part 460 is connected to the first electrode. It is formed at the same time as 451. That is, a predetermined region of the planarization layer 405 and the passivation layer 404 as the second interlayer insulating layer and the gate insulating layer 402 as the first interlayer insulating layer are etched to form a predetermined region of the lower electrode 431 of the capacitor 430. When the first via hole 470a is exposed, the second interlayer insulating layer is etched to expose a predetermined region of the drain electrode 423b of the switching thin film transistor 420 and the driving thin film transistor. After the third via hole 470c exposing the drain electrode 443b of 440 is formed at the same time, the first electrode material is deposited and patterned to form the contact portion 460 and the first electrode 451.

In this case, the fabrication process of Example 2 includes forming a buffer layer 401 on the substrate 400, a scan line 411 on the buffer layer 401, a gate electrode 422 of a switching thin film transistor, and a capacitor. Forming a lower electrode 431 of the gate electrode and a gate electrode 442 of the driving thin film transistor; and a gate insulating film as a first interlayer insulating layer on a substrate on which the gate electrodes 422 and 442 and the lower electrode 431 of the capacitor are formed. (402) forming an amorphous silicon pattern on the gate insulating film 402, depositing a metal catalyst on the substrate on which the amorphous silicon pattern is formed, and heat treating the substrate to form the amorphous silicon pattern as a polycrystalline silicon pattern. MILC crystallization to form the semiconductor layer 421 and a source / drain electrode 423 of the switch thin film transistor on the substrate on which the semiconductor layer 421 is formed, and an upper portion of the capacitor. Electrode 432, only the step of forming the common power line 413 and data line 412 is only different from the above <Example 1> The rest is the same.

Therefore, when the semiconductor layers 421 and 441 are crystallized by the MILC crystallization method, part of the lower electrode 431 of the capacitor 430 is not exposed so that the lower electrode 431 is oxidized by heat treatment. You can prevent it. In this case, the first electrode material is a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Accordingly, in the organic electroluminescent device of the present invention, when the semiconductor layer of the thin film transistor is crystallized by the MILC crystallization method, the lower electrode of the capacitor is not exposed and the lower electrode is prevented from being oxidized. By simultaneously forming a contact portion for contacting the thin film transistor and the lower electrode of the capacitor, the contact portion can be formed without increasing the process step.

The present invention has been shown and described with reference to the preferred embodiments as described above, but is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

Therefore, the organic electroluminescent device of the present invention and its manufacturing method do not expose the lower electrode of the capacitor when crystallized by the MILC crystallization method, the effect that can solve the problem that the lower electrode of the capacitor is oxidized without increasing the process step There is.

Claims (14)

Board; And A thin film transistor formed on the substrate and including a semiconductor layer crystallized by MILC crystallization; A dielectric layer that is a part of a first interlayer insulating layer including a lower electrode positioned on the same layer as the gate electrode of the thin film transistor and a portion of a first via hole disposed under the source / drain electrode of the thin film transistor and exposing a portion of the lower electrode; A capacitor comprising; A second interlayer insulating layer on the thin film transistor and the capacitor, the second interlayer insulating layer including a second via hole exposing a portion of the source / drain electrodes of the thin film transistor and a portion of the first via hole exposing a portion of the lower electrode of the capacitor; And A contact portion disposed on the second interlayer insulating layer and contacting the lower electrode of the capacitor through the first via hole and contacting the source / drain of the thin film transistor through the second via hole; A flat panel display comprising a. The method of claim 1, And a first electrode formed of the same material as the contact portion on the second interlayer insulating layer. The method of claim 2, And a second electrode and an organic layer including at least a light emitting layer on the first electrode.  The method of claim 2, And the first electrode is made of ITO or IZO. The method of claim 1, And the first interlayer insulating film is a gate insulating film. The method of claim 1, And the second interlayer dielectric layer is at least one of a passivation layer and a planarization layer. The method of claim 1, And the MILC crystallization method is a crystallization method using a metal catalyst deposited on the semiconductor layers exposed by source / drain electrode contact holes of the thin film transistor. The method of claim 7, wherein The metal catalyst is at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd or Pt. The method of claim 1, The thin film transistor may be a switching thin film transistor or a driving thin film transistor. The method of claim 9, And the switching thin film transistor is connected to a scan line and a data line. The method of claim 9, And the driving thin film transistor is connected to a lower electrode of the capacitor, a common power line connected to the upper electrode of the capacitor, and the first electrode. Preparing a substrate; Forming an amorphous silicon pattern on the substrate; Forming a gate insulating film on the substrate on which the amorphous silicon pattern is formed; Forming a gate electrode and a lower electrode of the capacitor on the gate insulating film; Forming a first interlayer insulating film on the substrate on which the gate electrode and the lower electrode of the capacitor are formed; Etching the first interlayer insulating film and the gate insulating film to expose a predetermined region of the amorphous silicon pattern; Depositing a metal catalyst on the substrate; Heat treating the substrate to MILC crystallize the amorphous silicon pattern into a polycrystalline silicon pattern; Forming a top electrode of a source / drain electrode and a capacitor on the substrate; Forming a second interlayer insulating film on the substrate; Etching the second interlayer insulating layer to etch a predetermined region of the source / drain electrode and the first interlayer insulating layer and the second interlayer insulating layer to open a predetermined region of the lower electrode of the capacitor; And Depositing a first electrode material on the substrate and patterning the first electrode material to form a contact portion and a first electrode connecting the source / drain electrode and the lower electrode of the capacitor; Flat panel display device manufacturing method comprising a. Preparing a substrate; Forming a gate electrode and a lower electrode of the capacitor on the substrate; Forming a first interlayer insulating film on the substrate on which the gate electrode is formed; Forming an amorphous silicon pattern on the gate insulating film; Depositing a metal catalyst on the substrate on which the amorphous silicon pattern is formed; Heat treating the substrate to crystallize MILC into a polycrystalline silicon pattern; Forming a source / drain electrode and an upper electrode of a capacitor on the substrate on which the polycrystalline silicon layer is formed; Forming a second interlayer insulating film on the substrate on which the source / drain electrodes and the upper electrode of the capacitor are formed;  Etching the second interlayer insulating layer to etch a predetermined region of the source / drain electrode and the first interlayer insulating layer and the second interlayer insulating layer to open a predetermined region of the lower electrode of the capacitor; And Depositing a first electrode material on the substrate and patterning the first electrode material to form a contact portion and a first electrode connecting the source / drain electrode and the lower electrode of the capacitor; Flat panel display device manufacturing method comprising a. The method according to claim 12 or 13, After forming the first electrode, And forming a pixel defining layer, an organic layer including at least an organic emission layer, and a second electrode on the first electrode.

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