KR100662983B1 - Scan driving circuit and organic light emitting display using the same - Google Patents

Abstract

A scan driving circuit and an organic electroluminescence device using the same are provided to improve the waveform of an output signal by forming multiple stages for outputting selection and boot signals in order and to reduce power consumption by removing a static current flowing path. A first scan driving unit outputs a selection signal or a boost signal in order through multiple stages. Each stage of the first scan driving unit includes a first transistor(M1) receiving the output voltage of the previous stage or a first input signal and having a gate terminal connected to a first clock terminal; a second transistor(M2) provided with a gate terminal connected to the output stage of the first transistor and connected to a second clock terminal and an output line(OUT); a third transistor(M3) provided with a gate terminal connected to the first clock terminal and connected between a second power source(VSS) and a first node; a fourth transistor(M4) provided with a gate terminal connected to the output stage of the first transistor and connected between the first clock terminal and the first node; a fifth transistor(M5) provided with a gate terminal connected to the first node and connected between a first power source(VDD) and the output line; a sixth transistor(M6) provided with a gate terminal connected to the output stage of the first transistor and connected to a third power source input line and a boost signal output line; a seventh transistor(M7) provided with a gate terminal connected to the first node and connected between the first power source and the boost signal output line; and an eighth transistor(M8) provided with a gate terminal connected to the second clock terminal and connected between the sixth and seventh transistors.

Description

Scan driving circuit and organic light emitting device using same

1 is a block diagram showing the structure of a conventional general scan driving circuit.

FIG. 2 is a circuit diagram of an arbitrary stage in the scan driving circuit shown in FIG.

3 is an input / output signal waveform diagram of the stage shown in FIG.

4 is a block diagram schematically showing an organic electroluminescent device according to an embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an example embodiment of a pixel circuit provided in each pixel area of the organic electroluminescent device illustrated in FIG. 4.

6 is a timing diagram of a selection signal, a light emission signal, and a boost signal input to the pixel circuit of FIG. 5.

Fig. 7 is a block diagram showing the configuration of a first scan driver of the scan driver circuit according to the first embodiment of the present invention.

Fig. 8 is a circuit diagram of a first stage of a scan driving unit of the first scan driving unit according to the first embodiment of the present invention.

9 is a timing diagram of input / output signals of the stage shown in FIG. 8; FIG.

Fig. 10 is a circuit diagram of the first to fourth stages of the boost drive unit of the first scan drive unit according to the first embodiment of the present invention.

FIG. 11 is a timing diagram of input / output signals of the stage shown in FIG. 10; FIG.

12 is a timing diagram of signals input / output to each stage of the first scan driver according to the first embodiment of the present invention;

Fig. 13 is a block diagram showing the configuration of a first scan driver of a scan driver circuit according to a second embodiment of the present invention;

Fig. 14 is a circuit diagram of an arbitrary stage in the first scan driver according to the second embodiment of the present invention.

FIG. 15 is a timing diagram of input / output signals of the stage shown in FIG. 14; FIG.

Fig. 16 is a circuit diagram of an arbitrary stage in the first scan driver according to the third embodiment of the present invention.

FIG. 17 is a timing diagram of input / output signals of the stage shown in FIG. 16; FIG.

Fig. 18 is a circuit diagram of an arbitrary stage in the first scan driver according to the fourth embodiment of the present invention.

FIG. 19 is a timing diagram of input / output signals of the stage shown in FIG. 18; FIG.

Fig. 20 is a block diagram showing the configuration of a first scan driver of a scan driver circuit according to a fifth embodiment of the present invention.

Fig. 21 is a circuit diagram of an arbitrary stage in the first scan driver according to the fifth embodiment of the present invention.

FIG. 22 is a timing diagram of input / output signals of the stage shown in FIG. 21; FIG.

<Explanation of symbols for the main parts of the drawings>

300: scan drive circuit 310: first scan driver

320: second scan drive unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to organic electroluminescent devices, and more particularly, to a scan drive circuit used in a current write-type organic electroluminescent device.

In general, an organic electroluminescent device is a display device for electrically exciting a fluorescent organic compound to emit light, and is capable of representing an image by voltage or current writing M * N organic light emitting cells. The organic light emitting cell has a structure of an anode (ITO), an organic thin film, and a cathode layer (metal).

The organic thin film has a multilayer structure including an emission layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) to improve the emission efficiency by improving the balance between electrons and holes. It also includes a separate electron injection layer (EIL) and a hole injection layer (HIL).

As such a method of driving the organic light emitting cell, there are a simple matrix method and an active matrix method using a thin film transistor (TFT). In the simple matrix method, the anode and the cathode are orthogonal and the line is selected and driven, whereas the active driving method connects the thin film transistors to each indium tin oxide (ITO) pixel electrode and the capacitance of the capacitor connected to the gate of the thin film transistor. Is driven according to the maintained voltage.

At this time, the active driving method is divided into a voltage programming method and a current programming method according to the type of the signal applied to set the voltage to the capacitor.

Such an active driving type organic electroluminescent device includes a display panel, a data driving circuit, a scan driving circuit, and a timing controller. The scan driving circuit receives a scan driving control signal from the timing controller and scans the scan driving circuit. The driving circuit generates a scan signal and sequentially supplies the generated scan signal to the scan lines of the display panel.

That is, the scan driving circuit sequentially generates the scan signal and provides the scan signal to the panel to drive the plurality of pixels provided in the panel.

1 is a block diagram showing the structure of a conventional general scan driving circuit.

Referring to FIG. 1, a conventional scan driving circuit includes a plurality of stages ST1 to STn connected dependently to a start pulse input line, and the plurality of stages ST1 to STn are start pulses. The SP is sequentially shifted in accordance with the clock signal C to generate output signals SO1 to SOn. In this case, each of the second to nth stages ST2 to STn receives the front end output signal as a start pulse and shifts it.

Accordingly, the stages generate output signals SO1 to SOn in which the start pulses are sequentially shifted, and provide them to the matrix pixel array.

FIG. 2 is a circuit diagram of an arbitrary stage in the scan driving circuit shown in FIG. 1, and FIG. 3 is an input / output signal waveform diagram of the stage shown in FIG.

2 and 3, each stage constituting the scan driver circuit uses a flip-flop in the form of a master-slave. This flip-flop continues to receive input when the clock clk is at the low level, and the output retains its previous output.

On the other hand, when the clock clk is at the high level, the input IN retained when the clock clk is at the low level is outputted to the output and no further input is received.

In such a circuit, in the case of an inverter provided inside the flip-flop, there is a problem that a static current flows when the input in is at a low level. In addition, since the number of inverters receiving a high level input (in) and an inverter receiving a low level input (in) is the same in the flip-flop, the static current is generated in the half of the inverters inside the flip-flop to increase the power consumption. There are disadvantages.

In the circuit of FIG. 3, the high level of the output voltage OUT is determined by the ratio of the resistance connecting the supply voltage VDD and the ground GND to a voltage value (ratioed logic), and the output voltage OUT. The low level of H is higher than the threshold of the transistor by the ground voltage.

That is, since the input voltage level to be accepted at the high level is different for each stage according to the variation of the characteristics of the transistor, if such a circuit is adopted, there is a disadvantage that the circuit may malfunction due to a deviation in the high level of the output voltage.

In addition, the low level deviation of the output voltage may be reflected as a deviation of the on resistance of the input transistor T1 of the inverter included in the circuit of FIG. 2 to increase the high level deviation of the output voltage. In particular, the organic electroluminescent device panel uses a transistor having a large variation in characteristics, thereby making the problem worse.

In addition, the inverter discharges current through the input transistor T1 to charge the output terminal, and current flows through the load transistor T2 to discharge the output terminal. When the output terminal is charged, the load transistor is charged. As the source-gate voltage of (T2) decreases gradually, the discharge current decreases rapidly, resulting in a decrease in discharge efficiency.

The present invention provides a scan driving circuit for providing a selection signal and / or a boost signal in an active driving current write type organic electroluminescent device, comprising: a multi-stage stage for sequentially outputting the selection signal and the boost signal; It is an object of the present invention to provide a scan driving circuit which reduces power consumption by improving a signal waveform and eliminating a path through which static current can flow to the stage, and an organic electroluminescent device using the same.

In addition, a scan driving circuit and an organic electroluminescent device using the same are configured to set the current I _OLED supplied to the organic EL element _OLED to a desired value by freely adjusting the pulse width and the swing of the boost signal. The purpose is to provide.

In order to achieve the above object, the first aspect of the present invention provides a scan driving circuit comprising a plurality of stages connected to an input signal line or a previous stage output voltage line and connected to a clock signal input line. A first scan driver for sequentially outputting a selection signal or a boost signal through a stage of the first scan driver, wherein each stage of the first scan driver for outputting the boost signal receives a previous output voltage or an initial input signal; A first transistor M1 having a gate terminal connected to one clock terminal; A second transistor (M2) connected to an output terminal of the M1 and connected to a second clock terminal and an output line (OUT); A third transistor (M3) connected with a gate terminal to the first clock terminal and connected between a second power supply (VSS) and a first node (N1); A fourth transistor (M4) connected to a gate terminal of the output terminal of the M1 and connected between the first clock terminal and the first node (N1); A fifth transistor (M5) connected to a gate terminal of the first node (N1) and connected between a first power source (VDD) and the output line (OUT); A sixth transistor M6 connected to an output terminal of the M1 and connected to a third power supply VL input line and a boost signal output line BST; A seventh transistor (M7) connected to a gate terminal of the first node (N1) and connected between a first power supply (VDD) and the boost signal output line (BST); A gate driving terminal is connected to the second clock terminal, and an eighth transistor M8 connected between the M6 and M7 is included.

In addition, the second aspect of the present invention is a scan driving circuit composed of multiple stages connected to an input signal line or a previous stage output voltage line and connected to a clock signal input line, respectively. And a first scan driver for sequentially outputting a selection signal and a boost signal, wherein each stage of the first scan driver receives a previous output voltage or an initial input signal, and has a gate terminal connected to the first clock terminal. A first transistor M1; A second transistor (M2) connected to an output terminal of the M1 and connected to a second clock terminal and an output line (OUT); A third transistor (M3) connected with a gate terminal to the first clock terminal and connected between a second power supply (VSS) and a first node (N1); A fourth transistor (M4) connected to a gate terminal of the output terminal of the M1 and connected between the first clock terminal and the first node (N1); A fifth transistor (M5) connected to a gate terminal of the first node (N1) and connected between a first power source (VDD) and the output line (OUT); A sixth transistor M6 connected to an output terminal of the M1 and connected to a third power supply VL input line and a boost signal output line BST; A seventh transistor (M7) connected to a gate terminal of the first node (N1) and connected between a first power supply (VDD) and the boost signal output line (BST); An eighth transistor (M8) connected to the second clock terminal and connected between the M6 and M7; A ninth transistor M9 connected to an output terminal of the M1 and connected to a selection control signal input line and a selection signal output line SEL; A scan driving circuit comprising a gate terminal connected to the first node N1 and a tenth transistor M10 connected between a first power supply VDD and the selection signal output line SEL. To provide.

The third aspect of the present invention also includes a pixel portion including a plurality of pixels positioned to be connected to selection signal lines, data lines, light emission signal lines, and boost signal lines; A data driver circuit for supplying a data signal to the data lines; A first scan driver comprising a plurality of stages connected to a clock signal input line and sequentially outputting a selection signal or a boost signal through the stages; A scan driving circuit including a second scanning driver for sequentially outputting a light emission signal through the stage of the multi-stage,

Each stage of the first scan driver for outputting the boost signal includes: a first transistor (M1) receiving a previous output voltage or an initial input signal and having a gate terminal connected to the first clock terminal; A second transistor (M2) connected to an output terminal of the M1 and connected to a second clock terminal and an output line (OUT); A third transistor (M3) connected with a gate terminal to the first clock terminal and connected between a second power supply (VSS) and a first node (N1); A fourth transistor (M4) connected to a gate terminal of the output terminal of the M1 and connected between the first clock terminal and the first node (N1); A fifth transistor (M5) connected to a gate terminal of the first node (N1) and connected between a first power source (VDD) and the output line (OUT); A sixth transistor M6 connected to an output terminal of the M1 and connected to a third power supply VL input line and a boost signal output line BST; A seventh transistor (M7) connected with a gate terminal of the first node (N1) and connected between a first power supply (VDD) and the boost signal output line (BST); A gate terminal is connected to the second clock terminal, and an eighth transistor M8 connected between the M6 and M7 is included.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram schematically illustrating an organic electroluminescent device according to an embodiment of the present invention.

As shown in FIG. 4, the organic electroluminescent device according to the exemplary embodiment of the present invention includes an organic EL display panel (hereinafter, referred to as a display panel) 100, a data driver circuit 200, and a scan driver circuit. The scan driver 300 includes a first scan driver 310 for providing a selection signal and / or a boost signal, and a second scan driver 320 and 320 for providing a light emission signal.

However, the first scan driver 310 may be separately configured as a scan driving unit and a boost driving unit so as to separately output a selection signal and a boost signal, and in this case, the boost driving unit outputting the boost signal is an odd number. And separated again to separate and output the even-numbered boost signal.

The display panel 100 includes a plurality of data lines D ₁ -D _n extending in a column direction and a plurality of signal lines S ₁ -S _m , E ₁ -E _m, and B ₁ -B extending in a row direction. _m ), and a plurality of pixel circuits 110 formed in a matrix shape.

Here, the signal lines may include a plurality of selection signal lines S _1- S _m which transmit a selection signal for selecting a pixel, and a plurality of light emission signal lines E _1- which transmit a light emission signal for controlling the light emission period of the organic EL element. E _m ) and a plurality of boost signal lines B ₁ -B _m transmitting a boost signal for setting the gate voltage of the driving thin film transistor m1 to a desired value.

The pixel circuits 110 are respectively arranged in pixel areas defined by the data lines D ₁ -D _n and the scan, light emission, and boost signal lines S ₁ -S _m , E ₁ -E _m, and B ₁ -B _m . ) Is formed.

The data driver circuit 200 applies the data current I _DATA to the data lines D ₁ -D _n , and the first scan driver 310 of the scan driver circuit 300 selects the signal lines S ₁ -S _m. ), A selection signal for selecting a pixel circuit is sequentially applied, and a boost signal for setting the gate voltage of the driving thin film transistor m1 of the pixel circuit to a desired value is sequentially applied to the boost signal lines B ₁ -B _m . do.

In addition, the second scan driver 320 of the scan driving circuit 300 sequentially applies a light emission signal for controlling the luminance of the pixel circuit 110 to the light emission signal lines E ₁ -E _m .

FIG. 5 is a circuit diagram illustrating an example embodiment of a pixel circuit provided in each pixel area of the organic electroluminescent device illustrated in FIG. 4.

In FIG. 5, only the pixel circuit connected to the j th data line D _j and the i th signal line S _i , E _i , B _i is illustrated for convenience of description.

As shown in FIG. 5, the pixel circuit 110 according to the exemplary embodiment of the present invention includes an organic EL element OLED, transistors m1-m4, and capacitors C1 and C2. Here, a PMOS transistor is used as the transistors m1-m4, but the present invention is not limited thereto.

The first transistor m1 is connected between the power supply VDD and the organic EL element OLED to control the current flowing through the organic EL element. Specifically, the source of the transistor m1 is connected to the power supply VDD, and the drain is connected to the cathode of the organic EL element OLED through the transistor m3.

In addition, the second transistor (m2) passes the data signal from the selection signal line in response to the selection signal from the (S _i) the data lines (D _j) to the gate of the first transistor (m1), and a fourth transistor (m4 ) Diode-connects the first transistor m1 in response to the selection signal.

In addition, the first capacitor C2 is connected between the gate and the source of the first transistor m1 to charge a voltage corresponding to the data current I _DATA from the data line D _j , and the third transistor m3. ) Transmits a current flowing in the first transistor m1 to the organic EL element OLED in response to the light emission signal from the light emission signal line E _i .

Further, the second capacitor C2 is connected between the gate of the first transistor m1 and the boost signal line _Bi .

At this time, the voltage of the node of the second capacitor C2 is increased by the voltage rising width (-V _B ) of the boost signal from the boost signal line _Bi , so that the gate voltage V _G of the first transistor m1 is increased. The amount of increase (-V _G ) becomes as in Equation 1. Therefore, in response to the parasitic capacitance components of the transistors m1, m2, and m4, the voltage rising width (-V _B ) of the boost signal is adjusted to obtain the rising width (-V _G ) of the gate voltage V _G of the transistor m1. Can be set. That is, the current I _OLED supplied to the organic EL element OLED can be set to a desired value.

6 is a timing diagram of a selection signal, a light emission signal, and a boost signal input to the pixel circuit of FIG. 5.

5 and 6, the selected signal lines (S _n) is the first and the fourth transistor (m2, m4) by a select signal turns on the first transistor (m1) is passed the data current (I _DATA) in The third transistor m3 needs to be turned off during this time. If the third transistor m3 is turned on while the data current I _DATA is transmitted to the first transistor m1 and current flows in the organic EL element OLED, the data current flows to the drain of the first transistor m1. A current corresponding to the difference between I _DATA and the current flowing in the organic EL element OLED flows, and a voltage corresponding to the current is written in the capacitor C1.

Accordingly, as shown in FIG. 6, when the end of the emission signal pulse of the emission signal line En comes later than the end of the pulse of the selection signal of the selection signal line Sn, the third transistor m2 is turned on. Transistor m3 is not turned on.

That is, in the case of the present invention, the low level pulse width of the selection signal is applied about 2 us less than the horizontal period on the basis of the horizontal period, whereas the high level pulse width of the light emission signal corresponds to the low level pulse width of the selection signal. It is greatly applied to include all of them.

When the end of the pulse of the boost signal from the boost signal line B _n comes earlier than the end of the pulse of the selection signal, the writing of the data current I _DATA is completed after the node voltage of the second capacitor C2 rises. The effect of raising the node voltage of the capacitor C2 is lost. Accordingly, in the present invention, as shown in FIG. 6, when the pulse end of the selection signal transmitted to the selection signal line S _n comes earlier than the pulse end of the boost signal transmitted to the boost signal line B _n , the data current ( After writing I _DATA , the node voltage of capacitor C2 rises.

In addition, when the start of the pulse of the boost signal comes later than the start of the pulse of the selection signal, the voltage of the first capacitor C1 is lowered by the node voltage drop of the second capacitor C2 in the middle of the voltage being written into the first capacitor C1. This changes. As described above, when the voltage of the first capacitor C1 is changed, the voltage writing operation of the first capacitor C1 must be performed again, so that the time for writing the voltage into the first capacitor C1 becomes insufficient. Therefore, as shown in FIG. 6, when the start of the selection signal transmitted to the selection signal line S _n comes later than the start of the boost signal transmitted to the boost signal line B _n , the node voltage of the capacitor C2 drops. After that, a write operation of the data current I _DATA is performed.

When the pulse end of the light emission signal comes before the pulse end of the boost signal due to the difference between the load connected to the boost signal line B _n and the light emission signal line E _n , the pulse end of the light emission signal and the pulse end of the boost signal The current before the node voltage rise of the second capacitor C2 flows through the organic EL element OLED during the period between the stresses of the organic EL element OLED. If this operation is repeated repeatedly, the life of the organic EL element OLED may be shortened. Therefore, as shown in FIG. 6, the pulse end of the boost signal transmitted to the boost signal line B _n comes earlier than the pulse end of the light emission signal transmitted to the light emission scan line E _n , thereby providing a node of the second capacitor C2. After the voltage rises, a current flows in the organic EL element OLED.

In addition, when the pulse start of the light emission signal comes later than the start of the pulse of the boost signal, the current according to the node voltage drop of the second capacitor C2 during the period between the start of the pulse of the boost signal and the start of the pulse of the light emission signal is reduced to the organic EL element ( OLED) to stress the organic EL device (OLED). If such stress is repeated, the life of the organic EL element OLED may be shortened. Accordingly, as shown in FIG. 6, the pulse start of the light emission signal comes before the pulse start of the boost signal so that the node voltage of the second capacitor C2 decreases after the third transistor m3 is turned off.

That is, in the case of the present invention, the low level pulse width of the boost signal is largely applied to include the low level pulse width of the selection signal, and is less than the high level pulse width of the light emission signal.

As described above with reference to FIG. 4, the selection signal, the boost signal, and the light emission signal are output to the panel through the first scan driver 310 and the second scan driver 320.

Hereinafter, the configuration and operation of a scan driving circuit according to an exemplary embodiment of the present invention for outputting a selection signal and a boost signal having a waveform as shown in FIG. 6 will be described.

That is, the configuration of the first scan driver of the scan driver circuit of the present invention will be described, and the second scan driver that outputs the light emission signal can be sufficiently inferred from the configuration and operation of the first scan driver. do.

Fig. 7 is a block diagram showing the configuration of the first scan driver of the scan driver circuit according to the first embodiment of the present invention.

Here, the first scan driver 310 according to the first exemplary embodiment of the present invention is separated into a scan driving unit 312 and a boost driving unit 314 to separately output a selection signal and a boost signal.

Accordingly, the scan driving unit 312 and the boost driving unit 314 have n stages connected to each of the input signal IN1 and IN2 lines, and clock signals are applied to each stage.

In addition, the first and second clock signals CLK1 and CLK2 are applied to each stage constituting the scan driving unit 312, and the third, fourth, fifth, and third signals are applied to each stage constituting the boost driving unit 314. Two clock signals of the six clock signals CLK3, CLK4, CLK5, and CLK6 are alternately applied.

Output lines of these n stages are respectively connected to n row lines S1 to Sn and B1 to Bn included in the pixel array to provide a selection signal and a boost signal to each pixel constituting the pixel array. .

Here, first input signals IN1 and IN2 are respectively supplied to the first stages provided in the scan driving unit 312 and the boost driving unit 314, and output signals of the first to n-1 stages are respectively provided at the rear stages. It is supplied as an input signal to the stages.

In addition, each of the stages of the scan driving unit 312 that outputs a selection signal has a first clock to which first and second clock signals CLK1 and CLK2 are supplied, respectively, provided that the phases are inverted and overlap each other at a high level. The terminal CLKa and the second clock terminal CLKb are provided, a first clock signal CLK1 is supplied to the first clock terminal CLKa of the odd stages, and a second clock is supplied to the second clock terminal CLKb. The signal CLK2 is supplied. On the contrary, the second clock signal CLK2 is supplied to the first clock terminal CLKa of the even-numbered stages, and the first clock signal CLK1 is supplied to the second clock terminal CLKb.

That is, each stage that receives the first input signal IN1 or the previous stage output voltage gi and the first and second clock signals CLK1 and CLK2 is connected to the first and second clocks through the output line of each stage. The low level signals are sequentially output at intervals as long as the signals overlap at the high level.

On the other hand, each of the stages of the boost driving unit 314 which outputs a boost signal has two phases among the third to sixth clock signals CLK3, CLK4, CLK5, and CLK6 provided with a phase inversion and overlapping at a high level. A first clock terminal CLKa and a second clock terminal CLKb, which are alternately supplied with a clock signal, are provided.

That is, as shown, the third clock signal CLK3 is supplied to the first clock terminal CLKa of the first stage, the fifth clock signal CLK5 is supplied to the second clock terminal CLKb, and the second clock terminal CLKa is provided. The fourth clock signal CLK4 is supplied to the first clock terminal CLKa of the stage, and the sixth clock signal CLK6 is supplied to the second clock terminal CLKb.

In the case of the third stage, the fifth clock signal CLK5 is supplied to the first clock terminal CLKa and the third clock signal CLK3 is supplied to the second clock terminal CLKb as opposed to the first stage. In the case of the fourth stage, the sixth clock signal CLK6 is supplied to the first clock terminal CLKa and the fourth clock signal CLK4 is supplied to the second clock terminal CLKb as opposed to the second stage. do.

After the fifth stage, the clock signals inputted to the first to fourth stages are input in the same manner as the first to fourth stages in units of four consecutive stages.

That is, each stage supplied with the first input signal IN2 or the previous output voltage and the third and fifth clock signals CLK3 and CLK5 or the fourth and sixth clock signals CLK4 and CLK6 may be configured as the first stage signal. The low level signal is sequentially output to the odd-numbered boost signal line and the even-numbered boost signal line at intervals as long as the third, fifth clock signal, or fourth and sixth clock signals are overlapped at the high level through an output line. do.

However, the low level boost signals output from adjacent odd and even stages are superimposed and output in a predetermined portion.

In this case, as described above with reference to FIG. 6, the low level pulse width of the boost signal is largely output to include the low level pulse width of the selection signal corresponding thereto, and is less than the high level pulse width of the light emitting signal. do. In addition, the low level pulse width of the selection signal is output with a width less than the horizontal periodical.

Fig. 8 shows a specific circuit configuration of the first stage of the scan drive unit of the first scan driver according to the first embodiment of the present invention. 9 is a timing diagram of input / output signals of the stage shown in FIG. 8.

8 and 9, the stage of the scan driving unit may perform a precharge during a first period in which phases are different from each other with respect to the input clock signals CLK1 and CLK2. Evaluation is performed during the second period having the inverted phase, and as a result, low-level pulses are sequentially output at intervals as long as the clock signal overlaps at the high level.

That is, the output of the high level is output in the precharge period, and the signal corresponding to the input received in the precharge period is output in the evaluation period.

However, in the stage constituting the scan driving unit, the evaluation period (precharge period) of the odd stage is equal to the precharge period (evaluation period) of the even-numbered stage.

Hereinafter, the operation of the stage will be described in more detail through the circuit configuration of the first stage of the scan driving unit shown in FIG. 8.

However, in the case of a transistor provided in a stage, a PMOS thin film transistor is described as an example, but embodiments of the present invention are not necessarily limited thereto.

Referring to FIG. 8, the first stage 400 as the odd stage of the scan driving unit according to the first embodiment of the present invention receives an initial input signal IN1 and a gate terminal is connected to the first clock terminal. A first PMOS transistor M1; A second POMS transistor (M2) connected to an output terminal of the first PMOS transistor (M1) and connected to a second clock terminal and an output line (OUT); A third PMOS transistor (M3) connected to a gate terminal of the first clock terminal and connected between a second power supply (VSS) and a first node (N1); A fourth POMS transistor (M4) connected to an output terminal of the first PMOS transistor (M1) and connected between a first clock terminal and a first node (N1); A gate terminal is connected to the first node N1, and a fifth PMOS transistor M5 connected between the first power supply VDD and the output line OUT is included.

In addition, a first capacitor C1 connected between the output terminal of the first PMOS transistor M1 and the output line OUT is further included.

As shown in the drawing, when the stage is an odd stage of the scan driving unit, the first clock signal CLK1 is supplied to the first clock terminal and the second clock signal CLK2 is supplied to the second clock terminal. do. On the contrary, when the stage is even-numbered, the second clock signal CLK2 is supplied to the first clock terminal, and the first clock signal CLK1 is supplied to the second clock terminal.

In addition, a separate negative power may be applied to the second power source VSS, but may be configured to be grounded (GND) as shown. In the embodiment of the present invention, it is shown that the second power supply is implemented as ground.

Each stage is largely composed of a transfer unit, an inversion unit, and a buffer unit, and the transfer unit includes first and second POMS transistors M1 and M2 and a first capacitor C1. ), The inverting portion is composed of first, third and fourth PMOS transistors M1, M3, and M4, and the buffer portion is composed of fifth PMOS transistor M5.

At this time, the period during which the first clock signal CLK1 is at a low level, that is, the high level of the second clock signal CLK2, is a precharge period, and the first clock signal CLK1 is at a high level, that is, the second clock. The period in which the signal CLK2 is at the low level becomes the evaluation period. Accordingly, the output of the high level is output in the precharge period, and the signal corresponding to the input received in the precharge period is output in the evaluation period.

However, in the exemplary embodiment of the present invention, the first and second clock signals as signals input to each stage are provided by overlapping a predetermined portion at a high level as shown.

This causes the pair of clock signals CLK1 and CLK2 to be input to each stage to sequentially output low level signals at time intervals as long as they overlap at a high level, and thus, a predetermined time interval between output signals of each stage. This is to secure a margin for clock skew or delay.

Referring to FIGS. 8 and 9, the operation of the circuit for the odd stage of the scan driving unit is described first. First, the precharge period, that is, the first clock signal CLK1 is at a low level, that is, the second clock signal ( While CLK2 is input to the high level, M1 and M3 are turned ON, and the input signal IN1 is transmitted to the gate terminals of M2 and M4, respectively.

Therefore, in the precharge period, the previous output voltage or the input signal IN1 as an input signal is stored in the first capacitor C1, and the second clock signal CLK2 or the second node is stored in the first node N1. Since the low level signal is charged by the power supply VSS, the M5 is turned on so that the high power first power supply VDD is output through the output terminal OUT.

That is, in the precharge period, the output of the buffer unit of the stage becomes a high level.

In addition, during the evaluation period, M1 is turned off to block the input signal IN1, and M3 and M4 are also turned off.

At this time, when the signal input during the precharge period, that is, the previous output voltage or the input signal IN1 is at a high level, the precharged signal level is maintained during the precharge period, and the buffer unit still outputs a high level. Done.

On the other hand, when the signal input during the precharge period, that is, the previous output voltage or the input signal IN1 is at the low level, the M2 is turned on by the low level signal stored by the first capacitor C1. As a result, when the M2 is turned on, the transfer unit outputs the second clock signal CLK2 having a low level through the output terminal OUT.

In other words, in the evaluation period, the stage outputs a low level when the signal input in the previous precharge period, that is, the previous stage output voltage or the first input signal IN1 is at a low level, and when the stage is at a high level, Perform the operation of outputting.

However, as described above, the first and second clock signals as signals input to the stage are provided by overlapping a predetermined portion at a high level as shown.

Accordingly, when the first and second clock signals CLK1 and CLK2 are at the high level, when the previous and second precharge periods are precharged, both M1 and M3 controlled by the first clock signal CLK1 are turned off, The voltage remains the same, keeping the previous output.

On the other hand, if the previous period is an evaluation period, M1 and M3 are off, and M2 maintains the previous state. If M2 is off, the high level is input. As a result, the high level output is maintained by M5. .

On the contrary, if the M3 is turned on, the low level is input, and since the gate terminal of the M2 is floating, the voltage of C1 is maintained as it is, and accordingly, the second clock signal having the high level is outputted. As a result, a high level is output.

As described above, when the first and second clock signals CLK1 and CLK2 are at the high level, the previous output is maintained when the previous is the precharge period, and the output is at the high level when the evaluation period is the first and second clock signals CLK1 and CLK2. As the high level of) overlaps, it is possible to give a time interval between output pulses of adjacent stages.

FIG. 10 shows a specific circuit configuration of the first to fourth stages of the boost drive unit of the first scan driver according to the first embodiment of the present invention. 11 is a timing diagram of input / output signals of the stage shown in FIG.

As shown in FIG. 10, the circuit configuration and operation of each stage of the boost driving unit are the same as those of the scan driving unit described above with reference to FIG. 8, and thus, detailed descriptions thereof will be omitted.

However, in the case of the stage of the boost driving unit, the third clock signal CLK3 is supplied to the first clock terminal of the first stage, the fifth clock signal CLK5 is supplied to the second clock terminal, and The fourth clock signal CLK4 is supplied to the first clock terminal, and the sixth clock signal CLK6 is supplied to the second clock terminal.

In the case of the third stage, the fifth clock signal CLK5 is supplied to the first clock terminal, the third clock signal CLK3 is supplied to the second clock terminal, and the fourth stage is opposite to the first stage. In contrast to the second stage, the sixth clock signal CLK6 is supplied to the first clock terminal and the fourth clock signal CLK4 is supplied to the second clock terminal.

After the fifth stage, clock signals inputted to the first to fourth stages are input in the same manner as the first to fourth stages in units of four consecutive stages.

That is, each stage supplied with the first input signal IN2 or the previous output voltage and the third and fifth clock signals CLK3 and CLK5 or the fourth and sixth clock signals CLK4 and CLK6 may be configured as the first stage signal. The low level signal is sequentially output to the odd-numbered boost signal line and the even-numbered boost signal line at intervals as long as the third, fifth clock signal, or fourth and sixth clock signals are overlapped at the high level through an output line. do.

However, the low level boost signals output from adjacent odd and even stages are superimposed and output in a predetermined portion.

That is, each of the low level boost signals output from the radix stage and the low level boost signals output from the even stage is output at a predetermined interval, but in general, the low level boost signals are output from the adjacent radix and even stages. The boost signal of the level is output by overlapping a predetermined portion, as shown in FIG.

In the case of the stage constituting the boost drive unit, the evaluation period (precharge period) of the i-th stage is equal to the precharge period (evaluation period) of the i + 2th stage, as shown in FIG.

12 is a timing diagram of signals input / output to each stage of the first scan driver according to the first embodiment of the present invention.

That is, this is a timing diagram collectively showing signals input / output to the scan driving unit and the boost driving unit described above with reference to FIGS. 9 and 11.

As shown in FIG. 12, the third and fifth clock signals CLK3 and CLK5 and the fourth and sixth clock signals CLK4 and CLK6 input to each stage of the boost driving unit are input to the scan driving unit. Compared to the two clock signals CLK1 and CLK2, the overlapping period at a high level is longer, the precharge and evaluation periods are longer, and the input signal IN2 respectively input to the boost driving unit is also input to the scan driving unit. It is characterized in that it has a low level wider than the input signal (IN1).

The third to sixth clock signals are sequentially delayed by a predetermined period and input.

As described above with reference to FIG. 6, the low level pulse width of the boost signal is largely applied to include the low level pulse width of the corresponding selection signal.

That is, according to the first embodiment of the present invention, the clock signals CLK3, CLK4, CLK5, and CLK6 applied to the boost driving unit are respectively increased so that the pulse width of the output boost signal is larger than the pulse width of the corresponding selection signal. The period and the low level width of the input signal IN2 may be adjusted to be wider than the clock signals CLK1 and CLK2 and the input signal IN1 applied to the scan driving unit.

Fig. 13 is a block diagram showing the configuration of a first scan driver of a scan driver circuit according to a second embodiment of the present invention.

However, the same configuration and operation as those of the first embodiment described with reference to FIG. 7 will be omitted.

That is, the first scan driver 310 according to the second exemplary embodiment of the present invention is similar to the first exemplary embodiment described above with reference to FIG. 7 to separately output the selection signal and the boost signal, respectively. The drive unit 316 is separated and configured.

However, in addition to the clock signals CLK3, CLK4, CLK5 and CLK6 and the input signal IN2, the control signals D1, D2, D3, and D4 may be further adjusted with respect to the boost driving unit 316. Characterized in that it is authorized.

In this case, D1, D2, D3, and D4 control signals are sequentially input to the first to fourth stages of the boost drive unit, and after the fifth stage, the first to fourth stages are configured in units of four consecutive stages. As in the fourth stage, the control signals D1, D2, D3, and D4 input to the first to fourth stages are sequentially input.

FIG. 14 is a circuit diagram of an arbitrary stage in the first scan driver according to the second embodiment of the present invention. FIG. 14 is a diagram illustrating the first stage of the scan drive unit and the first to fourth stages of the boost drive unit shown in FIG. 10. The circuit configuration is shown. 15 is a timing diagram of input / output signals of the stage shown in FIG.

As shown in FIGS. 14 and 15, the configuration of the stage 400 of the scan driving unit and the timing diagram of the signals input thereto are the same as those of the scan driving unit of the first embodiment described with reference to FIGS. 8 and 9. Should be omitted.

However, in the case of the boost driving unit, the sixth PMOS thin film transistor M6 and the seventh PMOS thin film transistor M7 are additionally configured in the configuration of the first embodiment shown in FIG. 8, and the swing of the output boost signal is adjusted. The control signal (B1, B2, B3, B4) is input to the input terminal of the M6.

Here, D1, D2, D3, and D4 control signals are input to the first to fourth stages of the boost driving unit, respectively.

In more detail, as illustrated in FIG. 11, the stage 500 of the boost driving unit includes a gate terminal connected to an output terminal of the M1 in addition to M1 to M5 and C1, and an input line and a boost of the control signals D1 to D4. A sixth POMS transistor M6 connected to the signal output line BST; A gate terminal is connected to the first node N1, and a seventh PMOS transistor M7 connected between the first power supply VDD and the boost signal output line BST is further configured.

As described above, the M6 and M7 are further configured, and as the adjustment signal is applied through the M6, the difference between the high level and the low level absolute value of the boost signal output from each stage, that is, the swing of the output pulse is adjusted by the adjustment signal. do.

That is, the same signal as in the first embodiment is output through the output terminal OUT of the stage and input to the next stage, but depends on the swing degree of the control signal through the boost signal output line BST of each stage. The boost signal is thereby output.

As shown in FIG. 15, the adjustment signals D1, D2, D3, and D4 applied to the boost driving unit are higher than those of the clock signals CLK3, CLK4, CLK5, and CLK6 applied to the boost driving unit. It can be seen that the absolute difference of the low level is applied with a small pulse.

That is, the control signal is less swing of the pulse than the corresponding clock signal.

Accordingly, the boost signal output through the stage of the boost driving unit illustrated in FIG. 14 is not only outputted with a pulse width of the boost signal greater than that of the corresponding selection signal as described in the first embodiment. The control signal is output as a pulse having a small difference between the absolute value of the high level and the low level, that is, a pulse having a small swing.

That is, the second embodiment of the present invention has the advantage that the pulse swing of the boost signal outputted as compared with the first embodiment described above can be adjusted through the control signal.

In addition, while applying a third power supply (VL) instead of the control signals (D1, D2, D3, D4) for adjusting the swing of the output pulse, it is possible to output a boost signal similar to the second embodiment described above. This will be described with reference to FIGS. 16 and 17.

Fig. 16 is a circuit diagram of an arbitrary stage in the first scan driver according to the third embodiment of the present invention, and shows a specific circuit configuration of the first stage of the scan / boost drive unit. 17 is a timing diagram of input / output signals of the stage shown in FIG.

As shown in FIG. 16 and FIG. 17, the scan / boost drive unit according to the third embodiment of the present invention, instead of the predetermined control signals D1, D2, D3, and D4, is applied to M6 unlike the second embodiment described above. The third power source VL has a characteristic of being applied.

At this time, the third power supply VL is provided with a negative voltage corresponding to a low level value of the control signal.

However, as shown in FIG. 17, the waveform of the boost signal output in the third embodiment is output in the form of a staircase of the first low level and the second low level, and when the first low level is output, Both M6 and M7 are turned on, resulting in a problem in which the first power source VDD and the third power source VL are connected.

Accordingly, in the third embodiment, power consumption increases in a period during which the first low level of the boost signal is output.

In order to overcome this disadvantage, the fourth embodiment of the present invention is characterized in that M8 is additionally configured to remove the first low level output of the boost signal, which will be described below with reference to FIGS. 18 and 19.

Fig. 18 is a circuit diagram of an arbitrary stage in the first scan driver according to the fourth embodiment of the present invention, and shows a specific circuit configuration of the first stage of the scan / boost drive unit. 19 is a timing diagram of input / output signals of the stage shown in FIG.

Referring to FIG. 18, in the circuit configuration of the stage according to the fourth embodiment of the present invention, a gate terminal is connected to an output terminal of M1 in addition to M1 to M5 and C1, and a third power supply (VL) input line and a boost signal output are provided. A sixth POMS transistor M6 connected to the line BST; A gate terminal is connected to the first node N1 and a gate terminal is connected to the second clock terminal as well as the seventh PMOS transistor M7 connected between the first power supply VDD and the boost signal output line BST. It is characterized in that it is further provided with an M8 connected between the M6 and M7.

In this way, the M8 is additionally configured to eliminate the section in which both the M6 and the M7 are turned on, thereby overcoming the problem of connecting the first power source VDD and the third power source VL, thereby reducing power consumption. The waveform of the boost signal outputted as shown in FIG. 19 can be improved.

20 is a block diagram showing the configuration of a first scan driver of a scan driver circuit according to a fifth embodiment of the present invention.

This is characterized in that the first scan drive unit divided into a scan drive unit and a boost drive unit in the first to fourth embodiments is integrated into the scan / boost drive unit 317.

Since this is derived by combining the first and fourth embodiments described above, the description of the same parts as described above will be omitted.

That is, clock signals CLK7, CLK8, CLK9, and CLK10 and an input signal IN3 are applied to the scan / boost drive unit, and control signals D1, D2, D3, and D4 for controlling the swing of the output pulse. Instead, the third power source VL is applied, and the selection control signals A1, A2, A3, and A4 are sequentially applied to sequentially output the odd and even selection signals.

At this time, the third power supply VL is provided with a negative voltage corresponding to a low level value of the control signal.

Here, A1, A2, A3, and A4 selection control signals are input to the first to fourth stages of the scan / boost drive unit, respectively.

In this case, A1, A2, A3, and A4 selection control signals are sequentially input to the first to fourth stages of the boost driving unit, and after the fifth stage, the first to fourth stages are configured in units of four consecutive stages. As in the fourth stage, the selection control signals A1, A2, A3, and A4 input to the first to fourth stages are sequentially input.

FIG. 21 is a circuit diagram of an arbitrary stage in the first scan driver according to the fifth embodiment of the present invention, and shows a specific circuit configuration of the first stage of the scan / boost drive unit shown in FIG. FIG. 22 is a timing diagram of input / output signals of the stage shown in FIG. 21.

As shown in FIGS. 21 and 22, the scan / boost driving unit according to the fifth embodiment of the present invention includes the ninth PMOS thin film transistor M9 and the tenth PMOS thin film in the configuration of the fourth embodiment shown in FIG. 19. The transistor M10 is further configured, and the selection control signals A1, A2, A3, and A4 are input to the input terminal of the M9 in order to sequentially output the selection signals.

Here, A1, A2, A3 and A4 selection control signals are sequentially input to the first to fourth stages of the scan / boost drive unit.

In more detail, as illustrated in FIG. 21, in the stage 600 of the scan / boost driving unit, gate terminals are connected to the output terminals of M1 in addition to M1 to M8 and C1, and selection control signals A1, A2, and A3. A4) a ninth POMS transistor M9 connected to the input line and the selection signal output line SEL; A gate terminal is connected to the first node N1, and a tenth PMOS transistor M10 connected between the first power supply VDD and the selection signal output line SEL is further configured.

As described above, the M9 and M10 are further configured, and as the selection control signal is applied through the M9, the selection signals output from each stage may be sequentially output as shown in FIG. 22.

That is, the fifth embodiment of the present invention has the advantage of reducing the number of driving units as a whole.

In addition, in the case of the fifth embodiment, as in the fourth embodiment, M8 connected between the M6 and the M7 is further provided, thereby eliminating the section in which both the M6 and the M7 are turned on, and as a result, the first power source VDD. And it is possible to overcome the problem that the third power source (VL) is connected, there is an advantage that can improve the power consumption.

According to the present invention, a multi-stage stage for sequentially outputting the selection signal and the boost signal is provided to improve the waveform of the output signal and to eliminate the path through which static current can flow for the stage. It has the advantage of reducing power.

In addition, when the high level output is output through the scan driving circuit, the output stage is not charged, thereby minimizing leakage current. When the low level output is output, the decrease of the current discharging the output stage is minimized, thereby increasing the operation speed. Has the advantage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A scan driving circuit comprising a plurality of stages connected in series to an input signal line or a previous stage output voltage line and connected to a clock signal input line, respectively, A first scan driver which sequentially outputs a selection signal or a boost signal through the stage of the multi-stage, Each stage of the first scan driver for outputting the boost signal includes: a first transistor (M1) receiving a previous output voltage or an initial input signal and having a gate terminal connected to the first clock terminal; A second transistor (M2) connected to an output terminal of the M1 and connected to a second clock terminal and an output line (OUT); A third transistor (M3) connected with a gate terminal to the first clock terminal and connected between a second power supply (VSS) and a first node (N1); A fourth transistor (M4) connected to a gate terminal of the output terminal of the M1 and connected between the first clock terminal and the first node (N1); A fifth transistor (M5) connected to a gate terminal of the first node (N1) and connected between a first power source (VDD) and the output line (OUT); A sixth transistor M6 connected to an output terminal of the M1 and connected to a third power supply VL input line and a boost signal output line BST; A seventh transistor (M7) connected to a gate terminal of the first node (N1) and connected between a first power supply (VDD) and the boost signal output line (BST); And a gate terminal connected to the second clock terminal and an eighth transistor (M8) connected between the M6 and the M7. The method of claim 1, And a first capacitor (C1) connected between the output terminal of the first transistor (M1) and the output line (OUT). The method of claim 1, And the third power supply (VL) is a negative voltage corresponding to a predetermined low level value. The method of claim 3, wherein And the low level of the third power supply is less than the low level absolute value of the clock signal. A scan driving circuit comprising a plurality of stages connected in series to an input signal line or a previous stage output voltage line and connected to a clock signal input line, respectively, A first scanning driver for sequentially outputting the selection signal and the boost signal through the stage of the multi-stage, Each stage of the first scan driver includes: a first transistor (M1) receiving a previous output voltage or an initial input signal and having a gate terminal connected to the first clock terminal; A second transistor M2 connected to an output terminal of the M1 and connected to a second clock terminal and an output line OUT; A third transistor (M3) connected with a gate terminal to the first clock terminal and connected between a second power supply (VSS) and a first node (N1); A fourth transistor (M4) connected to a gate terminal of the output terminal of the M1 and connected between the first clock terminal and the first node (N1); A fifth transistor (M5) connected to a gate terminal of the first node (N1) and connected between a first power source (VDD) and the output line (OUT); A sixth transistor M6 connected to an output terminal of the M1 and connected to a third power supply VL input line and a boost signal output line BST; A seventh transistor (M7) connected to a gate terminal of the first node (N1) and connected between a first power supply (VDD) and the boost signal output line (BST); An eighth transistor (M8) connected to the second clock terminal and connected between the M6 and M7; A ninth transistor M9 connected to an output terminal of the M1 and connected to a selection control signal input line and a selection signal output line SEL; A scan driving circuit comprising a gate terminal connected to the first node N1 and a tenth transistor M10 connected between a first power supply VDD and the selection signal output line SEL. . The method of claim 5, And a first capacitor (C1) connected between the output terminal of the first transistor (M1) and the output line (OUT). The method of claim 5, And the third power supply (VL) is a negative voltage corresponding to a predetermined low level value. The method of claim 7, wherein And the low level of the third power supply is less than the low level absolute value of the clock signal. The method of claim 5, And a selection control signal for sequentially outputting an odd and even selection signal to the selection control signal input line. A pixel portion including a plurality of pixels positioned to be connected to the selection signal lines, the data lines, the emission signal lines, and the boost signal lines; A data driver circuit for supplying a data signal to the data lines; A first scan driver comprising a plurality of stages connected to a clock signal input line and sequentially outputting a selection signal or a boost signal through the stages; A scan driving circuit including a second scanning driver for sequentially outputting a light emission signal through the stage of the multi-stage, Each stage of the first scan driver for outputting the boost signal includes: a first transistor (M1) receiving a previous output voltage or an initial input signal and having a gate terminal connected to the first clock terminal; A second transistor (M2) connected to an output terminal of the M1 and connected to a second clock terminal and an output line (OUT); A third transistor (M3) connected with a gate terminal to the first clock terminal and connected between a second power supply (VSS) and a first node (N1); A fourth transistor (M4) connected to a gate terminal of the output terminal of the M1 and connected between the first clock terminal and the first node (N1); A fifth transistor (M5) connected to a gate terminal of the first node (N1) and connected between a first power source (VDD) and the output line (OUT); A sixth transistor M6 connected to an output terminal of the M1 and connected to a third power supply VL input line and a boost signal output line BST; A seventh transistor (M7) connected to a gate terminal of the first node (N1) and connected between a first power supply (VDD) and the boost signal output line (BST); And an eighth transistor (M8) connected to the second clock terminal and connected between the M6 and M7.

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