KR100660891B1 - Semiconductor device having vertical channel transistor and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided to improve the degree of integration by using an improved pillar structure with two vertical channel transistors. A semiconductor device includes a substrate(100), a plurality of pillars, a lower gate electrode, and an upper gate electrode. The plurality of pillars are arranged along first and second directions on the substrate. Each pillar is composed of a lower channel portion, an upper channel portion and a common drain portion(120) between the lower and the upper channel portions. The lower gate electrode(225) is used for enclosing a first periphery of the lower channel portion of the pillar. The upper gate electrode(215) is used for enclosing a second periphery of the upper channel portion of the pillar.

Description

Semiconductor Device Having Vertical Channel Transistor And Method For Manufacturing The Same

1A to 1L are perspective views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

2A through 2F are plan views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

3A-3W are cross-sectional views taken along cut line A-A and cut line B-B of FIGS. 2A-2F.

4 is a circuit diagram illustrating a portion of a cell array region of a semiconductor device according to an embodiment of the present invention.

(Explanation of symbols for main parts of drawing)

100 substrate 101 support substrate

102: buried insulating film 103: semiconductor active layer

140: lower storage node electrode portion 245: lower plate electrode

130: lower source portion 122: lower channel portion

225: lower gate electrode 255: lower word line

120: common drain portion 265: bit line

112: upper channel portion 215: upper gate electrode

275: upper word line 110: upper source portion

284: upper storage electrode pad 285: upper storage electrode

295: upper plate electrode

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a vertical channel transistor and a method of manufacturing the same.

In a semiconductor device employing a planar type transistor in which a gate electrode is formed on a semiconductor substrate and a junction region is formed on both sides of the gate electrode, attempts to reduce the channel length continue as the integration density of the semiconductor device increases. have. However, reducing the channel length results in short channel effects such as drain induced barrier lowering (DIBL), hot carrier effect and punch through. In order to prevent such a short channel effect, various methods have been proposed, such as a method of reducing the depth of the junction region and a method of extending the channel length by forming a groove in the channel region.

However, as the integration density of semiconductor memory devices, particularly dynamic random access memory (DRAM), is approaching giga bits, the above attempts to prevent short channel effects are also reaching their limit.

To address this, transistors with vertical channels have been disclosed.

U. S. Patent No. 5,885, 864 discloses a memory cell having a transistor having a vertical channel. The memory cell includes a gate electrode surrounding a pillar portion of a silicon material, a first source / drain electrode positioned at an upper portion of the pillar portion, and a second source / drain positioned in a silicon material substantially horizontally extending from the base of the pillar portion. An access transistor having an electrode; And a storage capacitor having a storage electrode connected to the first source / drain electrode.

K. Sunouchi et. Al. Also published a paper entitled, “A Surrounding Gate Transistor Cell for 64/256 Mbit DRAMs” in Techn. Digest IEDM, pp. 23-25, 1989. The paper discloses a surrounding gate transistor cell. The cell has a transfer gate and a capacitor electrode surrounding the pillar silicon islands. A bit line is contacted over the silicon pillar. That is, all the elements for one memory cell are located in one silicon pillar.

The cell disclosed in the US patent and the paper includes a transistor and a capacitor in one silicon pillar region, and thus has a device planar area of 4F ² . Therefore, there is a limit in reducing the planar area of the device.

The technical problem to be achieved by the present invention is to provide a semiconductor device that can be applied to an ultra-high integration device.

In addition, another technical problem to be achieved by the present invention is to provide a method for manufacturing a semiconductor device that can be applied to an ultra-high integration device.

In order to achieve the above technical problem, an aspect of the present invention provides a semiconductor device. The semiconductor device has a substrate. Pillars arranged in a first direction and in a second direction crossing the first direction are positioned on the substrate. Each pillar includes a lower channel portion, an upper channel portion, and a common drain portion positioned between the lower channel portion and the upper channel portion. A lower gate electrode surrounding the outer circumference of the lower channel portion is provided, and an upper gate electrode surrounding the outer circumference of the upper channel portion is provided.

The pillar may further include a lower storage node electrode disposed below the lower channel portion, and the semiconductor device may further include an upper storage node electrode positioned above the upper channel portion. In addition, the semiconductor device may further include a lower plate electrode surrounding the lower storage node electrode portions of the pillars.

The pillar may further include a lower source part disposed between the lower channel part and the lower storage node electrode part. In this case, the lower gate electrode is electrically insulated from the common drain portion and the lower source portion.

The pillar may further include an upper source portion disposed between the upper channel portion and the upper storage node electrode. In this case, the upper gate electrode is electrically insulated from the common drain portion and the upper source portion. The semiconductor device may further include a storage node contact pad positioned between the upper source portion and the upper storage node electrode.

The semiconductor device may further include a lower word line connected to lower gate electrodes of pillars arranged in the first direction. In this case, the lower word line may surround the outer circumference of the lower gate electrode.

The semiconductor device may further include a bit line connected to common drain portions of the pillars arranged in the second direction. In this case, the bit line may surround the common drain portion.

The device may further include an upper word line connected to upper gate electrodes of the pillars arranged in the first direction. In this case, the upper word line may surround the upper gate electrode.

In order to achieve the above technical problem, an aspect of the present invention provides a method of manufacturing a semiconductor device. The manufacturing method includes forming hard mask patterns arranged on a substrate in a first direction and a second direction crossing the first direction; Etching the substrate using the hard mask patterns as masks to form columnar upper channel portions having a width narrower than that of the hard mask patterns; Forming an upper gate electrode on an outer circumference of the upper channel portion; Etching the substrate by using the upper gate electrode as a mask to form a common drain portion having a pillar shape; Forming insulating spacers on sidewalls of the common drain portion; Etching the substrate using the hard mask pattern and the insulating spacer as a mask to form a lower channel portion having a pillar shape having a width smaller than that of the common drain portion; And forming a lower gate electrode on an outer circumference of the lower channel portion.

Etching the substrate using the lower gate electrode as a mask to form a lower storage node electrode part having a pillar shape; Removing the hard mask pattern; An upper storage node electrode may be formed on the upper channel portion.

Before forming the lower storage node electrode portion, the substrate may be etched using the hard mask pattern and the lower gate electrode as a mask to form a lower source portion having a pillar shape. In addition, before forming the upper channel portion, the substrate may be etched using the hard mask pattern as a mask to form an upper source portion. In this case, the upper storage node electrode may be formed on the upper source portion.

Before forming the upper storage node electrode, a storage node contact pad may be formed on the upper source portion.

A lower word line is formed to connect lower gate electrodes formed under the hard mask patterns arranged in the first direction, and connected to common drain regions formed under the hard mask patterns arranged in the second direction. A bit line may be formed, and an upper word line may be formed to connect upper gate electrodes formed under the hard mask patterns arranged in the first direction.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. In addition, throughout the specification, 'source' may be substituted for 'drain', and at the same time, 'drain' may be substituted for 'source'.

4 is a circuit diagram illustrating a portion of a cell array region of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4, an upper word line W / L _H and a lower word line W / L _L parallel to the upper word line W / L _H are arranged in one direction, and the word lines W are arranged. Bit lines B / L are arranged in a direction intersecting / L _H and W / L _L. An upper unit cell UC _H is defined by the intersection of the upper word line W / L _H and the bit line B / L, and the lower word line W / L _L and the bit line B / _L. The lower unit cell UC _l is defined by the intersection of L).

The upper unit cell UC _H includes an upper transistor T _H and an upper capacitor C _H. The upper transistor T _H has a gate connected to the upper word line W / L _H , a drain connected to the bit line B / L, and the upper capacitor C _H is a storage node electrode. The source electrode is connected to the source of the upper transistor T _H , and the plate electrode is connected to the upper plate electrode line P / L _H. Similarly, the lower unit cell UC _L includes a lower transistor T _L and a lower capacitor C _L. The lower transistor T _L has a gate connected to the lower word line W / L _L , a drain connected to the bit line B / L, and the lower capacitor C _{L is} connected to a storage node electrode. The source of the lower transistor T _L is connected, and the plate electrode is connected to the lower plate electrode line P / L _L. Meanwhile, the upper transistor T _H and the lower transistor T _L connected to one bit line B / L share a drain.

1A to 1L are perspective views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2A to 2F are plan views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. admit. 3A-3W are cross-sectional views taken along cut line AA and cut line BB of FIGS. 2A-2F, wherein region “A” is an area taken along cut line AA and region “B” is taken along cut line BB. Area. In the meantime, the interlayer insulating layers described below are not illustrated.

1A, 2A, and 3A, a substrate 100 is provided. The substrate 100 may be a silicon on insulator (SOI) substrate. The SOH substrate has a support substrate 101, a buried insulating layer 102 on the support substrate 101, and a semiconductor active layer 103 on the buried insulating layer 103.

Impurities for forming a well are implanted into the substrate 100. The impurities for forming the wells may be P-type impurities. As a result, P wells are formed in the semiconductor active layer 103. Subsequently, channel impurities are implanted into the substrate 100.

A pad oxide film 201 is formed on the substrate 100. The pad oxide layer 201 may be formed by thermal oxidation. In addition, the pad oxide layer 201 may be a silicon oxide layer. A hard mask film is stacked on the pad oxide film 201. The hard mask layer may be a material having an etch selectivity with respect to the pad oxide layer 201 and the semiconductor active layer 103. The hard mask layer may be, for example, a silicon nitride layer. Subsequently, the hard mask layer is patterned to form a hard mask pattern 203 arranged in a first direction and a second direction crossing the first direction. The first direction may be an X axis direction parallel to the cutting line A-A, and the second direction may be a Y axis direction parallel to the cutting line B-B. In addition, the hard mask pattern 203 may have a square shape. In this case, the length of one side of the hard mask pattern 203 may be 1F (minimum feature size).

Subsequently, the pad oxide film 201 and the semiconductor active layer 103 are etched using the hard mask pattern 203 as a mask. Such etching is preferably anisotropic etching. As a result, a first sub pillar made of the semiconductor active layer material is formed, and the first sub pillar is the upper source portion 110 having a pillar shape. The width of the upper source portion 110 may be the same as the width 203 of the hard mask pattern.

2A shows the unit cell region C. FIG. One side of the unit cell region C has a feature size of 2F which is an X-axis pitch of the hard mask pattern 203, and the other side has a Y-axis pitch of the hard mask pattern 203. Has a feature size of 2F. As a result, the squared feature size of the unit cell region C is 4F ² .

Meanwhile, the planar shape of the hard mask pattern 203 illustrated in FIGS. 1A and 2A may be square, but may be patterned in a circle during an actual process.

1B, 2A, and 3B, by stacking a first insulating spacer material on the substrate on which the upper source part 110 is formed and etching back the first insulating spacer material, the upper source The first insulating spacer 207 is formed on the sidewall of the part 110. The first insulating spacer 207 may also be formed on sidewalls of the hard mask pattern 203. The first insulating spacer material is a material having an etch selectivity with respect to the substrate 100, that is, the semiconductor active layer 103, and may be, for example, a silicon nitride layer.

Referring to FIGS. 1B, 2B, and 3C, the substrate 100, that is, the semiconductor active layer 103 is formed by a predetermined depth using the hard mask pattern 203 and the first insulating spacer 207 as a mask. Etch it. The etching of the semiconductor active layer 103 is preferably anisotropic etching. As a result, a second lower portion of the upper source portion 110 and a lower portion of the first insulating spacer 207 made of the semiconductor active layer material and integrally extended with the lower portion of the upper source portion 110. Sub pillars are formed. Subsequently, sidewalls of the second sub-pillar are etched by a predetermined width using the hard mask pattern 203 and the first insulating spacer 207 as a mask. Etching the sidewalls of the second sub-pillar is preferably isotropic etching. As a result, an upper channel portion 112 having a width smaller than the width of the hard mask pattern 203 and having a pillar shape is formed under the upper source portion 110.

Subsequently, a first gate insulating layer 212 is formed on the substrate on which the upper channel portion 112 is formed. In detail, the first gate insulating layer 212 is exposed by forming sidewalls of the upper channel portion 112, the semiconductor active layer 103 exposed between the upper channel portions 112, and the upper channel portion 112. It is formed on the lower surface of the upper source portion 110. The upper gate insulating film 212 is preferably a thermal oxide film formed using a method of thermally oxidizing the substrate, but is not limited thereto, and may be a deposition oxide film. The upper gate insulating layer 212 may be a silicon oxide layer SiO ₂ , a hafnium oxide layer HfO ₂ , a tantalum oxide layer Ta ₂ O ₅ , or an ONO (oxide / nitride / oxide) layer.

Subsequently, an upper gate electrode layer is stacked on the substrate 100 on which the upper gate insulating layer 212 is formed. The upper gate electrode layer may be a polysilicon layer or a silicon germanium layer doped with n-type or p-type impurities. The upper gate electrode layer is etched back using the upper gate insulating layer 212 as an etch stop layer. As a result, the upper gate electrode layer remains in a space formed by the upper channel portion 112, the upper source portion 110, the first insulating spacer 207, and the substrate 100. The upper gate electrode film forms the upper gate electrode 215. The upper gate electrode 215 is a surrounding gate electrode surrounding the outer circumference of the upper channel part 112.

1B, 2B, and 3D, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the substrate 100 on which the upper gate electrode 215 is formed, and thus the upper channel portion ( The common drain region 120a is formed in the substrate 100 between the 112.

Referring to FIGS. 1C, 2B, and 3E, the upper gate insulating layer 212 and the substrate 100, that is, the semiconductor active layer may be formed using the hard mask pattern 203 and the upper gate electrode 215 as a mask. Etch 103). Such etching is preferably anisotropic etching. As a result, a third sub-pillar formed of the semiconductor active layer 103 material and extending downwardly as a single body with the upper channel portion 112 is formed. The third sub pillar is a common drain portion 120 having a pillar shape, and the common drain portion 120 has a width wider than that of the upper channel portion 112. The common drain part 120 includes the common drain area 120a.

The upper gate electrode 215 is insulated from the upper source portion 110 and the common drain portion 120 by the upper gate insulating layer 212.

1D, 2C, and 3F, by stacking a second insulating spacer material on the substrate on which the common drain part 120 is formed and etching back the second insulating spacer material, the common drain part 120 is formed. The second insulating spacer 217 is formed on the sidewalls of the second insulating spacer 217. The second insulating spacer 217 may also be formed on sidewalls of the first insulating spacer 207 and the upper gate electrode 215. The second insulating spacer material may be a material having an etch selectivity with respect to the substrate, that is, the semiconductor active layer 103, and may be, for example, a silicon nitride layer.

Subsequently, the substrate 100, ie, the semiconductor active layer 103, is etched by a predetermined depth using the hard mask pattern 203 and the second insulating spacer 217 as a mask. The etching of the semiconductor active layer 103 by a predetermined depth is preferably anisotropic etching. As a result, a fourth sub made of the semiconductor active layer material under the common drain portion 120 and under the second insulating spacer 217, and extending integrally therewith with the common drain portion 120. Pillars are formed. Subsequently, sidewalls of the fourth sub-pillar are etched by a predetermined width using the hard mask pattern 203 and the second insulating spacer 217 as a mask. Etching the sidewalls of the fourth sub-pillar by a predetermined width is preferably isotropic etching. As a result, a lower channel portion 122 having a pillar shape having a width smaller than that of the common drain portion 120 is formed below the common drain portion 120.

Subsequently, a lower gate insulating layer 222 is formed on the substrate on which the lower channel portion 122 is formed. In detail, the lower gate insulating layer 222 may include sidewalls of the lower channel portion 122, lower surfaces of the common drain portion 120 exposed by the lower channel portion 122, and the lower channel portions 122. It is formed on the semiconductor active layer 103 exposed in between. The lower gate insulating layer 222 is preferably a thermal oxide film formed using a method of thermally oxidizing the substrate, but is not limited thereto, and may be a deposition oxide film. The lower gate insulating layer 222 may be a silicon oxide layer (SiO ₂ ), a hafnium oxide layer (HfO ₂ ), a tantalum oxide layer (Ta ₂ O ₅ ), or an ONO (oxide / nitride / oxide) layer.

Subsequently, a lower gate electrode layer is stacked on the substrate 100 on which the lower gate insulating layer 222 is formed. The lower gate electrode layer may be a polysilicon layer or a silicon germanium layer doped with n-type or p-type impurities. Subsequently, the lower gate electrode layer is etched back using the lower gate insulating layer 222 as an etch stop layer. As a result, the lower gate electrode layer remains in a space formed by the lower channel portion 122, the common drain portion 120, the second insulating spacer 217, and the substrate 100. The lower gate electrode film forms the lower gate electrode 225. In this case, the lower gate electrode 225 has a form of a surrounding gate electrode surrounding the outer circumference of the lower channel portion 122.

1D, 2C, and 3G, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the substrate 100 on which the lower gate electrode 225 is formed, and thus the lower channel portion 122 is formed. The lower source region 130a is formed in the substrate 100 between the layers. In addition, an LDD region may be formed by implanting an n-type impurity at a dose lower than that of an impurity for forming the lower source region 130a.

1E, 2C, and 3H, the lower gate insulating layer 222 and the substrate, that is, the semiconductor active layer 103 using the hard mask pattern 203 and the lower gate electrode 225 as a mask. Is etched to a predetermined depth. The etching of the semiconductor active layer 103 is preferably anisotropic etching. As a result, a fifth sub-pillar formed of a material of the semiconductor active layer 103 and extending downwardly as a single body with the lower channel part 122 is formed. The fifth sub pillar forms a lower source portion 130, and the lower source portion 130 has a width wider than that of the lower channel portion 122. The lower source portion 130 includes the lower source region 130a.

The lower gate electrode 225 is insulated from the common drain portion 120 and the lower source portion 130 by the lower gate insulating layer 222.

1E, 2C, and 3I, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the substrate 100 on which the lower source portion 130 is formed, and the lower source region ( Ion implantation is carried out at a higher concentration than the impurity concentration in 130a). As a result, a high concentration impurity region is formed in the semiconductor active layer 103.

1F, 2C, and 3J, the semiconductor active layer 103 having the high concentration impurity region is etched using the hard mask pattern 203 and the lower gate electrode 225 as a mask, and the buried insulation Etch until layer 102 is exposed. Such etching is preferably anisotropic etching. As a result, a sixth sub-pillar formed of a material of the semiconductor active layer 103 and extending downwardly as a unit with the lower source portion 130 is formed. The sixth sub pillar forms the lower storage node electrode unit 140.

Accordingly, the upper source unit 110, the upper channel unit 112, the common drain unit 120, the lower channel unit 122, the lower source unit 130, and the lower storage node electrode unit 140. ) Forms one pillar.

1G, 2C, and 3K, a dielectric material is stacked on a substrate 100 on which the lower storage node electrode unit 140 is formed, and the stacked dielectric material is etched back to expose the buried insulating layer. The dielectric film spacer 242 is formed. The dielectric layer spacer 242 may be formed to surround at least the outer circumference of the lower storage node electrode unit 140. In addition, the dielectric layer spacer 242 may be formed to surround the outer circumference of the lower source portion 130.

A plate electrode material is stacked on the substrate 100 on which the dielectric film spacer 242 is formed. Preferably, the plate electrode material is formed to fill at least the space between the pillars. Subsequently, the stacked plate electrode materials are etched back to a predetermined depth to form a plate electrode 245 surrounding at least the outer circumference of the lower storage node electrode unit 140. The plate electrode 245 is also formed between the lower storage node electrode portions 140 and is formed to surround the outer circumference of the plurality of lower storage node electrode portions 140. Preferably, the height of the plate electrode 245 is higher than the height of the lower storage node electrode unit 140. Meanwhile, the plate electrode material may be doped polysilicon.

Referring to FIGS. 1G, 2C, and 3L, the first interlayer insulating layer 250 is stacked on a substrate on which the plate electrode 245 is formed, and is stacked to a thickness sufficient to fill a space between the pillars. do. Subsequently, the first interlayer insulating layer 250 is planarized until the surface of the hard mask pattern 203 is exposed. In this case, the planarization process may be a chemical mechanical polishing process or an etch back process.

1H, 2D, and 3M, the planarized first interlayer insulating film 250 is selectively etched by using a photolithography method to thereby form a first trench 250a in the first interlayer insulating film 250. Form. The first trench 250a may have a depth sufficient to expose the sidewall of the lower gate electrode 225 without exposing sidewalls of the lower source portion 130 in the first trench 250a. It is formed to extend in the X-axis direction. Accordingly, an upper portion of the dielectric layer spacer 242 formed on the sidewall of the lower gate electrode 225 is exposed in the first trench 250a. Preferably, the width of the first trench 250a is greater than the width between both sidewalls of the lower gate electrode 225.

Subsequently, an upper portion of the dielectric layer spacer 242 exposed in the first trench 250a is etched to expose sidewalls of the lower gate electrode 225 in the first trench 250a. Subsequently, the sidewall of the lower gate electrode 225 may be interfaced using an oxide wet etching solution. Thereafter, a first wiring conductive layer is stacked on the substrate on which the sidewalls of the lower gate electrode 225 are exposed, and the first wiring conductive layer is etched back to an extent that an upper portion of the lower gate electrode 225 is exposed. As a result, a lower word line 255 is formed between the lower gate electrodes 225 adjacent to each other on the X axis. Further, when the first trench 250a is formed larger than the width of the lower gate electrode 225, the lower word line 255 extends in the X-axis direction while surrounding the outer circumference of the lower gate electrode 225. . Accordingly, delay of a signal transmitted along the lower word line 255 may be prevented.

Referring to FIGS. 1H, 2D, and 3N, a second interlayer insulating layer 260 is stacked on a substrate on which the lower word line 255 is formed, and the thickness of the first trench 250a is sufficiently filled. Laminated. Next, the second interlayer insulating film 260 is planarized until the surface of the hard mask pattern 203 is exposed. In this case, the planarization process may be a chemical mechanical polishing process or an etch back process.

1I, 2E, and 3O, a second trench 260a is formed in the planarized second interlayer insulating layer 260 and the first interlayer insulating layer 250. The second trench 260a may be deep enough to expose at least a portion of the sidewall of the common drain 120 without exposing the lower gate electrode 225 in the second trench 260a. It is formed to have, but is formed to extend in the Y-axis direction. Accordingly, a portion of the second insulating spacer 217 of FIG. 3N formed on the sidewall of the common drain 120 is exposed in the second trench 260a. Preferably, the width of the second trench 260a is larger than the width between both sidewalls of the common drain 120.

Subsequently, only portions exposed in the second trenches 260a of the second insulating spacers 217 are etched to expose at least a portion of sidewalls of the common drain part 120 in the second trenches 260a. The gate electrode 225 is not exposed. Subsequently, a second wiring conductive film is stacked on the substrate on which the sidewalls of the common drain part 120 are exposed, and the second wiring conductive film is etched back so that the upper portion of the sidewall of the common drain part 120 is exposed. . As a result, the bit lines 265 are formed between the common drain portions 120 adjacent to each other in the Y-axis direction. Further, when the second trench 260a is formed larger than the width of the common drain portion 120, the bit line 265 extends in the Y-axis direction while surrounding the outer circumference of the common drain portion 120. Accordingly, delay of a signal transmitted along the bit line 265 may be prevented.

Subsequently, referring to FIGS. 1I, 2E, and 3P, a third interlayer insulating layer 270 is stacked on the substrate on which the bit line 265 is formed, and the thickness enough to sufficiently fill the second trench 260a. Laminate. Next, the third interlayer insulating film 270 is planarized until the surface of the hard mask pattern 203 is exposed. In this case, the planarization process may be a chemical mechanical polishing process or an etch back process.

1J, 2F, and 3Q, a third trench 270a is formed in the planarized third interlayer insulating layer 270, the second interlayer insulating layer 260, and the first interlayer insulating layer 250. Form. The third trench 270a may have a depth sufficient to expose at least a portion of the sidewall of the upper gate electrode 215 without the common drain 120 being exposed in the third trench 270a. It is formed to extend in the X-axis direction. Preferably, the width of the third trench 270a is larger than the width between both sidewalls of the upper gate electrode 215.

Subsequently, a third wiring conductive film is stacked on the substrate in which the sidewalls of the upper gate electrode 215 are exposed in the third trench 270a, and the third wiring conductive film is exposed to an upper portion of the upper gate electrode 215. Etch back enough. As a result, an upper word line 275 is formed between the upper gate electrodes 215 adjacent to each other on the X axis. Furthermore, when the third trench 270a is formed larger than the width between both sidewalls of the upper gate electrode 215, the upper word line 275 surrounds the outer circumference of the upper gate electrode 215 and is X. Extend in the axial direction.

Referring to FIGS. 1J, 2F, and 3R, a fourth interlayer insulating layer 280 is stacked on the substrate on which the upper word line 275 is formed, and the third trench 270a is sufficiently filled with the third interlayer insulating film 280. The interlayer insulating film 270 is formed to have a predetermined height. Subsequently, the stacked fourth interlayer insulating film 280 is planarized, but planarized to have a predetermined height from the hard mask pattern 203.

1J, 2F, and 3S, a contact hole 280a is formed in the fourth interlayer insulating layer 280 to expose the hard mask pattern 203.

1K, 2F, and 3T, the pad oxide layer may be removed by removing the hard mask pattern 203 of FIG. 3S and the first insulating spacer 207 of FIG. 3S exposed in the contact hole 280a. An upper portion of 105 of FIG. 3S and a sidewall of the upper source portion 110 are exposed. In this case, an upper portion of the upper gate electrode 215 may also be exposed. The hard mask pattern 203 of FIG. 3S and the first insulating spacer 207 of FIG. 3S may be removed using a wet etching method. Subsequently, the pad oxide layer 105 of FIG. 3S is removed to expose the upper portion of the upper source portion 110. In removing the pad oxide layer 105 of FIG. 3S, the interlayer insulating layer 280 around the contact hole 280a may be partially etched, and thus the width of the contact hole 280a may be somewhat wider. As a result, an upper portion of the upper word line 275 may also be exposed in the contact hole 280a as well as the upper gate electrode 215.

1K, 2F, and 3U, a third insulating spacer layer is stacked on the substrate having the exposed upper source region 110. The third insulating spacer layer may be formed of a material having an etching selectivity with respect to the interlayer insulating layer 280 and the upper source portion 110, for example, a silicon nitride layer. Next, the third insulating spacer layer is etched back to expose the surface of the upper source portion 110 to form a third insulating spacer 283 on the sidewall of the contact hole 280a. As a result, the third insulating spacer 283 may cover the upper portion of the upper gate electrode 215 and the upper word line 275 exposed in the contact hole 280a.

Subsequently, impurities, for example, phosphorus (P) or arsenic (As) ions, are implanted into the upper source portion 110 exposed by the third insulating spacer 283 to form the upper source region.

1K, 2F, and 3V, a contact pad conductive layer is stacked to sufficiently fill the space between the third insulating spacers 283. The conductive film may be a polysilicon film containing n-type impurities. The contact pad conductive layer is planarized until the surface of the fourth interlayer insulating layer 280 is exposed, so that the storage node contact pads 284 are in contact with the upper source portion 110 between the third insulating spacers 283. ).

Subsequently, a storage node electrode layer is stacked on the substrate on which the storage node contact pads 284 are formed, and the electrode layer is patterned to form an upper storage node electrode 285. The electrode film may be a polysilicon film, a titanium film, a nickel film, a titanium nitride film, or a ruthenium film doped with n-type impurities.

1L, 2F, and 3W, an upper dielectric layer 290 is stacked on surfaces of the upper storage node electrode 285 and the fourth interlayer insulating layer 280, and the dielectric layer 290 is formed. A plate electrode 295 is formed on the upper storage node electrode 285.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1L, 2F, and 3W.

First, the substrate 100 is provided. The substrate 100 includes a support substrate 101 and an insulating layer 102 positioned on the support substrate 101. The substrate 101 may be an SOI substrate, and in this case, the insulating layer 102 may be a buried insulating layer of the SOI substrate.

Pillars formed on the substrate 100, that is, in the second direction crossing the first direction and intersecting the first direction, are formed on the insulating layer 102. The first direction may be an X-axis direction parallel to the A-A direction of FIG. 2F, and the second direction may be a Y-axis direction parallel to the B-B direction of FIG. 2F. Each pillar has a lower channel portion 122, an upper channel portion 112, and a common drain portion 120 positioned between the lower channel portion 122 and the upper channel portion 112. The common drain unit 120 includes a common drain region 120a in which impurities are injected. The lower gate electrode 225 surrounding the lower channel portion 122 is positioned at the outer circumference of the lower channel portion 122, and the upper channel portion 112 is surrounded at the outer circumference of the upper channel portion 112. The upper gate electrode 215 is located.

The pillar may further include a sub pillar extending below the lower channel portion 122. The sub pillar may be the lower source portion 130. In addition, the pillar may further include a sub pillar extending to an upper portion of the upper channel portion 112. The sub pillar extending above the upper channel part 112 may be the upper source part 110. Accordingly, the pillar may include an upper source unit 110, an upper channel unit 112, a common drain unit 120, a lower channel unit 122, and a lower source unit 130 that are extended to each other.

The upper source portion 110, the upper channel portion 112, the upper gate electrode 215 formed on the sidewalls of the upper channel portion 112, and the common drain portion 120 are upper transistors (T in FIG. 4). _H ) is formed. Similarly, the lower source portion 130, the lower channel portion 122, the lower gate electrode 225 formed on the sidewalls of the lower channel portion 122, and the common drain portion 120 are lower transistors (FIG. 4). T _L ). As shown, the upper transistor (T _{H in} FIG. 4) and the lower transistor (T _{L in} FIG. 4) are vertical channel transistors. As a result, two vertical channel transistors sharing a drain are formed in one pillar. Alternatively, the pillar may not include the lower source portion 130 and the upper source portion 110. In this case, an upper source region may be formed on an upper portion of the upper channel portion 112 to replace the role of the upper source portion 110. It may be to take the role of the source unit 130. However, by forming the lower source portion 130 and the upper source portion 110, it is possible to implement a stable device operation.

A lower gate insulating layer 222 is interposed between the lower gate electrode 225 and the lower channel portion 122, and the lower gate insulating layer 222 extends to extend the lower gate electrode 225 and the common drain portion ( It is also located between the 120 and between the lower gate electrode 225 and the lower source portion 130. Similarly, an upper gate insulating film 212 is interposed between the upper gate electrode 215 and the upper channel part 112, and the upper gate insulating film 212 extends to the upper gate electrode 215 and the common drain. It is also located between the portions 120 and between the upper gate electrode 215 and the upper source portion 110.

The pillar extends below the lower source portion 130. The region extending below the lower source portion 130 may be the lower storage node electrode portion 140. The concentration of the impurities injected into the lower storage node electrode unit 140 may be higher than the concentration of the impurities injected into the lower source unit 130.

A lower plate electrode 245 surrounding the lower storage node electrode unit 140 is provided on an outer circumference of the lower storage node electrode unit 140. A dielectric layer spacer 242 is interposed between the lower storage node electrode unit 140 and the lower plate electrode 245. Accordingly, the lower storage node electrode unit 140, the dielectric layer spacer 242, and the lower plate electrode 245 form a lower capacitor C _L of FIG. 4. Further, the lower plate electrode 245 extends to be positioned between the lower storage node electrode portions 140, and further surrounds the outer circumference of the plurality of lower storage node electrode portions 140. The lower plate electrode 245 may correspond to the lower plate electrode line P / L _L illustrated in FIG. 4.

The upper storage node electrode 285 may be positioned on the upper source unit 110. In addition, a storage node contact pad 284 may be positioned between the upper source unit 110 and the upper storage node electrode 285. Alternatively, the upper storage node electrode 285 and the storage node contact pad 284 may be integrally formed. An upper plate electrode 295 is provided on the upper storage node electrode 285 to surround the upper storage node electrode 285. An upper dielectric layer 290 is interposed between the upper storage node electrode 285 and the upper plate electrode 295. Accordingly, the upper storage node electrode 285, the upper dielectric layer 290, and the upper plate electrode 295 form an upper capacitor C _{H in} FIG. 4. In addition, the upper plate electrode 295 extends to be positioned between the upper storage node electrodes 285 and is formed to surround the plurality of upper storage node electrodes 285. Therefore, the upper plate electrode 295 may correspond to the upper plate electrode line P / L _H illustrated in FIG. 4.

Meanwhile, a lower word line 255 (W / L _L of FIG. 4) is provided on the lower plate electrode 245 to connect the lower gate electrodes 225 of the pillars arranged in the X-axis direction. Preferably, the lower word line 255 has a shape surrounding the outer circumference of the lower gate electrode 225. The lower word line 255 is insulated from the lower source portion 130 by the dielectric layer spacer 242 and the lower plate by the first interlayer insulating layer 250 disposed on the lower plate electrode 245. It is insulated from the electrode 245.

A bit line 265 (B / L of FIG. 4) intersecting the lower word line 255 is provided on the lower word line 255 and the lower plate electrode 245. The bit line 265 is connected to the common drain portions 120 of the pillars arranged in the Y-axis direction. Preferably, the bit line 265 has a form surrounding the outer circumference of the common drain portion 120. The bit line 265 is insulated from the lower plate electrode 245 by the first interlayer insulating layer 250, and is lowered by the second interlayer insulating layer 260 positioned on the lower word line 255. It is insulated from the word line 255, and is insulated from the lower gate electrode 225 by the second interlayer insulating layer 260 and the insulating spacer 217.

An upper word line 275 is disposed on the bit line 265 and the lower word line 255 in parallel with the lower word line 255. The upper word line 275 is connected to the upper gate electrodes 215 of the pillars arranged in the X-axis direction. Preferably, the upper word line 275 has a shape surrounding the outer circumference of the upper gate electrode 215. In addition, the upper word line 275 is insulated from the lower word line 255 by the second interlayer insulating layer 260 and by the third interlayer insulating layer 270 disposed on the bit line 265. The bit line 265 is insulated from the common drain unit 120.

As described above, since one pillar includes two vertical channel transistors, the planar area of the device is reduced to 1/2 compared with the case of forming one vertical channel transistor in one pillar. Furthermore, when this is applied to a DRAM device having one transistor and one capacitor, two cells are positioned up and down in one unit cell region (C of FIG. 2A). That is, since two cells are positioned up and down in the 4F ² square feature size, the square feature size occupied by one cell becomes 2F ² . As a result, the degree of integration of the DRAM device can be significantly improved.

As described above, according to the present invention, one pillar may include two vertical channel transistors, thereby reducing the planar area of the device, and further increasing the integration degree of the DRAM device when applied to the DRAM device.

Claims (33)

Board; Pillars arranged in a first direction and in a second direction crossing the first direction are positioned on the substrate, wherein each pillar is positioned between the lower channel portion, the upper channel portion, and the lower channel portion and the upper channel portion. A common drain portion; A lower gate electrode surrounding an outer circumference of the lower channel portion; And And an upper gate electrode surrounding an outer circumference of the upper channel portion. The method of claim 1, The pillar further includes a lower storage node electrode portion positioned below the lower channel portion, The semiconductor device may further include an upper storage node electrode positioned on the upper channel part. The method of claim 2, And a lower plate electrode surrounding the lower storage node electrode portions of the pillars. The method of claim 2, The pillar further comprises a lower source portion disposed between the lower channel portion and the lower storage node electrode portion. The method of claim 4, wherein And the lower gate electrode is electrically insulated from the common drain portion and the lower source portion. The method of claim 2, The pillar further comprises an upper source portion disposed between the upper channel portion and the upper storage node electrode. The method of claim 6, And the upper gate electrode is electrically insulated from the common drain portion and the upper source portion. The method of claim 6, And a storage node contact pad positioned between the upper source portion and the upper storage node electrode. The method of claim 1, And a lower word line connecting the lower gate electrodes of the pillars arranged in the first direction. The method of claim 9, And the lower word line surrounds an outer circumference of the lower gate electrode. The method of claim 1, And a bit line connected to common drain portions of the pillars arranged in the second direction. The method of claim 11, And the bit line surrounds the common drain portion. The method of claim 1, And an upper word line connected to the upper gate electrodes of the pillars arranged in the first direction. The method of claim 13, And the upper word line surrounds the upper gate electrode. The method of claim 1, The pillar may further include a lower source portion positioned below the lower channel portion and an upper source portion positioned above the upper channel portion. The method of claim 1, And the substrate has a support substrate and an insulating layer positioned on the support substrate, and the pillars are positioned on the insulating layer. The method of claim 16, The substrate is an SOI substrate, and the insulating layer is a semiconductor device, characterized in that the buried insulating layer of the SOI substrate. Board; Pillars arranged in a first direction and in a second direction crossing the first direction are positioned on the substrate, wherein each pillar is sequentially disposed in the lower storage node electrode portion, the lower source portion, the lower channel portion, and the common drain. A portion, an upper channel portion and an upper source portion; An upper storage node electrode positioned on the upper source portion; A lower gate electrode surrounding an outer circumference of the lower channel portion; An upper gate electrode surrounding an outer circumference of the upper channel portion; A lower word line connecting the lower gate electrodes of the pillars arranged in the first direction; A bit line connected to common drain portions of the pillars arranged in the second direction; And And an upper word line connected to the upper gate electrodes of the pillars arranged in the first direction. Forming hard mask patterns arranged on the substrate in a first direction and a second direction crossing the first direction; Etching the substrate using the hard mask patterns as masks to form columnar upper channel portions having a width narrower than that of the hard mask patterns; Forming an upper gate electrode surrounding the upper channel portion on an outer circumference of the upper channel portion; Etching the substrate by using the upper gate electrode as a mask to form a common drain having a pillar shape; Forming insulating spacers on sidewalls of the common drain portion; Etching the substrate using the hard mask pattern and the insulating spacer as a mask to form a lower channel portion having a pillar shape having a width smaller than that of the common drain portion; And forming a lower gate electrode surrounding the lower channel portion on an outer circumference of the lower channel portion. The method of claim 19, Etching the substrate using the lower gate electrode as a mask to form a lower storage node electrode part having a pillar shape; Removing the hard mask pattern; And forming an upper storage node electrode on the upper channel portion. The method of claim 20, Before removing the hard mask pattern, And forming a lower plate electrode surrounding the lower storage node electrode portions of the pillars. The method of claim 20, Before forming the lower storage node electrode portion, And etching the substrate using the hard mask pattern and the lower gate electrode as a mask to form a lower source portion in the form of a pillar. The method of claim 20, Before forming the upper channel portion, further comprising etching the substrate using the hard mask pattern as a mask to form an upper source portion, The upper storage node electrode is formed on the upper source portion. The method of claim 23, wherein Before forming the upper storage node electrode, forming a storage node contact pad on the upper source portion. The method of claim 19, Forming the upper channel portion may include anisotropically etching the substrate by a predetermined depth using the hard mask pattern to form a sub pillar below the hard mask pattern, and isotropically etching the sidewall of the sub pillar by a predetermined width. Method for manufacturing a semiconductor device, characterized in that. The method of claim 19, Forming an upper gate insulating film on an outer circumference of the upper channel portion before forming the upper gate electrode, The forming of the upper gate electrode includes stacking a gate conductive layer on a substrate on which the upper gate insulating layer is formed, and etching back the gate conductive layer. The method of claim 19, Forming the lower channel portion may include anisotropically etching the substrate by a predetermined depth using the insulating spacer as a mask to form a sub pillar below the common drain portion, and isotropically etch the sidewall of the sub pillar by a predetermined width. Method for manufacturing a semiconductor device, characterized in that. The method of claim 19, Forming a lower gate insulating layer on an outer circumference of the lower channel portion before forming the lower gate electrode, The forming of the lower gate electrode includes stacking a gate conductive film on a substrate on which the lower gate insulating film is formed, and etching back the gate conductive film. The method of claim 19, Forming a lower word line connected to lower gate electrodes respectively formed under the hard mask patterns arranged in the first direction, Forming bit lines connected to common drain regions formed under the hard mask patterns arranged in the second direction, And forming an upper word line connected to upper gate electrodes formed under the hard mask patterns arranged in the first direction, respectively. The method of claim 29, The forming of the lower word line may include forming an interlayer insulating layer on the substrate on which the lower gate electrode is formed. A trench is formed in the interlayer insulating layer, wherein the trench exposes sidewalls of lower gate electrodes respectively positioned under the hard mask patterns arranged in the first direction. A wiring conductive film is laminated in the trench, And etching the wiring conductive layer. The method of claim 29, Forming the bit line forms an interlayer insulating film on the substrate on which the lower gate electrode is formed, A trench is formed in the interlayer insulating layer, wherein the trench exposes sidewalls of common drain portions respectively disposed under the hard mask patterns arranged in the second direction. A wiring conductive film is laminated in the trench, And etching the wiring conductive layer. The method of claim 29, Forming the upper word line forms an interlayer insulating film on the substrate on which the lower gate electrode is formed, A trench is formed in the interlayer insulating layer, wherein the trench exposes sidewalls of the upper gate electrodes positioned under the hard mask patterns arranged in the first direction. A wiring conductive film is laminated in the trench, And etching the wiring conductive layer. The method of claim 19, The substrate is an SOI substrate having a support substrate, a buried insulating layer positioned on the support substrate, and a semiconductor active layer positioned on the buried insulating layer. The upper channel portion, the common drain portion and the lower channel portion is a semiconductor device manufacturing method, characterized in that formed by etching the semiconductor active layer.

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