KR100654009B1 - Spread spectrum communication system utilizing differential code shift keying - Google Patents

Abstract

A spread spectrum data communication system using a modulation technique called differential code shift keying (DCSK) transfers data in the form of time shifts between successive circular rotated waveforms of length T, known as spread waveforms. A plurality of bits are transmitted during each symbol period divided into a plurality of shift indices, each shift index representing a particular bit pattern. The spread waveform is rotated by an amount depending on the data to be transmitted, or transmitted as a difference between two consecutive turns. A correlator 42 using a matched filter with a template of the chirp waveform pattern is used to detect the amount of rotation of the chirp in the received signal for each symbol. The received data is supplied into the shift register 38 to be rotated in rotation. During each rotation shift, the matched filter produces a correlation sum. The shift index selected for each symbol corresponds to the shift index that yields the maximum correlation sum 44. The differential shift index is generated by subtracting the currently received shift index from the previously received shift index. The differential shift index is then decoded to yield the initially transmitted data.

Spread Spectrum, Shift Index, Correlator, Symbol, Sampling

Description

Spread Spectrum Communication System Using Differential Code Shift Keying {SPREAD SPECTRUM COMMUNICATION SYSTEM UTILIZING DIFFERENTIAL CODE SHIFT KEYING}

The present invention relates generally to data communication systems, and more particularly to spread spectrum communication systems that use differential code shift keying to transmit and receive data.

The use of spread spectrum communication technology to improve the reliability and security of communication is well known and increasingly common. In spread spectrum communication, data is transmitted using a spectral bandwidth much larger than the bandwidth of the data to be transmitted. This provides more reliable communication in the presence of high narrowband noise, spectral distortion and pulsed noise, as well as providing other advantages. Spread-spectrum communication systems generally use correlation techniques to identify incoming signals.

Spread-spectrum communication systems are commonly used in military environments to overcome high energy narrowband relative jamming. In a commercial or home environment, the system can be used to implement high reliability communications on noise media such as AC power lines. In particular, certain household electrical appliances and devices have the potential to severely disrupt communication signals on power lines. For example, electronic dimming devices typically use a triac or silicon controlled rectifier (SCR) to control the AC waveform when performing the dimming function, resulting in a large amount of noise on the power line.

Communication media, such as AC power lines, can be damaged by high speed fading, unpredictable amplitude and phase distortion, and other noise. In addition, the communication channel may be subject to unpredictable time varying jamming and narrowband interference. In order to transmit digital data over such a channel, it is desirable to use as wide a bandwidth as possible for data transmission, which can be realized by using spread spectrum technology.

In one form of universal spread spectrum communication, a so-called direct sequence spread spectrum is first generated by modulating digital data and then multiplying the result with a signal having desirable spectral characteristics, in particular a PN sequence. The PN sequence is a periodic sequence of bits with period N. Each bit in this sequence is called a chip. Sequences have very low autocorrelation for greater than one chip delay. In some systems, the PN sequence is replaced with a chirp waveform.

Spread-spectrum receivers are generally required to perform synchronization that is performed using an acquisition method in combination with a tracking loop or other tracking mechanism. In environments where noise is unpredictable, such as AC power lines, tracking routes usually cause loss of information. Communication systems for overcoming these problems are large, complex and expensive. Also, such a system typically only pays off when only one or two bits per symbol are transmitted.

The present invention relates to a spread spectrum data communication system that uses a modulation technique called differential code shift keying (DCSK) to increase the number of bits transmitted per symbol, reduce synchronization requirements, and improve performance. This data is transmitted in the form of time shifts between successive circularly rotated length T waveforms called diffusion waveforms. The diffusion waveform may be of any type of waveform having suitable autocorrelation characteristics. In the example presented here, a standard CEBus chirp may be used as the spread waveform to allow coexistence of the standard CEBus transmission with the transmission generated by the communication system of the present invention.

During each symbol period, also called unit symbol time (UST), a plurality of bits are transmitted. The symbol period is divided into a plurality of shift indices, each shift index representing a particular bit pattern. The waveform is rotated by an amount according to the data to be transmitted. The data is delivered in the amount of rotation applied to the concubine before it is sent. In addition, data may be conveyed with a shift difference between successive symbols. The correlator is used to decode the received waveform. This correlator uses a matched filter with a template of the chirp waveform pattern to detect the amount of chirp rotation in the received signal for each symbol. The received data is supplied to the shift register and rotated cyclically. During each rotation shift, the matched filter generates a correlation sum. The shift index selected for each UST corresponds to the shift index for which the maximum (or minimum) correlation sum is calculated. The differential shift index is obtained by subtracting the currently received shift index from the previously received shift index. This differential shift index is then decoded to yield the initially transmitted data.

The transmitter sends data to the receiver in the form of a packet. The start field of the packet is placed at the beginning of the packet. The receiver uses linear correlation to examine the correlation peak over all possible shifts of each received symbol. If the start field of a packet is detected, the receiver looks at two consecutive zeros. If two consecutive zeros are received within the start field of the packet, synchronization occurs. Once synchronized, the recursive correlation is used to receive the rest of the packet. Differential data sent by the transmitter is encoded with a shift distance computed between two consecutive symbols. Differentiators in the receiver generate differential data. Then, integrating the difference data helps to avoid double error results.

The present invention discloses two embodiments, called a fast embodiment and a high reliability embodiment. When used with a standard 100 microsecond CEBus chirp, high speed embodiments can achieve data rates up to approximately 50 Kbps. High reliability embodiments use longer spread waveform lengths to increase transmission reliability. The receiver also divides the input signal into two or more separate frequency bands. Each band receives it, generating a correlation sum. The correlation results of each band are combined to determine the maximum correlation shift index. In the example presented here, the high reliability embodiment constitutes a symbol called supercheap, which is 800 microseconds in duration, from eight chirps, each 100 microseconds. The entire superpatch is cyclically shifted in accordance with the data to be transmitted. The correlator in the receiver with the template of the supercomb pattern is used to detect and decode the supercomb from the received signal.

The spread spectrum communication system of the present invention has the advantages of high reliability transmission, simplicity, high speed synchronization and fast recovery from severe fading. Further, using symbol periods, such as conventional direct sequence spread spectrum communication systems, multiple data bits may be transmitted per symbol to allow longer periods or higher data yields for each symbol. Another advantage of the system is to provide a channel strength characterized by the frequency change signal to noise ratio. In addition, the present invention can be implemented at low cost, such as a single VLSI integrated circuit.

Thus, according to the present invention, there is provided a method of communicating over a communication channel from a transmitter to a receiver, wherein both the transmitter and the receiver are connected with the communication channel, wherein the communication method, in the transmitter, each symbol is to be transmitted within this symbol. Generating a plurality of symbols constructed using a spread waveform cyclically shifted by an amount in accordance with the data, placing the plurality of symbols on a communication channel, receiving a signal from the communication channel at a receiver, receiving Decoding the plurality of symbols at the receiver by correlating the received signal with a template corresponding to a spread waveform.

Further, according to the present invention, there is provided a method of communicating over a communication channel from a transmitter to a receiver, wherein both the transmitter and the receiver are connected with the communication channel, wherein the communication method, at the transmitter, each symbol is to be transmitted within this symbol. Generating a plurality of symbols constructed using a spread waveform cyclically shifted by an amount in accordance with the data, placing the plurality of symbols on a communication channel, receiving a signal from the communication channel at a receiver, Correlating the received signal with a template corresponding to the spreading waveform to decode a plurality of symbols at the receiver to issue a differential shift index indicating a time shift between successive cyclic shifts of the spreading waveform.

The diffusion waveform may be composed of a chirp waveform or a superchirp waveform composed of a plurality of individual chirps. In addition, the decoding step includes cyclically shifting each received symbol by a total amount equivalent to one symbol length, correlating the received symbol with a template corresponding to the spread waveform during each cyclic shift of the received symbol; Generating a shift index corresponding to the maximum correlation sum, and decoding the shift index to produce an initial transmitted data.

The decoding step also includes cyclically shifting each received symbol to a total amount equivalent to one symbol length, correlating the received symbol with a template corresponding to the spread waveform during each cyclic shift of the received symbol; Generating a first shift index and a negative shift index respectively corresponding to the positive correlation sum and the negative correlation sum, and decoding the first shift index and the second shift index to calculate the first data output and the second data output, respectively; And outputting the first shift index or the second shift index based on the maximum of the positive correlation sum and the negative correlation sum.

According to the present invention, there is provided a spread spectrum communication system for communicating over a communication channel, wherein the system uses a spread waveform that is cyclically shifted by an amount in accordance with the data to be transmitted in this symbol, each symbol being connected to the communication channel. And a receiver coupled with the communication channel, the receiver generating a plurality of symbols, and decoding the plurality of symbols by receiving a signal from the communication channel and correlating the received signal with a template corresponding to a spread waveform.

According to the present invention, there is also provided a method of generating a signal to be transmitted over a communication channel from an input bit stream and using a spread waveform, the method comprising the steps of: forming a serial stream of shift indices from the input bit stream; Determining an initial index according to each shift index in the serial stream of indexes, cyclically shifting the spreading waveform according to the initial index, and transmitting the cyclically shifted spreading waveform on a communication channel. .

According to the present invention, there is also provided a method for generating a spread spectrum signal for transmission over a communication channel from an input bit stream and using a spread waveform, the method comprising: forming a shift index from the input bit stream; Determining an initial index according to the equation;

Cyclically shifting the spread waveform in accordance with the initial index, and transmitting the cyclically shifted spread waveform on the communication channel. The method further comprises calculating a differential shift index by differentiating the input bit stream.

According to the present invention, there is also provided a transmitter for generating a signal to be transmitted over an communication channel from an input bit stream and using a spread waveform, the transmitter comprising means for forming a shift index from each group of n bits in the input bit stream. And means for determining an initial index according to the shift index, means for cyclically shifting the spread waveform according to the initial index, and means for providing the cyclically shifted spread waveform over the communication channel.

The means for cyclically shifting the spreading waveform comprises counting means adapted to receive an initial index and look up table means for outputting sample positions of the spreading waveform corresponding to the output of the counting means. The transmitter further includes a differential that differentials the input bit stream to produce a differential shift index.

In addition, according to the present invention, there is provided a receiver connected to a communication channel for receiving a plurality of symbols consisting of a spread waveform in which each symbol is cyclically rotated by an amount according to data to be transmitted for a specific symbol time, wherein the receiver comprises a receive input. Each cycle of the shift means using a sampling means for sampling the signal, a shift means having a plurality of taps while rotating the output of the sampling means, and a template connected to the plurality of taps of the shift means and corresponding to the diffusion waveform. Correlation means for generating a correlation sum during the shift and generating a plurality of correlation sums for each received symbol, a maximum correlation detection means for determining a maximum correlation sum from the plurality of correlation sums, and a shift index associated with the maximum correlation sum It includes a data decoder to decode and generate its output.

According to the present invention, there is also provided a receiver, connected to a communication channel, for receiving data decoded as a plurality of symbols in which each symbol is transmitted using a spreading waveform, the receiver receiving the received input signal at a plurality of frequencies. Signal splitting means for dividing into bands, each outputting a plurality of band pass signals associated with a single frequency band, sampling means for sampling the plurality of band pass signals, and an output of the sampling means, respectively. A correlation means for correlating for each frequency band and generating a plurality of band correlation sums for each frequency band, a summation means for summing each of the plurality of band correlation sums to yield a plurality of correlation sums, and a maximum correlation from the plurality of correlation sums Maximum correlation detection means for determining the sum, and the maximum correlation sum is used to decode the received symbols and generate the output. It comprises means for decoding data.

According to the present invention, there is also provided a receiver connected to a communication channel to receive data encoded into a plurality of symbols consisting of a spread waveform in which each symbol is cyclically rotated by an amount according to the data to be transmitted for a particular symbol time. The receiver comprises: signal splitting means for dividing a received input signal into a plurality of frequency bands, each outputting a plurality of band pass signals associated with a single frequency band, and a plurality of sampling the plurality of band pass signals And a sampling means of circulating rotation of the output of each sampling means associated with each frequency band, each of the plurality of shift means each having a plurality of taps, and each of which is connected to an output of one of the shift means, A correlation sum is generated during each cyclic shift of the shift means using the corresponding template, each of which corresponds to each received symbol. A plurality of correlation means for generating a plurality of band correlation sums, a summation means for summing a plurality of band correlation sums respectively output by each correlation means to generate a plurality of correlation sums, and a maximum correlation sum from the plurality of correlation sums. Means for determining a maximum correlation and a data decoder for decoding the shift index associated with this maximum correlation sum and generating its output.

The receiver is further connected with an output of the maximum correlation detecting means, further comprising a differencer for generating a differential shift index corresponding to the time difference between two successive circularly rotated spread waveforms.

The receiver further comprises an integrator connected to the output of the data decoder, integrating the output of the data decoder. The signal splitting means comprise a plurality of band pass filters each having a bandwidth and a center frequency according to its frequency band. Sampling means include a 1-bit analog to digital converter or comparator and sample circuit. The sampling means comprises means for generating both an I or in phase data stream and a Q or quadrature data stream, wherein the Q data stream is time delayed by a predetermined amount relative to the I data stream.

Said correlation means comprise complex correlation means. Complex correlation means include means for applying a nonlinear function to the plural correlation results. This nonlinear function is a receiver that contains a squared function.

According to the present invention, there is also provided a method for receiving data encoded as a plurality of symbols and transmitted over a communication channel, wherein each transmission symbol uses a spread waveform, the method comprising: receiving a plurality of received input signals; Dividing into frequency bands of C, generating a plurality of band pass signals, each associated with a single frequency band, sampling the plurality of band pass signals to produce a sample stream, and generating a plurality of band correlation sums Correlating a sample stream associated with each frequency band to each other, summing a plurality of band correlation sums respectively to generate a plurality of correlation sums, determining a maximum correlation sum from the plurality of correlation sums, and the maximum correlation Decoding the shift index for each received symbol using the sum and generating the output.

According to the present invention, there is also provided a method for receiving data encoded as a plurality of symbols and transmitted over a communication channel, each symbol having a spread waveform that is cyclically rotated by an amount according to the data to be transmitted for a particular symbol time. And the method comprises: dividing a received input signal into a plurality of frequency bands, generating a plurality of band pass signals, each associated with a single frequency band, sampling the plurality of band pass signals to sample a stream of samples; Calculating, circulating a sample stream of each frequency band, and correlating the cyclically rotated sample stream for each frequency band using a template corresponding to the spread waveform, and generating a band correlation sum for each cyclic rotation. Calculating a plurality of band correlation sums for each symbol, and generating a plurality of correlation sums. Summing a plurality of band correlation sums for each frequency band, determining a maximum correlation sum from the plurality of correlation sums, and decoding a shift index associated with the maximum correlation sum and generating an output thereof. do.

Further, according to the present invention, in a spread spectrum communication system for communicating over a communication channel connected to both a transmitter and a receiver, a method for synchronizing the receiver is provided, which method performs a zero differential shift with respect to each other. Transmitting a plurality of spreading waveforms having a plurality of spreading waveforms, receiving and decoding the plurality of spreading waveforms, and synchronizing when receiving a minimum predetermined number of spreading waveforms having zero differential shifts from each other. Each diffusion waveform has a rotational shift of zero.

The invention is described with reference to the accompanying drawings as an example.

1 is an example of a chirp waveform suitable for use in a spread spectrum communication system of the present invention.

2 is an example of a sample symbol stream waveform generated by rotating each chirp pattern by a representative amount of data to be transmitted.

3 illustrates a packet structure of the data communication protocol of the present invention.

4 is a high level block diagram illustrating a transmitter of the first embodiment of the present invention.

5A and 5B are high level block diagrams illustrating a receiver of a first embodiment of the present invention.

6 is a high level diagram illustrating a transmitter of a first embodiment of the present invention suitable for transmitting differential data or absolute data with separate non-data symbols.

7A and 7B are high level block diagrams illustrating in more detail the receiver of the first embodiment of the present invention.

8 is a high level flowchart illustrating a preamble and synchronization reception method according to a first embodiment of the present invention.

9 is a high level flowchart illustrating a cyclic mode reception method of the first embodiment of the present invention.

10 is a high level flowchart illustrating the linear tracking correction method of the present invention.

FIG. 11 is an example of a super chirp waveform generated from a plurality of single chirps and consisting of one super UST.

12 is a high level block diagram illustrating a transmitter of a second embodiment of the present invention.

FIG. 13 is a high level diagram illustrating a transmitter of a second embodiment of the present invention suitable for transmitting differential data or absolute data with separate non-data symbols.

14A, 14B and 14C are high level block diagrams illustrating a receiver of a second embodiment of the present invention.

15 is a high level flowchart illustrating a preamble and synchronization reception method according to a second embodiment of the present invention.

16 is a high level flowchart illustrating a cyclic mode reception method of a second embodiment of the present invention.

The present invention is a spread spectrum data communication system suitable for a relatively noisy environment such as an AC power line. Two other embodiments of the spread spectrum data communication system of the present invention are described. The first embodiment, also called the high speed embodiment, includes a transmitter and receiver pair capable of relatively high speed data communication. The second embodiment, also called a high reliability embodiment, has a lower data transmission rate than the first embodiment, but there are transmitter and receiver pairs that communicate at a higher confidence level. Both embodiments of the present invention are particularly suitable for use in an environment including a modem operating according to the CEBus communication standard. High speed embodiments can transmit data at much higher rates than the current CEBus standard can. The CEBus standard is defined by the Electronics Industry Association and is known as EIA-600.

The spread spectrum system of the present invention transfers data in the form of time shifts between successive circularly rotated length T waveforms called spread waveforms. The diffusion waveform may be composed of any type of waveform having suitable autocorrelation characteristics. Preferably, the diffusion waveform consists of a chirp waveform. An example of a chirped waveform, i.e., a spread waveform suitable for use in the spread spectrum communication system of the present invention, is shown in FIG. The spread waveform shown in FIG. 1 spans a period called unit symbol time UST. During each symbol period or UST, a plurality of bits are transmitted. The symbol period is divided into a plurality of shift indices, each shift index representing a particular bit pattern. The spread waveform is rotated by an amount according to the data to be transmitted. The data is delivered in the amount of rotation applied to the concubine before it is transmitted. In addition, data is conveyed in shift differences between successive symbols. In general, the chirp includes a swept frequency signal. For example, the frequency sweep can span 200 to 400 KHz, 100 KHz to 200 KHz as in the concubines specified in the CEBus standard. Alternatively, the chirp can include the swept frequency waveform shown in FIG. 1.

The spread spectrum communication system of the present invention transmits data using a technique known as differential code shift keying (DCSK). Using this technique, data is transmitted in the form of a time shift between successive circularly rotated spread waveforms, or its own shift in absolute form. The spread waveform can be configured with standard CEBus to avoid problems in the CEBus modem environment. Where interoperability with non-CEBus environments or CEB devices is not critical, the present invention may use other spreading waveforms.

An example of a sample symbol stream waveform generated by rotating each chirp pattern by a representative amount of data to be transmitted is shown in FIG. The DCSK modulation scheme of the present invention transmits data by rotating a chirp waveform by a certain amount according to the data to be transmitted. Thus, during each UST, the chirp starts at the point of the chirp waveform corresponding to the data to be transmitted during that particular UST. 2, four USTs showing a sample symbol stream are shown. Data to be transmitted in each UST is delivered in the amount of rotation applied to each chirp waveform. For example, in the first UST, the chirp waveform is rotated by a certain amount indicated by the length of the horizontal arrow. Arrows pointing vertically downward indicate the beginning of the initial chirp waveform to which no rotation is applied. Within each UST, the amount of rotation applied to the concubines is determined before the data is transmitted.

The DCSK modulation method of the present invention is advantageous in that it is resistant to synchronization error, is relatively easy to implement, and exhibits a performance similar to that of an error correction code in the appearance of white Gaussian noise. In operation, each UST is divided into a predetermined number of shift indices or shift positions. In the example presented here, each UST is divided into 32 shift indices. However, each UST may be divided into a plurality of shift indices higher or lower than 32. Each UST is divided into 32 bits and transmitted at a rate of 5 bits per symbol. Hereinafter, the high reliability embodiment will be described following the high speed embodiment.

The packet structure of the data communication protocol unit of the present invention is shown in FIG. In general, the packet structure of the present invention is composed of a preamble, a start of packet (SOP) field, an L byte data field, and a cyclic redundancy check (CRC) field in the same manner as the CEBus packet structure. However, the packet structure of the present invention includes additional fields. The preamble unit 450 is similar to the preamble field defined in the CEBus standard. The start (SOP) field 452 of the packet consists of the symbol '1111' which is recognized as three consecutive zeros by the receiver of the present invention. Note that '1' in the start field of the packet indicates an absolute shift of zero, and the term 'zero' indicates a differential shift of zero.

The term DCSK is derived from the fact that the receiver detects a difference in rotation between received consecutive symbols. If the two last zeros of the start field of the packet are detected, the receiver may receive synchronously. Protocol version 454 is a three bit field containing the protocol version used for the particular packet. The protocol version field allows for various types of transport protocols, for example, from high data rate to low data rate. This field also allows any user protocol to be executed. The protocol version field is transmitted using one symbol and is required to detect the end of the start field and the protocol version field of the packet by having a shift value other than zero appropriate for the receiver. In addition, the protocol version field should be transmitted using a fixed number of bits per symbol known by the receiver. This ensures that the receiver can receive and decode the protocol version field. Once decoded, another receive mode can be set. The remaining structure and coding of the packet is also determined by the protocol version field. This includes the number of bits per symbol, ie the number of chirp shifts per symbol time. In general, five bits are transmitted for each symbol consisting of a concubine.

Packet length 456 is a seven bit field that indicates the size of the packet in bytes. In general, the packet size is limited to a certain number, such as 128 bytes or 1024 bits. The header error detection code (HEDC) 458 is an 8-bit field containing a packet length field and an error detection code for the protocol version. The data field 460 consists of a sequence of DCSK data bundles. The beginning of this field is aligned to the chirp boundary, and the length L bytes of the field is determined by the packet length field. The cyclic redundancy check (CRC) field 462 is composed of a 16-bit error detection field. This field is subsequently followed by a DCSK data chirp without any chirp boundary assignment. If any bits remain unused after the CRC field, they are zero padded at the end of the final chirp.

Hereinafter, the transmission unit of the communication system of the present invention will be described in more detail. A high level block diagram illustrating a transmitter of a high speed embodiment of the present invention is shown in FIG. The transmitter and receiver of the present invention will be described in the case where the chirp or symbol time is divided into 32 shift indices. Thus, five bits are transmitted at one time during each symbol time. However, those skilled in the art can modify the receiver and transmitter of the present invention to transmit more or fewer bits per symbol period. Referring to FIG. 4, the host supplies data to be transmitted to the transmitter, which is generally indicated at 12. The host supplies the data to be transmitted with the header and CRC fields already generated. The host used to form the shift index is input to the initial index portion 14 of the transmitter. The shift index includes a number in the range of 0 to 2 ⁿ −1, where 'n' indicates the number of bits transmitted per symbol time. In the example described here, 'n' is five. Thus, the shift index includes a number in the range of 0 to 31. The initial index in the chirp is computed by dividing the chirp's length by the total number of symbols in the encoding set of ²ⁿ , for example, and multiplying it by the shift index, as given below.

In this example, the chirp length is set to 512. Thus, each concubine is divided into 32 indexes, each of which is spaced 16 apart from each other, i.e. 0, 16, 32, and so on. The initial index is then input to a counter 16 that counts the chirp length, i. The sync signal serves to clear the counter initially. The output of the counter is supplied to the address input portion of the condensed sample read only memory (ROM) 18. The ROM includes a digitized representation of the chirp frequency waveform. The output of the ROM is input to the D / A converter 20, and the analog output of the D / A converter 20 is first filtered by a band pass filter (BPF) 21 having an appropriate pass band according to the signal width. do. Thereafter, the output of the BPF is amplified by the output amplifier 22. The output of this amplifier includes a transmission output signal.

Hereinafter, the receiver of the communication system of the present invention will be described in more detail. A high level block diagram illustrating a receiver of a high speed embodiment of the present invention is shown in FIG. The received signal is input to a band pass filter (BPF) 32, and the bandwidth of the band pass filter 32 is wide enough to receive the frequency range transmitted within the chirp. The output of the band pass filter is input to the 1-bit A / D converter 34. This 1-bit A / D converter can include a comparator combined with a sampler clocked at the appropriate sampling frequency. The output of the A / D converter is input to one of the two inputs of the shift register # 1 35 and the multiplexer (mux) 40. The output of the multiplexer is input to the second shift register # 2 38. For illustrative purposes, the length of both shift registers # 1 and # 2 are each 256 bits long. 256 bits output from shift register # 1 are input to shift register # 2, respectively. The output of shift register # 2 is input to correlator 42. This correlator is implemented using a matched filter that functions to recognize the chirp pattern. The chirp pattern is stored as a template in the correlator and used to detect the presence or absence of a chirp from the received input signal. The serial output of shift register # 2 is wrapped around to the second input of multiplexer 40. The select output of the multiplexer is controlled by a linear / cyclic control signal.

Receiver 30, generally referred to as 30, can operate in linear or cyclic mode. During linear mode operation, the multiplexer is set to select the output of the A / D converter as the input of shift register # 2. Before synchronization occurs, the correlator is set to operate in linear mode. As each bit is received, this bit is clocked into shift register # 2. The output of shift register # 2 is input to correlator 42. Each bit entered into the correlator is multiplied by a corresponding bit from the template. Thereafter, all 256 multiplication values are summed to form the output of the correlator. The multiplication of the template bits in the correlator with each input bit can be performed using the XOR function.

The sum output of the correlator is input to the maximum correlation detector 44. During each symbol period, the maximum correlation detector serves to determine the maximum of all 256 sums output by the correlator. The maximum correlation detector outputs two values upon detecting the maximum correlation sum. The first value N _MAX indicates the position within 256 possible shifts associated with the maximum correlation sum. In addition, the value S _MAX is determined to be the maximum and represents a particular correlation sum associated with the position indicator N _MAX . Thus, the value N _MAX can take a predetermined value in the range of 0 to 255. Then, the shift index for which the maximum correlation is calculated is input to the next quarter. This divider consists of a summer 50, a delay unit 52 and a second summer 54. The delay circuit 52 delays the input value by one unit symbol time. The output of the delay unit is subtracted from the modulo chirp length of the current index value via summer 54. The output of summer 54 indicates the difference or delta shift between the two shifts detected corresponding to two consecutive symbol times.

The output of the summer and the autocorrelation maximum S _MAX are input to the differential data decoder 56. The differential data decoder functions to map the shift index, which may be in the range of 0 to 255, according to the initial data transmitted to a value in the range of 0 to 31.

In the cyclical operation mode, the output of the 1-bit A / D converter 34 is input to the shift register # 1 36. The received data is clocked into shift register # 1 until it is completely filled. At this time, the shift register contains data representing the complete symbol time. Once fully populated, the contents of shift register # 1 are loaded in parallel in shift register # 2. Multiplexer 40 is selected to wrap serial data from shift register # 2 and return the serial data to shift register # 2. The counter 46 functions to count the length of the chirp, which is normally one UST wide. The initial sync signal is used to initially reset the counter. The load signal output from the counter is input to the shift register # 2, and serves to provide timing for dumping the contents of the shift register # 1 to the shift register # 2. Shift register # 2 is clocked by the same multiple as the number of bits constituting the length of this shift register. Each time the shift register rotates, the correlator generates a sum input to the maximum correlation detector. Every time the shift register rotates 256 turns. The maximum correlation detector outputs N _MAX and S _MAX corresponding to the index that yielded the maximum correlation sum and its maximum sum. The counter supplies the count index to be input to the maximum correlation detector. This index supplies a counter value for each revolution of shift register # 2.

The tracking correction circuit 48 fine tunes the value in the counter based on the symbol unit. The tracking correction circuit functions to fine tune the value in the counter based on the symbol unit. The small difference between the received index and the ideal index is used as input to the tracking correction circuit 48. The positive or negative error signal is output by the tracking correction circuit and input to the counter. This error signal serves to fine tune the values in the counter to better track the reception and correlation of the chirp within each symbol time.

The transmitter 12 shown in FIG. 4 transmits data using the absolute value transmission mode. In this mode, all 2 ⁿ symbols are sent directly with no difference or integration. Each five bit symbol is used to directly determine the rotation shift index for each chirp in the UST. Thus, the receiver 30 shown in FIG. 5 includes an integrator 62 that functions to integrate the delta shift generated by the differential data decoder. In addition, additional transmission and reception modes are possible. For example, because the transmitter is used in differential mode, the transmitter integrates this data into a modular chirped length before the data is transmitted. Thus, the receiver must differential the received data for proper reception, as in the receiver shown in FIG. In this case, however, no integrator is necessary. In another example, data is first differentially modulated by the number of shift indices in the transmitter, encoded, and then integrated before being applied to the chirp sample ROM. Thus, the receiver first differentiates the data, decodes the output of the difference, and finally integrates the output of the decoder to form the output of the receiver. The encoder in the transmitter serves to encode the entire symbol, including both data and non-data symbols.

This final example can be used to encode a separate symbol that is not in the data symbol set with a data symbol ( ^2N or some other number). In the 5-bit example presented here, the total number of symbols greater than 32 is to be transmitted, some of which are non-data symbols. To implement this, the chirp symbol time is divided into a plurality of shift indices greater than 32 to accommodate separate non-data symbols.

6 is a high level diagram illustrating a transmitter of a fast embodiment of the present invention suitable for transmitting differential data or absolute data with separate non-data symbols. In order to transmit data using the differential transmission mode, an optional difference 72 is not necessary. The host supplies data that acts as a shift index to the initial index computation unit 80. The shift index in the chirp symbol is computed and input to an integrator 85 composed of a summer 82 and a delay unit 84. Summer 82 adds modulo 2 ⁿ , that is, modulo 32. The output of the summer is delayed and then added together with the output of the initial index computation unit 80. The output of the integrator is input to a counter 86 which functions in the same manner as the counter of the transmitter shown in FIG. The chirp sample ROM 88, D / A converter 90, band pass filter (BPF) 91 and output amplifier 92 function similarly to the corresponding components in the transmitter shown in FIG.

Hereinafter, the receiver of the communication system of the present invention will be described in more detail. A high level block diagram illustrating a receiver of a high speed embodiment of the present invention is shown in more detail in FIGS. 7A and 7B. The analog received data is input to a band pass filter (BPF) 102, and the bandwidth of the band pass filter 102 is set over the frequency range of the chirp waveform. The output of the BPF filter is input to the 1-bit A / D converter 104, which can be implemented using a comparator in combination with a sampling circuit. The output of the A / D converter is input to shift register # 1 106 and multiplexer (mux) 114. The output of this multiplexer 114 is input to shift register # 2 108, and the serial output of this shift register # 2 108 is wrapped around the second input of the multiplexer. As in the receiver of Figure 5, the multiplexer is selected by linear / cyclic control signals.

Receive in linear mode is used during the preamble for synchronization. Once synchronization is made, a circular receive mode is used to demodulate the rest of the packet. During the linear mode of operation, the multiplexer is selected to input data from A / D converter 104 to shift register # 2. Since each bit is shifted through shift register # 2, correlator 110 generates a summation output that is input to maximum correlation detector 112. Once synchronization is achieved, the receiver is switched to a cyclic mode of operation. In this mode, data for the entire UST is shifted to the shift register # 1, and when a load command is issued from the counter 116, the entire contents of the shift register # 1 are transferred to the shift register # 2. The contents of shift register # 2 are then rotated bit by bit through multiplexer 114. The output of shift register # 2 is input to correlator 110 which acts as a matched filter. The 256 bits of shift register # 2 are each multiplied by corresponding bits of the template stored in correlator 110. The 256 multiplication values are then summed to produce the output of the correlator. This multiplication can be performed using the XOR gate. After proper conversion, a summation is generated that the correlator can have both positive and negative signs.

The correlator can also implement a matched filter using less than 256 taps. The number of taps used by the correlator can be reduced by nearly one third of the total number of taps corresponding to the number of bits in shift register # 2. This can be implemented by sampling the template against a threshold of both the positive and negative values of the template. The positive value of the template is compared to the positive threshold, and any value below this threshold is discarded and not used. Similarly, the negative value of the template is compared with the negative threshold so that any value below this negative threshold is also discarded and not used. In this way the number of taps can be reduced by almost two thirds. This can substantially improve performance since noise cannot be generated through the removed taps and does not affect the output sum of the correlator.

The sum of the outputs of the correlator is input through a maximum correlation detector, which finds the maximum correlation sum of both the positive and negative values of the sum in each UST. This maximum correlation detector outputs two shift indices each representing the maximum correlated shift value of both the positive and negative values of the correlation sum, N _POS and N _NEG . In addition, the corresponding absolute values of the correlation sum of both the positive and negative correlation maximums are also output to S _POS and S _NEG , respectively. The sum values S _POS and S _NEG are input to low pass filters (LPFs) 150 and 152, respectively. The correlation sum is smoothed before entering the comparator 154. Comparator 154 functions to determine the maximum between the positive and negative correlation sums. The output of the comparator forms the basis for selecting positive index N _POS or negative index N _NEG .

The positive index is input to the positive reception logic circuit 144 and the negative index is input to the negative reception logic unit 146. Since both the positive and negative receive logic circuits function the same, only the positive receive logic circuit is described for convenience of description. The index output by the maximum correlation detector is first differentiated. The divider consists of a summer 126, a delay unit 128, and a summer 130. The differencer generates shift deltas between each shift index found by the maximum correlation detector. This delta shift value is then rounded to the nearest shift value. In the example presented here, a symbol having 5 data bits and a shift register having 256 bits are used to transfer the shift indexes separated by 8 bits from each other. Thus, the delta shift index output by the differencer is rounded to the nearest 8-bit multiple, i.

The rounded delta shift index is then input to the differential data decoder 136, which functions to decode the shift index to a value between 0 and 31 representing the transmitted data. If the transmitter is set to absolute transmission mode, i.e., a mode that straight encodes data bits into symbols without difference or integration, the output of the differential data decoder indicates the differences between symbols and integrates to recover the transmitted initial data. Need to be. Integrator 148 is comprised of summer 138 and delay circuit 140. The current shift index, consisting of values in the range 0 to 31, is added to modulo 32 along with the previous output of the summer. This value forms the receiver's output data and represents the 5 bits initially transmitted.

The output of the integrator 148 is input to the multiplexer 142 together with the output of the corresponding integrator and negative receive logic operation unit 146. The output of comparator 154 serves as the select input of multiplexer 142. Thus, the index that yielded the high correlation sum is used to determine the received output data.

The receiver also includes a linear mode tracking correction circuit 118 that functions to check the shift index near the upper edge of the UST. During operation of the receiver, it is not desirable for the correlation peak to occur close to the top of the UST. With a very high shift index, the correlation peak can span the boundary between two UST periods. Thus, upon detecting that a peak occurs near the UST boundary, the linear mode tracking correction circuit serves to adjust the counter value approximately 10% to shift the correction peak away from the UST boundary.

The value output by the linear mode tracking correction circuit is subtracted from the counter. The change in the counter value is effective to readjust the symbol reference point for the receiver so that the correlation peaks do not span the boundaries between the symbols. Note that the linear mode tracking correction circuit operates during the linear mode of operation used to receive the start field of the packet. Once tracking and synchronization is complete, the receiver switches to circular receive mode for the rest of the packet.

In addition to providing a correction to the counter, the linear mode tracking correction circuit also supplies a correction signal to summer 126, which is part of the differencer in positive receive logic 144. Similarly, the correction signal is supplied to the corresponding summer in negative reception logic circuit 146. A correction signal to the summer is needed to maintain the counter value synchronized to the next quarter.

In addition, the receiver 100 operates to compensate for clock drift in both linear and cyclical modes of operation. The correction signal is generated based on the difference between the differential shift index before and after rounding to the nearest full shift value. The round off shift value is input to summer 134. The rounded shift value is then subtracted from the unrounded shift value and the difference is low pass filtered and used to adjust the value in the counter 116. Depending on whether the comparator 154 is selected to use a positive or negative shift index, the multiplexer 124 has the ability to pass a value from the positive receive logic or negative receive logic to the low pass filter 122. do. The output of the low pass filter functions to smooth the round off correction value before being input to summer 120. Overflow on summer 120 output causes the counter to reload to zero for a new count. The correction signal from the low pass filter is subtracted from the counter's current value by a summer. The clock drift correction signal output from both summer 134 in the positive receive logic and the corresponding summer in the negative receive logic may have a positive or negative sign. Using this technique, synchronization of the counter to symbol periods is maintained.

보다 작을 때, 검출되며, 여기서 n은, 프로토콜 버전 필드가 판독되기 전에, 예를 들면, 3비트의 초기 심볼당 비트수이다. 또한, 보정 합의 피크치가 소정의 임계치보다 큰가의 여부가 체크된다(스텝 174). 만약, 상관 피크치가 상기 임계치보다 크다면, '캐리어 검출' 신호가 통보된다(스텝 176). 이어서, 임계치보다 크게 수신된 제로 델타, 즉 제로와 동등한 델타의 수를 카운트하는 기능을 하는 '하이 제로' 카운터가 증대한다(스텝 178). 일단, 최소 2개의 하이 제로가 수신되면(스텝 180), 수신기는 동기화를 고려한다. 이어서, 시간 베이스가 N_MAX의 값에 따라 보정된다(스텝 182). 일단, 수신기가 동기화되면, 상기 시프트 인덱스 값은 심볼 경계로부터 현재 카운터 값의 오프셋을 표시한다. 카운터는 각 심볼 의 적절한 프레이밍을 행하기 위하여 N_MAX 값을 사용하여 조정되는데, 즉, 카운터는 각 심볼의 스타트에서 카운팅을 개시한다. 이어서, 패킷의 나머지 수신이 순환적 수신 모드를 사용하여 지속된다(스텝 188).8 is a high level flowchart illustrating a method of preamble and synchronization reception in a fast embodiment of the present invention. First, all flags and counters are reset (step 160). Next, the linear mode of operation of the correlator is set (step 162). The received data bits are shifted into shift register # 2 until the maximum correlation is found (step 164). Once the maximum correlation peak is found, the receiver examines the adjacent maximum correlation peak. The zero counter is incremented when difference zero is detected (step 166) (step 172). The difference zero is when the absolute value of the difference between successive correlation peaks is less than half of the minimum delta shift, i.e.

When smaller, it is detected where n is the initial number of bits per symbol, for example, three bits before the protocol version field is read. In addition, it is checked whether the peak value of the correction sum is larger than the predetermined threshold (step 174). If the correlation peak value is larger than the threshold, a 'carrier detection' signal is notified (step 176). Subsequently, a 'high zero' counter, which functions to count the number of zero deltas received, i.e., deltas equal to zero, greater than the threshold is incremented (step 178). Once at least two high zeros are received (step 180), the receiver considers synchronization. Then, the time base is corrected according to the value of N _MAX (step 182). Once the receiver is synchronized, the shift index value indicates the offset of the current counter value from the symbol boundary. The counter is adjusted using the N _MAX value to perform proper framing of each symbol, ie the counter starts counting at the start of each symbol. Then, the remaining reception of the packet is continued using the cyclical reception mode (step 188).

Referring to step 166, if the continuous correlation peak is not within half of each other's minimum delta shift, the zero counter is cleared (step 170). In addition, the high zero counter is also cleared (step 168). The receiver then continues in the linear receive mode and finds the maximum correlation peak during the next UST period.

If the peak value is lower than the predetermined threshold (step 174), it is checked whether the zero counter value is greater than five (step 184). If the value of the counter is less than 5, the high zero counter is cleared (step 168) and the receiver continues to investigate the next maximum correlation peak. If the zero counter value is greater than 5, it indicates that a standard CEBus packet has been received, and the receiver switches to standard CEBus reception using the linear receive mode of this receiver.

보다 작을 때 검출되며, 여기서 n은 프로 토콜 버전 필드가 판독되기 전에, 예를 들면, 3비트의 초기 심볼당 비트수이다. 제로 카운터 값이 5보다 크지 않으면, 제어는 스텝 190으로 되돌아고, 수신기는 다음 최대 상관 피크를 조사한다(스텝 206). 제로 카운터의 값이 5보다 크면, 표준 CEBus 버스 패킷이 수신되고, 수신기는 표준 CEBus 수신을 행하기 위하여 선형 동작 모드로 스위치된다(스텝 208).9 is a high level flowchart illustrating a cyclic reception mode of a fast embodiment of the present invention. Cyclic reception mode is generally used to receive and synchronize the packet part. The first step is to find the correlation peak for each bit in UST that is 256 shifts in shift register # 2 108 (step 190). If the difference zero is detected (step 192), the zero counter increments by one (step 204). The difference zero is when the absolute value of the previous maximum correlation peak position subtracted from the current correlation peak position is less than one half of the minimum delta shift, ie

Is detected when smaller, where n is the initial number of bits per symbol, for example, three bits before the protocol version field is read. If the zero counter value is not greater than 5, control returns to step 190 and the receiver examines the next maximum correlation peak (step 206). If the value of the zero counter is greater than 5, a standard CEBus bus packet is received and the receiver is switched to linear mode of operation to perform standard CEBus reception (step 208).

If the absolute value of the difference between the two correlation peak values is not within one half of the minimum delta shift, the protocol version field of the packet is decoded (step 194). As described above, the start field of the packet includes four symbols with zero rotation shift. The receiver decodes the symbols into differential zeros. When detecting a nonzero delta shift, the start field of the protocol version is indicated, which is a single symbol of the nonzero shift.

Next, the packet length and the header error detection code HEDC are read (step 196). If the header error detection code is corrected (step 198), the rest of the packet is read (step 200). If the header error detection code is not corrected, the packet is ignored (step 210). If a complete packet is received, the end of the packet and the status of the CRC check are notified (step 202).

A high level flow chart illustrating the linear tracking correction method of the present invention is shown in FIG. As described above, tracking correction is performed by the linear mode tracking correction circuit 118 (Fig. 7). If the currently received shift index (indicated by N) is smaller than the predetermined threshold (step 220), the time value DELTA T is set, preferably 10% of the length of the chirp (step 222). The counter 116 (FIG. 7) which counts the modulo chirp length is corrected using the above DELTA T value (step 226). In particular, the upper limit of the counter is adjusted in accordance with ΔT. In addition, the last positive and negative maximum correlation shift positions are also corrected according to the DELTA T value (step 228). If the chirp length subtracted from the current shift index is equal to or greater than the predetermined threshold,? T is set to zero and the counter does not change (step 224).

Hereinafter, a second high reliability embodiment of the spread spectrum communication system of the present invention will be described in detail. The high reliability embodiment achieves a high level of reliability by connecting a plurality of single UST chirps to generate a single supercheap. For example, eight 100 microsecond UST periods may be connected to form a super UST period of 800 microseconds. At this time, differential code shift keying (DCSK) is applied to the supercombination in the same manner as for each individual symbol in the above-described fast embodiment.

In a high reliability embodiment, the data is transmitted in the form of a time shift between the supercombinations that are rotationally rotated. In the example presented here, each supercheap consists of eight standard CEBus, forming a supercheap 800 microseconds in length. Each individual chirp in the supercheap is cyclically shifted by a certain amount. The individual shift amount for each chirp in the superbook is fixed for all superbooks to be transferred. The shift amount or rotation amount of each chirp is selected so that the spurious peak of the superchief autocorrelation is relatively low. In addition, the shift of each individual chirp is selected such that the shift between successive chirps is sufficiently far from zero, such that the superopto start of a packet (SOP) for a packet transmitted using a standard CEBus packet or a fast embodiment of the present invention. It is not recognized as.                 

As with the fast embodiment, the number of bits transmitted in each supercombination determines the minimum number of shift indices required. An example of a shift index for a particular data sample is shown in FIG. 11. In this case, the superupe begins to be transmitted at the point of the arrow pointing downward. This transmission wraps around at the end of the waveform and returns to the point of the down arrow.

The packet structure of the communication system of the high reliability embodiment of the present invention is similar to that of the high speed embodiment shown in FIG. The packet structure of the high reliability embodiment includes a preamble, a packet start (SOP) field, a protocol version field, a packet length field, a header error correction code (HEDC), a differential code shift data field and a CRC field. The packet structure in the high reliability embodiment and the packet structure in the high speed embodiment are characterized by the fact that the start field of the packet of the high reliability embodiment has four supercombination symbols having a rotation shift of zero instead of four regular chirped symbols having zero shift. There is a difference in that. Four supercombination symbols are recognized by the receiver as three differential shifts of zero. If at least two or more of the last transmitted zeros are correctly detected, reception is possible. At this time, the receiver is synchronized with the received symbol stream. The remaining fields match the corresponding fields in the fast embodiment packet structure.

와 동등한 양만큼 신호를 지연시킨다. 값 f_c는 각 통과 대역의 복조 주파수를 표시한다. 지연 유닛의 출력은 Q 또는 쿼드러쳐 데이터 스트림을 형성하는 샘플링 레이트 f_s로 샘플링된다. 따라서, Q 샘플은 각 통과 대역 내의 복조 주파수의 90°도로 I 샘플에 대해서 지연된다. 3개 대역의 I 샘플은 샘플링 후에 정렬되지만, Q 샘플은 대역 의존 지연으로 인해 상기와 같지 않다.High reliability is achieved in the second embodiment by dividing the reception band into two or more equally sized sub-bands. In the example presented here, the receive band is divided into three equally sized sub-bands. For a chirped waveform spanning a frequency of 100 KHz to 400 KHz, there may be three bands, for example, 100 to 200 KHz, 200 to 300 KHz and 300 to 400 KHz. Thus, the receiver consists of three band pass input filters. The output of each bandpass filter is input to a 1-bit A / D converter that converts the output of each bandpass filter to a binary value. This 1-bit A / D converter includes a comparator and the next sampler clocked at the appropriate sampling frequency. Assuming a clock rate of 5.12 MHz, each band is sampled at a frequency of 320 KHz, forming an I or in-phase data stream. The output of the 1-bit A / D converter is also input to the delay circuit, which is

Delay the signal by an amount equal to. The value f _c indicates the demodulation frequency of each pass band. The output of the delay unit is sampled at a sampling rate f _s that forms a Q or quadrature data stream. Thus, the Q samples are delayed for the I samples at 90 ° of the demodulation frequency within each pass band. Three samples of I samples are aligned after sampling, but Q samples are not as above due to band dependent delay.

와 동일하다. 이어서, I 및 Q 데이터 스트림은 복소 템플릿을 사용하여 복소 상관되어 실제 및 가상 상관 합을 산출한다. 이어서, 상기 합들은 제곱되고 합산되어, 최대 상관 검출기에 입력된다. 3개의 통과 대역 모두로부터의 최대 상관 합이 결정되어, 상기 특정한 심볼에 수신기의 출력을 발생하기 위해 사용된다.The demodulation frequency f _c of each band is preferably a multiple of 1/2 of the sampling frequency f _s . Therefore, when the sampling frequency is 320 KHz, it is preferable that the center frequency is a multiple of 160 KHz. The demodulation frequency may be chosen to be a multiple of two or more FSs closest to the middle of a particular frequency band. In the example presented here, bands # 1 and f _c in the range of 100 to 200 KHz are selected to be 160K. Band # 2 is in the range from 200 to 300 KHz and f _c is selected to be 320 KHz. Band # 3 is in the 300-400 KHz range, and f _c is also selected as 320 KHz. The delay between each of the I and Q data streams causes a 90 ° shift in the particular carrier.

Is the same as The I and Q data streams are then complex correlated using the complex template to yield the actual and virtual correlation sums. The sums are then squared and summed and input to a maximum correlation detector. The maximum correlation sum from all three pass bands is determined and used to generate the receiver's output for that particular symbol.

A high level block diagram illustrating a high reliability transmitter of the present invention is shown in FIG. In general, the transmitter 30 is suitable for generating absolute transmission data as opposed to differential transmission data. If you want to send differential data, an increment step is required. Referring to FIG. 12, data is received from a host. The host generates and attaches a header and a CRC check sum in advance. Data is input to the initial index calculation unit 232. The data from the host forms a shift index in the supercomposition that is used to compute the index. The index is calculated in the same way as the transmitter of FIG. The length of the supercomposite is divided by the possible number of shifts of each supercombination symbol and then multiplied by the shift index. In the case where each superplot transmits 5 bits, the shift index may be configured with a value of 0 to 31. In addition, in the example presented here, the length of the superlap is taken as 2048 samples. Thus, the initial index consists of a number from 0 to 2047. This initial index is then input to the counter 234. The counter is an 11-bit modulo 2048 counter divided into two parts, 3 bits long and a section M bits long, where M is 8. The 3-bit portion corresponds to the length of 8 folds for creating a super tack symbol. The three high order bits are input to the index ROM 36, which serves to output an M bit value corresponding to the start point or initial shift index of each individual chirp in the superbook. The eight initial shift indices are selected in preference to all periods transmitted, and are selected to maximize the supercorrelation of the supercombination. The M bit output by the index ROM and the M SB (significant bit) from the counter 234 are added by the summer 237. Summer 237 adds the two values together with the modulus chirp length of each individual chirp making up the superchief, in this case 256. The output of the summer is input to the addressed chirp sample ROM 238 using the 8 bits output by the summer 237. The output of the chirp sample ROM is converted to analog by the D / A converter 240, filtered by the band pass filter (BPF) 241, and amplified by the output amplifier 242. The output of the amplifier forms a transmission output signal.

Superpatches are configured using 8 zips for compatibility with standard CEBus systems. However, there is one condition that the symbol length must be longer than that used in the fast embodiment. Thus, the super chirp can optionally be composed of a single chirp that spans the entire symbol length. The use of longer chirps results in higher reliability due to an increase in symbol length and thus more accurate correlation. In addition, higher reliability is achieved by using multiple pass bands of the receiver. Note that the receiver can be configured through the use of only one or a combination of these techniques to improve the reliability of the transmission.

13 is a high level diagram illustrating a transmitter of a high reliability embodiment of the present invention suitable for transmitting differential data or absolute data with separate non-data symbols. The transmitter of FIG. 13, which is generally referred to 250, is as shown in FIG. 12 except that a difference 252 and an integrator 262 are added.

The transmitter 250 shown in FIG. 13 transmits data using the absolute value transmission mode. In this mode, for example, 2 ⁿ symbols are sent directly without difference or integration. Each 5-bit symbol is used to directly determine the rotational shift index of each superplot in the UST. Thus, the receiver includes an integrator that functions to integrate the delta shifts generated by the differential data decoder. It is also possible to add transmit and receive modes. For example, the transmitter is used in differential mode, thereby integrating this data into the module's supercombination length before transmitting it. Thus, the receiver must differential the received data for proper reception. In this case, however, no integrator is necessary. In another example, the data is first differentiated from the modulo number of the shift index in the transmitter, encoded, and then integrated before being fed to the chirp sample ROM. Thus, the receiver first differentiates the data, decodes the output of the difference, and finally integrates the output of the decoder to form the output of the receiver.

This final example can be used to encode a separate symbol that is not in the data symbol set with a data symbol ( ^2N or some other number). In the 5-bit example presented here, the total number of symbols greater than 32 is to be transmitted, some of which are non-data symbols. To implement this, the chirp symbol time is divided into a plurality of shift indices greater than 32 to accommodate separate non-data symbols.

In order to transmit data using the differential transmission mode, an optional difference 72 is not necessary. The host supplies data that acts as a shift index to the initial index computation unit 260. The shift index in the chirp symbol is computed and input to an integrator 262 composed of a summer 264 and a delay unit 266. Summer 264 adds modulo 2 ⁿ , that is, modulo 32. The output of the summer is delayed and then added together with the output of the initial index computation unit 260. The output of the integrator is input to a counter 268 which functions similarly to the counter of the transmitter shown in FIG. The chirp sample ROM 274, D / A converter 276, band pass filter 277 and output amplifier 278 function similarly to the corresponding components in the transmitter shown in FIG.

When the transmitter and receiver pairs are used in differential mode, integrator 262 integrates the initial index data and supplies it to counter 268. In differential mode, the receiver only needs to differential the shift index output by the maximum correlation detector. If the symbol set consists of a number of symbols other than 2 ⁿ , then a difference 252 is needed. The data from the host is input to the delay unit 254 and then subtracted from the current data received from the host by the summer 256. The output from the summer is added to the data encode 258 by adding the modulo number of data symbols, i.e. 32. The data encoder maps 2 ⁿ data symbols to a particular shift index set. The data encoder is needed when the symbol encoding set includes non data symbols. For example, an encoding set may include 2 ⁿ data symbols along with separate non-data symbols used for various purposes.

The shift index is used to calculate the initial index input to integrator 262. The output of the integrator is delayed by delay unit 266 and added to the initial index by summer 264. This adder adds two quantitative modulo and superchirp lengths. Counter 268, index ROM 270, adder 272, chirp sample ROM 274, D / A converter 276, filter 277, and output amplifier are corresponding components in the transmitter shown in FIG. It works just like

A high level block diagram illustrating a receiver of a high reliability embodiment of the present invention is shown in FIGS. 14A, 14B and 14C. As mentioned above, the receiver is divided into three pass bands labeled band # 1, band # 2 and band # 3. The received signal includes a band pass filter (BPF) 282 that spans the frequency range of band # 1, a band pass filter 292 that spans the frequency range of band # 2, and a band that spans the frequency range of band # 3. Input to the pass filter 296. For the chirp pattern in the range of 100 to 400 KHz, band # 1 has a pass band of 100 to 200 KHz, band # 2 has a pass band of 200 to 300 KHz, and band # 3 has a pass band of 300 to 400 KHz.

Other embodiments may use different numbers of bands to increase reliability if the number of bands is two or more and at the same time increase reliability. If there are three bands, two of the bands may be damaged by noise and thus fail to receive, but the reception logic of the remaining bands may still output correct data. In addition, there is an advantage that the receiver is separated into three bands so that the receiver does not have any further phase distortion. The amount of distortion that each band can adjust is unchanged, but by increasing the amount of phase distortion in relation to all three bands working together, the receiver can adjust for better reception.

The output of band pass filter 282 for band # 1 is input to a 1-bit A / D converter 284. The output of band pass filter 292 for band # 2 is input to a 1-bit A / D converter 294. Similarly, the output of band pass filter 296 for # 3 is input to 1-bit A / D converter 298. Each output of the 1-bit A / D converter is input to the receiver auxiliary unit. In particular, each output of the 1-bit A / D converter is input to a receiving auxiliary unit, or receiver logic circuits 322, 324, 326 for each band # 1, band # 2, band # 3, respectively. Since the receiver logic circuits in the respective bands are composed of the same circuit section, only the reception logic circuit in the band # 1 is illustrated in FIG. 14A for convenience of description.

의 주기가 지연된 후에 샘플러(290)에 샘플링 주파수 f_s에서 샘플링된다. 샘플러의 출력은 90°쿼드러쳐 Q 비트 스트림을 형성한다. The operation of the receiver of FIGS. 14A, 14B and 14C is sampled at the sampling frequency f _s by the sampler 288 forming an I data stream. The output of the A / D converter 284 is also driven by the delay circuit 286.

The sampler 290 is sampled at the sampling frequency f _s after a period of. The output of the sampler forms a 90 ° quadrature Q bit stream.

The I and Q data streams are each input into separate sets of shift registers. The I bit stream or in-phase bit stream is input to one of two inputs of shift register # 1 300 and multiplexer 308. The output of multiplexer 308 is input to the serial input of shift register # 2 302. The serial output of shift register # 2 forms a second input to the multiplexer 308.

Similarly, a Q or out-of-phase bit stream is input to one of two inputs of shift register # 1 304 and multiplexer 310. The output of the multiplexer is input to the serial input of shift register # 2 306. The serial output of shift register # 2 is wrapped around to form a second input of multiplexer 310. The linear / cyclic control signal forms a select input to the multiplexers 308, 310. Both sets of shift registers for the I and Q channels operate similarly to the destinations shown in Figs. 7A and 7B.

Note that the size of the shift register in this embodiment is 256 bits long. Each shift register holds an equivalent value of one supercombination, or a concubine over a length of 8 UST. A 256 bit I value and a 256 bit Q value are input to the complex correlator 312 from the shift register # 2. This complex correlator functions to multiply the complex input I + jQ by the complex template M _i + jM _q to calculate the following relationship.

Complex Correlation Output = ( I + jQ) × ( M _i -jM _q )

= ( IM _i + QM _q ) + j ( -I M _q + Q M _i )

               = (Re) + j (Im)                 

Complex multiplication by the correlator results in the actual sum and the virtual sum being 9 bits wide, respectively. The actual correlation sum is then squared by the square function 314 and the virtual correlation sum is squared by the square function 316. The actual sum and square of the virtual sum are then added by the adder 318. The output of adder 318 forms the output of the receive logic circuit in band # 1. Similarly, the receive logic circuits in bands # 2 and # 3 produce the same output. Then, the output three correlation sums are summed by summer 320. The output of summer 320 is then input to maximum correlation detector 382.

The remainder of the receiver as shown in FIG. 14C is the same as the receiver described in connection with the fast embodiment of FIGS. 7A and 7B, except that the sum of the positive index and the positive correlator is used in the high reliability embodiment. It works. The index N _POS that calculates the maximum correlation value is input to the next quarter consisting of a summer 342, a delay unit 344, and a summer 346. The output of the differential shift index in the range of 0 to 255 is rounded by the rounding function 348 to the nearest shift value. The rounded shift value is then input to differential data decoder 350, which decodes the shift index value into a value within the original data sample range, in this case a number from 0 to 31. Since the output of the differential decoder is a differential data value, this output must be integrated before being output by the receiver. An integrator composed of summer 354 and delay unit 356 integrates the differential data values to calculate the received output data.

As with the receiver of the fast embodiment, the I and Q data values may be represented by a single bit, i.e., zero or one. In addition, the components of the complex templates M _i and M _q may be +1, -1 or 0. Multiplication with +1 or -1 is performed using the XOR function, and multiplication with 0 is performed by not connecting to a specific tap in the shift register. Multiplying to zero by removing the tabs in the manner described above not only improves performance, but also significantly saves hardware. This technique requires only about one third of the initial shift register tap to be added after it is connected.

The complex template of the complex correlator is computed by first passing the supercombination through each bandpass filter. Each output of the band pass filter is then sampled to generate an I and Q data stream. Each sample is then quantized to three levels of +1, -1, and 0. If the absolute value of the sample is below a certain threshold, it is quantized to zero. Otherwise, the sign is audited, the positive sign is coded as '1', and the negative sign is '0'. This same technique can be used to generate the template of the receiver shown in FIGS. 7A and 7B.

To further increase the resolution of the receiver, interpolation can be used. This can be accomplished by placing interpolation at the output of complex correlator 312 before the actual and virtual output correlation sums are squared. This interpolation can effectively double the sampling rate by generating an intermediate value. The interpolated value can be computed by adding up each successive pair of numbers and multiplying by a suitable constant such as 0.5. Multiplying 0.625 is useful for achieving interpolation in the form of sinx / x or sinc in the interpolation function. Thereafter, the output of the interpolator is squared and added.

Interpolation can be used to allow the use of low sampling rates. For example, if interpolation is used, the sampling rate can be reduced from 320KHz to 160KHz. Thus, the demodulation frequency f _c for each of the three bands can be changed to one-half multiple of the sampling rate, ie 80 KHz, which is a more desirable multiple. Thus, the intermediate frequency of band # 1 may be 160KHz, the intermediate frequency of band # 2 may be 240KHz, and the intermediate frequency of band # 3 may be 320KHz.

The receiver initiates operation in the preamble listening mode. The receiver computes the maximum absolute value of the complex correlation. In addition, the differential shift and correlation sum thresholds are also checked. If two consecutive shift zeros are detected, 'carrier detection' is notified. The sampling window is then synchronized and a cyclic correlator is used to decode the rest of the packet.

보다 작을 때, 검출되며, 여기서 n은, 프로토콜 버전 필드가 판독되기 전에, 예를 들면, 3비트의 초기 심볼당 비트수이다. 또한, 보정 합의 피크치가 소정의 임계치보다 큰가의 여부가 체크된다(스텝 374). 만약, 상관 합의 피크치가 상기 임계치보다 크다면, 제로 카운터의 값이 2 이상인 가의 여부가 체크된다(스텝 378). 만약, 제로 카운터 값이 2 이상이면, 선형 모드의 트래킹이 도 14c의 선형 모드 트래킹 보정 회로(336)를 사용하여 보정된다(스텝 380). 이 후, 패킷의 나머지 수신이 순환적 수신 모드를 사용하여 계속된다(스텝 382). 보정 합의 피크치가 임계치보다 크지 않다면, 제로 카운터의 값이 5보다 큰가의 여부가 판정된다(스텝 376). 그렇지 않다면, 제어는 스텝 360으로 진행하여, 처리를 시작한다. 만약, 제로 카운터가 5보다 크다면, 수신기는 더 이상의 제로가 수신되지 않을 때까지 수신을 계속한다(스텝 384). A high level flow chart illustrating a preamble and synchronization reception method of a high reliability embodiment of the present invention is shown in FIG. Ideally, all flags and counters are reset (step 360). Next, the linear mode of operation of the correlator is set (step 362). The received data bits are shifted into shift register # 2 until the maximum correlation is found at superposition, i.e., 8UST (step 364). Once the maximum correlation peak is found, the receiver examines the adjacent maximum correlation peak. If the difference zero is detected (step 368), the zero counter is incremented (step 372). The difference zero is when the absolute value of the difference between successive correlation peaks is less than half of the minimum delta shift, i.e.

When smaller, it is detected where n is the initial number of bits per symbol, for example, three bits before the protocol version field is read. In addition, it is checked whether the peak value of the correction sum is larger than the predetermined threshold (step 374). If the peak value of the correlation sum is greater than the threshold, it is checked whether the value of the zero counter is 2 or more (step 378). If the zero counter value is 2 or more, tracking in the linear mode is corrected using the linear mode tracking correction circuit 336 in Fig. 14C (step 380). Thereafter, the remaining reception of the packet is continued using the circular reception mode (step 382). If the peak value of the correction sum is not greater than the threshold, it is determined whether or not the value of the zero counter is greater than five (step 376). If not, control proceeds to step 360 to begin processing. If the zero counter is greater than five, the receiver continues to receive until no more zeros are received (step 384).

In step 368, if the difference between successive correlation peaks is 1/2 or more of the bit time, the zero counter is cleared (step 370), and control proceeds to step 360.

A high level flow diagram illustrating a cyclic mode reception method of a high reliability embodiment of the present invention used to receive the remainder of a packet is shown in FIG. In the first step, a correlation peak is found every 256 bits of each bit in the superposition, i.e., shift registers # 2 302, 306 (FIG. 14C) (step 390). If the difference zero is detected (step 392), the zero counter is incremented by one (step 394).

보다 작을 때 검출되며, 여기서 n은 프로토콜 버전 필드가 판독되기 전에, 예를 들면, 3비트의 초기 심볼당 비트수이다. 제로 카운터 값이 5보다 크지 않으면, 제어는 스텝 390으로 되돌아고, 수신기는 다음 최대 상관 피크를 조사한다(스텝 400). 제로 카운터의 값이 5보다 크면, 수신기는 더 이상의 제로가 수신되지 않을 때까지 대기하였다가, 제어를 스텝 390으로 되돌린다(스텝 402).The difference zero is when the absolute value of the previous maximum correlation peak subtracted from the current correlation peak position is less than half of the minimum delta shift, i.e.

Is detected when smaller, where n is the initial number of bits per symbol, for example, three bits before the protocol version field is read. If the zero counter value is not greater than 5, control returns to step 390 and the receiver examines the next maximum correlation peak (step 400). If the value of the zero counter is greater than 5, the receiver waits until no more zeros are received and returns control to step 390 (step 402).

If the absolute value of the difference between the two correlation peak values is not within half of the minimum delta time, the protocol version field of the packet is decoded (step 396). As discussed above, the SOP field of the packet preferably contains four identical symbols that are not rotated, with supershifts having a zero shift. The receiver decodes the symbols into differential zeros. The detection of a nonzero delta shift indicates the start field of the protocol version, since this protocol version field is a single symbol of nonzero shift. Once the protocol version is decoded, the responsiveness of the shift is set accordingly (step 398).

Next, the packet length and the header error detection code HEDC are read (step 404). If the header error detection code is corrected (step 406), the rest of the packet is read (step 408). If the header error detection code is not corrected, the packet is ignored (step 412). When the rest of the packet is read (step 408), the end of the packet and the status of the CRC check are notified (step 412).

While the invention has been described in terms of a limited number of embodiments, it is evident that many variations, applications, and other applications of the invention may be made.

It is used in spread spectrum communication systems using differential code shift keying to send and receive data.

Claims (54)

A method of communicating over a communication channel from a transmitter to a receiver, the method comprising: Both the transmitter and the receiver are connected to the communication channel, Generating, at the transmitter, a plurality of symbols consisting of a spread waveform in which each symbol is cyclically shifted by an amount according to the data to be carried by the symbol; Generating a transmission signal according to the plurality of symbols; Transmitting the transmission signal on the communication channel; Receiving the transmission signal from the communication channel at the receiver, generating a reception signal; Decoding the received signal by cyclically shifting the received signal at the receiver, the received signal correlating with a template corresponding to a spread waveform to generate a correlation sum during each cyclic shift, and Determining received data according to the shift corresponding to the maximum correlation sum Communication method comprising a. The method of claim 1, Wherein said spread waveform comprises a chirp waveform. The method of claim 1, The spreading waveform is a communication method consisting of a super chirp waveform consisting of a plurality of individual chirps. The method of claim 1, wherein the decoding step: Cyclically shifting each received symbol, During each cyclic shift of the received symbol, correlating the received symbol with a template corresponding to the spread waveform to generate a correlation sum; Generating a shift index corresponding to the maximum correlation sum, and Decoding the shift index to produce initially transmitted data. The method of claim 1, wherein the decoding step: Cyclically shifting each received symbol, During each cyclic shift of the received symbol, correlating the received symbol with a template corresponding to the spread waveform; Generating a first shift index and a second shift index respectively corresponding to the positive correlation sum and the negative correlation sum; Decoding the first shift index and the second shift index to produce a first data output and a second data output, respectively, and Outputting the first shift index or the second shift index based on the maximum of the positive correlation sum and the negative correlation sum. A spread spectrum communication system for communicating over a communication channel, A transmitter, coupled to the communication channel, for generating a plurality of symbols, each symbol configured using a spread waveform cyclically shifted by an amount in accordance with the data to be carried by the symbol, and A receiver coupled to the communication channel to decode the plurality of signals by receiving a signal from the communication channel and cyclically shifting the received signal; The received signal is correlated with a template corresponding to a spread waveform to generate a correlation sum during each cyclic shift, thereby determining received data according to the shift corresponding to the maximum correlation sum. Spread Spectrum Communication System. The method of claim 1, wherein the decoding step: Cyclically shifting each received symbol by a total amount equivalent to one symbol length, During each cyclic shift of the received symbol, correlating the received symbol with a template corresponding to the spread waveform; Generating a first shift index and a second shift index respectively corresponding to the positive correlation sum and the negative correlation sum; Decoding the first shift index and the second shift index to produce a first data output and a second data output, respectively, and Outputting the first shift index or the second shift index based on the maximum of the positive correlation sum and the negative correlation sum. delete delete A method of generating a signal for transmission over a communication channel from an input bit stream and using a spread waveform, the method comprising: Forming a serial stream of shift indices from the input bit stream; Determining an initial index according to each shift index in the serial stream of the shift index; Cyclically shifting the spread waveform according to the initial index, and Transmitting the cyclically shifted spread waveform on the communication channel How to include. A method for generating a spread spectrum signal for transmission over a communication channel from an input bit stream and using a spread waveform, the method comprising: Forming a shift index from the input bit stream; Determining an initial index according to the following equation,

Cyclically shifting the spread waveform according to the initial index, and Transmitting the cyclically shifted spreading waveform on the communication channel How to include. delete delete The method of claim 11, Differencing the input bit stream to produce a differential shift index. A transmitter for generating a signal to be transmitted over a communication channel from an input bit stream and using a spread waveform, Means for forming a shift index from each group of n bits in the input bit stream; Means for determining an initial index according to the shift index; Means for cyclically shifting the spread waveform in accordance with the initial index, and Means for transmitting the cyclically shifted spread waveform over the communication channel Transmitter comprising a. delete delete 16. The apparatus of claim 15, wherein the means for cyclically shifting the diffusion waveform is Counting means adapted to receive the initial index, and And look up table means for outputting sample positions of a spread waveform corresponding to the output of said counting means. The method of claim 15, And a differentiator for differentiating the input bit stream to produce a differential shift index. A receiver coupled to a communication channel to receive data encoded as a plurality of symbols in which each symbol is transmitted using a spread waveform, Signal splitting means for dividing a received input signal into one or more frequency bands, each outputting one or more band pass signals associated with a single frequency band; Sampling means for sampling the one or more band pass signals; Correlating means for correlating the output of the sampling means for each frequency band and generating one or more band correlation sums each corresponding to a different frequency band; Summing means for summing the one or more band correlation sums to produce a total correlation sum; Maximum correlation detecting means for determining a maximum correlation sum from the plurality of total correlation sums calculated during the time period, and Data decoding means for decoding the received symbols using the maximum correlation sum and generating an output thereof Receiver comprising a. delete delete delete The method of claim 20, And a differential, connected to an output of said maximum correlation detecting means, for generating a differential shift index corresponding to the time difference between two consecutive circularly rotated spread waveforms. delete delete delete delete The method of claim 20, The sampling means comprises means for generating both an I or in phase data stream and a Q or quadrature data stream, wherein the Q data stream is time delayed by a predetermined amount relative to the I data stream. delete delete delete The method of claim 20, Tracking means for maintaining and aligning the correlation means at symbol time. A method of receiving data encoded as a plurality of symbols and transmitted over a communication channel, the method comprising: Each symbol is transmitted using a spread waveform, Dividing the received input signal into a plurality of frequency bands to generate a plurality of band pass signals, each associated with a single frequency band; Sampling the plurality of band pass signals to produce a sample stream; Correlating the sample stream associated with each frequency band to generate a plurality of band correlation sums; Summing a plurality of band correlation sums respectively to generate a plurality of correlation sums; Determining a maximum correlation sum from the plurality of correlation sums, and Decoding the shift index for each received symbol using the maximum correlation sum and generating an output thereof Data receiving method comprising a. delete delete delete The method of claim 34, wherein Calculating the differential shift index corresponding to the time difference between two consecutive circularly rotated spread waveforms by differentiating the shift index. delete The method of claim 34, wherein The dividing step includes band-pass filtering each frequency band by a bandwidth and a center frequency according to each frequency band. delete delete The method of claim 34, wherein The sampling step includes generating both an I or in-phase data stream and a Q or quadrature data stream, wherein the Q data stream is time delayed with respect to the I data stream by a predetermined amount. The method of claim 34, wherein And wherein said correlating step comprises applying a complex correlation to said sample stream. The method of claim 44, And said applying said complex correlation comprises applying a nonlinear function to the result of said complex correlation. The method of claim 45, The nonlinear function includes a square function. The method of claim 34, wherein Maintaining and sorting the correlation at symbol time. A spread spectrum communication system for communicating over a communication channel connected to both a transmitter and a receiver, the method of synchronizing the receiver, comprising: Transmitting a plurality of spreading waveforms having zero differential shifts with respect to each other on the communication channel; Receiving the plurality of spread waveforms from the communication channel to generate a received signal, and Deciding synchronization when decoding the received signal and receiving at least a predetermined number of spreading waveforms having zero differential shifts from each other; Receiver synchronization method comprising a. delete delete delete A method of communicating over a communication channel from a transmitter to a receiver, the method comprising: Both the transmitter and the receiver are connected to the communication channel, Generating, at the transmitter, a plurality of symbols consisting of a spread waveform in which each symbol is cyclically shifted by an amount according to the data to be carried by the symbol; Generating a transmission signal in accordance with the plurality of symbols for transmission over the communication channel; Receiving the transmission signal from the communication channel at the receiver, generating a reception signal; Decoding the received signal at the receiver by correlating the received signal with a template corresponding to a spread waveform to generate a differential shift index indicating a time shift between successive cyclic shifts of the spread waveform Communication method comprising a. A method of receiving data encoded as a plurality of symbols and transmitted over a communication channel, the method comprising: Each symbol consists of a spread waveform that is cyclically rotated by an amount according to data to be transmitted for a particular symbol time, Dividing the received input signal into a plurality of frequency bands, generating a plurality of band pass signals, each associated with a single frequency band; Sampling the plurality of band pass signals to produce a sample stream; Circularly rotating the sample stream in each frequency band; Correlating the cyclically rotated sample stream for each frequency band using a template corresponding to the spread waveform, generating a band correlation sum during each cyclic rotation, and calculating a plurality of band correlation sums for each symbol; , Summing the plurality of band correlation sums for each frequency band to generate a plurality of correlation sums; Determining a maximum correlation sum from the plurality of correlation sums, and Decoding the shift index associated with the maximum correlation sum and generating an output thereof Data receiving method comprising a. A receiver coupled to a communication channel to receive data encoded as a plurality of symbols, the receiver comprising: Each symbol consists of a spread waveform that is cyclically rotated by an amount according to data to be transmitted for a particular symbol time, Signal splitting means for dividing a received input signal into a plurality of frequency bands, each outputting a plurality of band pass signals associated with a single frequency band; A plurality of sampling means for sampling the plurality of band pass signals; A plurality of shift means each of which rotates the output of each sampling means associated with each frequency band, each having a plurality of taps, Each connected to an output of one of the shift means, each generating a correlation sum during each cyclic shift of the shift means using a template corresponding to the spread waveform, each of which is a plurality of for each received symbol A plurality of correlation means for generating band correlation sums of Summing means for respectively summing a plurality of band correlation sums output by each correlation means to generate a plurality of correlation sums; Maximum correlation detecting means for determining a maximum correlation sum from the plurality of correlation sums, and A data decoder that decodes the shift index associated with the maximum correlation sum and generates an output thereof Receiver comprising a.

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