KR100647644B1 - Plasma display panel - Google Patents

Abstract

 A plasma display panel capable of reducing capacitance of a non-display area is disclosed. The disclosed plasma display panel includes a front substrate including a display area for displaying an image and a non-display area formed at a periphery of the display area and not displaying an image, across the display area and the non-display area of the front substrate. A plurality of X electrodes to be formed, a plurality of Y electrodes formed on the front substrate, the plurality of Y electrodes extending in parallel with a predetermined distance from the X electrode, and formed on the non-display area, and connecting the plurality of X electrodes in common; The common electrode pattern includes a common electrode pattern, and the common electrode pattern includes at least one window. A dielectric layer is further formed on the front substrate on which the X electrode and the Y electrode are formed, and the dielectric layer of the non-display area has a thickness smaller than that of the dielectric layer of the display area. As such, by providing at least one window in the common electrode pattern and relatively reducing the thickness of the dielectric layer of the non-display area, the capacitance of the non-display area can be reduced, thereby reducing power consumption of the plasma display panel. Can be.

X electrode, common electrode, common electrode pattern, window

Description

Plasma display panel {Plasma display panel}

1 is a plan view of a typical plasma display panel.

2 is a plan view of a plasma display panel according to an exemplary embodiment of the present invention.

3 is an exploded perspective view of the plasma display panel of FIG. 2.

4 is a plan view of the front substrate of FIG. 2.

FIG. 5 is a cross-sectional view taken along the line VV ′ of FIG. 2.

<Explanation of symbols for main parts of the drawings>

111: front substrate 133: X electrode

136: Y electrode 190: common electrode pattern

190a: Windows 115, 115a, 115b: dielectric layer

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of reducing the capacitance of a non-display area.

In recent years, a plasma display panel, which is attracting attention as a replacement of a conventional cathode ray tube display device, is configured by discharging a discharge gas between two substrates on which a plurality of electrodes are formed. When a predetermined discharge voltage is applied to these electrodes, ultraviolet rays are generated in the discharge space, and phosphors formed in a predetermined pattern by the ultraviolet rays are excited to obtain a desired image. The plasma display panel includes a front substrate including an X electrode and a Y electrode causing a discharge, and a back substrate including an address electrode facing the front substrate and selecting a discharge cell, wherein the front substrate of the plasma display panel is illustrated. 1 is shown.

Referring to FIG. 1, the front substrate 10 includes a display area A in which an image is displayed by plasma discharge, and a non-display area B positioned outside the display area A and in which no image is displayed. . The front substrate 10 and the rear substrate (not shown) on the upper surface of the front substrate 10 where the display area A and the non-display area B are defined, i.e., opposite the rear substrate (not shown). The X electrode 20 and the Y electrode 30 for discharging the discharge gas filled in between are arrange | positioned. The X electrode 20 and the Y electrode 30 extend parallel to each other in the x-axis direction of the drawing while being spaced apart by a predetermined interval.

The conventional X electrodes 20 are commonly bundled by the common electrode pattern 40 in order to improve current driving characteristics and discharge characteristics. The common electrode pattern 40 is disposed in one side non-display area B of the front substrate 10, and the common electrode pattern 40 drives a plasma display panel through a connection cable (not shown). (Not shown). On the other hand, the Y electrodes 30 are not individually tied to each other and are individually disposed and connected to the driving circuit board (not shown) by a connection cable (not shown).

However, the common electrode pattern 40 of the X electrode is formed of a conductive material and occupies a predetermined area as shown in FIG. 1, and a dielectric layer is formed on the surfaces of the common electrode pattern 40 and the X electrode 20. As not shown, the capacitance (parasitic capacitance) of the portion where the common electrode pattern 40 is formed, that is, the non-display area, becomes large. Such capacitance may cause a large amount of heat in the plasma display panel, and moreover, the plasma display apparatus, thereby increasing driving voltage and power consumption.

Accordingly, an object of the present invention is to provide a plasma display panel which can reduce capacitance of a non-display area.

In order to achieve the above object of the present invention, the present invention provides a front substrate including a display area for displaying an image and a non-display area formed at a periphery of the display area and not displaying an image, a display area of the front substrate, and A plurality of X electrodes formed across the non-display area, a plurality of Y electrodes formed on the front substrate, the plurality of Y electrodes extending parallel to the X electrode at a predetermined distance, and formed on the non-display area, A common electrode pattern may be commonly connected to the X electrode, and the common electrode pattern may include at least one window.

A dielectric layer is further formed on the front substrate on which the X electrode and the Y electrode are formed, and the dielectric layer of the non-display area has a thickness smaller than that of the dielectric layer of the display area.

The dielectric layer of the display area is composed of a first dielectric layer and a second dielectric layer, and the dielectric layer of the non-display area is composed of a first dielectric layer.

The bus electrode of claim 1, wherein the X electrode and the Y electrode have a transparent electrode extending on the front substrate with a first width and a second width formed on the transparent electrode and smaller than the first width. It consists of. The bus electrode may be a metal material.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a plan view of a plasma display panel according to an embodiment of the present invention, and FIG. 3 is an exploded perspective view of the plasma display panel of FIG. 2. 4 is a plan view of the front substrate of FIG. 2. FIG. 5 is a cross-sectional view taken along the line VV ′ of FIG. 2.

First, referring to FIG. 2, the plasma display panel 100 includes a top plate 150 and a bottom plate 160 coupled in parallel thereto. The display area D is defined in the center area where the upper plate 150 and the lower plate 160 overlap, and the image is displayed by the plasma discharge in the display area D. FIG. Meanwhile, other portions of the upper plate 150 and the lower plate 160 except for the display area D are divided into non-display areas N, which are located at the outer side of the display area D. FIG. The image is no longer displayed. A portion of the non-display area N where the upper plate 150 and the lower plate 160 overlap with each other is formed with a sealing member 190 such as a frit so as to surround the display area D, thereby forming the upper plate 150 and the lower plate. Bonding and sealing between the 160.

In the non-display area N, terminals of the electrodes formed on the upper and lower plates 150 and 160 are generally disposed at portions where the upper and lower plates 150 and 160 do not overlap. That is, the terminal portions (not shown) of the X electrodes 133 and the Y electrodes 136 are disposed on the left and right edge portions Na and Nb of the upper plate 150, respectively, and the upper and lower edge portions of the lower plate 160 are disposed. Terminals Nc and Nd of the address electrodes 122 are disposed. These terminal parts are electrically connected to a driving circuit board (not shown) for driving the plasma display panel by a connection cable (not shown) such as a flexible printed circuit board (FPCB).

The arrangement of the upper plate 150, the lower plate 160 and the electrodes will be described in more detail with reference to FIG. 3.

The front substrate 111 constituting the upper plate 150 and the rear substrate 121 constituting the lower plate 160 are spaced apart at regular intervals so as to provide a discharge space. In particular, the upper portion of the rear substrate 121 may include a discharge cell ( The partition wall 130 is formed to define 170. The partition 130 functions to prevent optical crosstalk between the discharge cells 170. In addition, a plurality of address electrodes 122 are arranged side by side at a predetermined interval on the rear substrate 121, and the address electrodes 122 are formed so as to be disposed for each discharge cell 170.

Meanwhile, a plurality of X electrodes 133 and Y electrodes 136 are disposed on opposite surfaces of the front substrate 111. The X electrodes 133 and the Y electrodes 136 are spaced apart at predetermined intervals and arranged in parallel, and are disposed at the same level from the front substrate 111. Each of the X electrode 133 and the Y electrode 136 includes transparent electrodes 131 and 134 and bus electrodes 132 and 135. The transparent electrodes 131 and 134 are formed of a transparent material that is a conductor capable of causing a discharge and does not prevent the light emitted from the phosphor 126 from traveling to the front substrate 111. And indium tin oxide (ITO). However, since transparent conductors such as ITO generally have a very high resistance, when the X electrode 133 and the Y electrode 136 are formed only by the transparent electrodes 131 and 134, the voltage drop in the longitudinal direction increases, thereby driving power. This consumes a lot and can slow down the response. In order to improve this, bus electrodes 132 and 135 having excellent electrical conductivity and a relatively narrow width than the transparent electrodes 131 and 134 are disposed on the transparent electrodes 131 and 134. The X electrode 133 and the Y electrode 136 composed of the transparent electrodes 131 and 134 and the bus electrodes 132 and 135 extend across the display area D to the non-display area Na or Nb.

As shown in FIG. 4, the X electrode 133 and the Y electrode 136 extend in parallel in the horizontal direction (x-axis direction) of the front substrate 111. In particular, in order to electrically connect with the driving circuit board, the plurality of X electrodes 133 extend further toward, for example, the non-display area Na on the left side, and the plurality of Y electrodes 136, for example, the non-display area on the right side. Extends further toward (Nb).

Meanwhile, the X electrodes 133 are commonly bundled by the conductive common electrode pattern 190 in the non-display area Na in order to improve current driving capability and discharge capability. Since the common electrode pattern 190 occupies a certain area, as described in the related art, the capacitance of the non-display area can be increased. Accordingly, in this embodiment, at least one window 190a is formed in the common electrode pattern 190 to reduce the capacitance of the common electrode pattern 190. As the window 190a is formed in the common electrode pattern 190, the area occupied by the common electrode pattern 190 may be reduced by the area of the window 190a, thereby reducing the capacitance of the non-display area Na.

In addition, the dielectric layer 115 may be formed on the front substrate 111 on which the X electrode 133 and the Y electrode 136 are formed. The dielectric layer 115 is generally formed by the first and second printing methods. 2 dielectric layers 115a and 115b. In this embodiment, in order to reduce the capacitance of the non-display area Na that is formed of the common electrode pattern 190, as shown in FIG. 5, the thickness of the dielectric layer 115 of the non-display area Na is displayed in the display area ( It is formed relatively thinner than the thickness of the dielectric layer 115 of D). Preferably, the first and second dielectric layers 115a and 115b are formed on the front substrate 111 corresponding to the display area D, and the first and second dielectric layers 115a and 115b are formed on the front substrate 111 corresponding to the non-display area Na. Only one dielectric layer 115a is formed. As described above, the capacitance of the non-display area Na can be further reduced by forming a relatively thin thickness of the dielectric layer 115 formed in the non-display area Na where the common electrode pattern 190 is formed. In FIGS. 3 and 5, reference numeral 125 denotes a dielectric layer formed on the rear substrate 121, 116 denotes a protective layer covered on the dielectric layer 115, and 200 denotes an upper plate (or a front substrate) and a lower plate. The spacing member which maintains the distance between (or back substrate) is shown.

As the plasma display panel of the present invention forms a plurality of windows in the common electrode pattern 190 that commonly connects the X electrodes 133, the area occupied by the common electrode pattern 190 is the area of the window 190a. Is reduced by. Accordingly, the occupation of the common electrode pattern 190 is based on the capacitance formula (C = εA / d, ε: dielectric constant of dielectric, A: area of conductor (i.e., common electrode pattern), d: thickness of dielectric). Since the area is relatively reduced, capacitance due to the common electrode pattern 190 may be reduced. In addition, the thickness of the dielectric overlapping the common electrode pattern 190 is also relatively reduced, thereby further reducing the capacitance of the non-display area.

As described above in detail, according to the present invention, at least one window is formed in a common electrode pattern formed on the front substrate and commonly connects a plurality of X electrodes, and the thickness of the dielectric layer of the non-display area in which the common electrode pattern is formed. Relatively reduce Accordingly, capacitance generated by the formation of the common electrode pattern can be reduced, and power consumption of the plasma display device can be lowered.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (5)

A plurality of X electrodes and a plurality of X electrodes including a display area for displaying an image and a non-display area formed at a periphery of the display area and not displaying an image, and disposed across the display area and the non-display area on one surface thereof; A front substrate including Y electrodes spaced a predetermined distance apart; A rear substrate disposed to face one surface of the front substrate and provided with a discharge space; A common electrode pattern including at least one opening disposed on the non-display area of the front substrate to commonly connect the plurality of X electrodes; A spacing member disposed at an edge of the non-display area to maintain a spacing between the front substrate and the back substrate; And A dielectric layer formed in the display area and the non-display area of the front substrate on which the X electrode and the Y electrode are formed; And a thickness of the dielectric layer corresponding to the non-display area from the outside of the display area to the spacer is smaller than the thickness of the dielectric layer formed on the display area. delete The method of claim 1, wherein the dielectric layer, A first dielectric layer formed on the display area and the non-display area; And And a second dielectric layer formed over the first dielectric layer on the display area. The method of claim 1, wherein the X electrode and the Y electrode, A transparent electrode extending on the front substrate and having a first width; And a bus electrode formed on the transparent electrode and having a second width smaller than the first width. The plasma display panel of claim 4, wherein the bus electrode is made of a metal material.

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