KR100647589B1 - Plasma dispaly panel having a different electrode structure and the fabrication method thereof - Google Patents

Abstract

Disclosed are a plasma display panel having different electrode structures and a method of manufacturing the same. According to the present invention, a plurality of substrates are disposed to face each other; a display layer configured to display an image on the substrate; an electrode having a double layer structure; and a non-display region partitioned outward from the display region. And a dummy electrode formed of a single layer of white single layer having excellent conductivity in the non-display area, thereby improving conductivity of the dummy electrode, thereby improving the ability of removing wall charges accumulated in the panel.

Description

Plasma display panel having a different electrode structure and manufacturing method thereof

1 is a cross-sectional view showing a cross-sectional structure of a unit cell of a conventional plasma display panel;

2 is an exploded perspective view illustrating a part of a conventional plasma display panel cut out;

3 is a schematic diagram illustrating a display area and a non-display area of FIG. 2;

4 is a cross-sectional view illustrating a state in which the bus electrode and the dummy bus electrode of FIG. 3 are formed;

FIG. 5 is an exploded perspective view of a plasma display panel partially cut out according to an embodiment of the present invention; FIG.

6 is a schematic diagram illustrating a display area and a non-display area of FIG. 5;

FIG. 7 is a perspective view illustrating a state in which the bus electrode and the dummy bus electrode of FIG. 5 are partially removed;

8A to 8F are cross-sectional views sequentially illustrating a process of forming a bus electrode and a dummy bus electrode according to an embodiment of the present invention.

8A is a diagram illustrating a state in which a paste for a first bus electrode is printed on a substrate;

8B is a cross-sectional view illustrating a state in which the first bus electrode paste of FIG. 8A is dried;

8C is a cross-sectional view illustrating a state in which a paste for a second bus and a dummy bus electrode is printed on the first bus electrode paste of FIG. 8B;

8D is a cross-sectional view illustrating a state in which the paste for the second bus and dummy bus electrodes of FIG. 8C is dried;

8E is a cross-sectional view illustrating a state in which the electrode of FIG. 8D is exposed;

8F is a cross-sectional view illustrating a state in which the electrode of FIG. 8E is developed to complete a bus electrode and a dummy bus electrode.

<Brief description of symbols for the main parts of the drawings>

50 ... plasma display panel 51 ... front board

52 bus electrode 52 a ... first bus electrode

52b ... second bus electrode 53 ... common electrode

54 ... scanning electrode 55 ... holding electrode

56.Front dielectric layer 57.Protective layer

59.Dummy bus electrode 510 ... Backplane

520 Address electrode 530 Backside dielectric layer

540 ... Bulk

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel and a method of manufacturing the same in which structures of electrodes in a display area and a non-display area are different from each other.

Typically, a plasma display panel injects and discharges a discharge gas on two substrates having a plurality of electrodes, and then applies a discharge voltage. When the gas emits light between the electrodes due to the discharge voltage, an appropriate pulse voltage is applied. It refers to a flat panel display that is applied to address a point where two electrodes intersect to implement a desired number, letter or graphic.

The plasma display panel may be classified into a direct current type and an alternating current type according to a type of driving voltage applied to a discharge cell, for example, a discharge type, and may be classified into a counter discharge type and a surface discharge type according to the configuration of the electrodes.

The DC plasma display panel has a structure in which all electrodes are exposed to a discharge space, and charges are directly transferred between corresponding electrodes. On the other hand, in the AC plasma display panel, at least one electrode is embedded in the dielectric layer, and instead of direct charge transfer between the corresponding electrodes, the ions and electrons generated by the discharge adhere to the surface of the dielectric layer to form a wall. It is possible to form a wall voltage and to maintain discharge by a sustaining voltage.

On the other hand, in the opposite discharge type plasma display panel, an address electrode and a scan electrode are provided to face each unit pixel, and addressing discharge and sustain discharge are generated between the two electrodes. On the other hand, in the surface discharge plasma display panel, an address electrode and a sustain electrode corresponding to each unit pixel are provided to generate addressing discharge and sustain discharge.

Referring to FIG. 1, in the conventional plasma display panel 10, a pair of sustain electrodes 12 having a predetermined width and height are formed on the same surface of the front substrate 11, and the sustain electrodes 12 It is embedded by the front dielectric layer 13. The passivation layer 14 is coated on the front dielectric layer 13.

An address electrode 16 having a predetermined width and height is formed on the back substrate 15 disposed to face the front substrate 11, and the address electrode 16 is embedded by the back dielectric layer 17. . The barrier ribs 18 are formed on the rear dielectric layer 17 to prevent cross talk between adjacent discharge cells. The barrier ribs 18 are formed on the upper surface of the rear dielectric layer 17 and the inner walls of the barrier ribs 18. The green and blue phosphor layers 19 are formed.

Meanwhile, an inert gas is sealed in the combined inner space of the front and rear substrates 11 and 15 to have a discharge region 100.

The operation of the plasma display panel 10 having the above structure will be briefly described as follows.

When a driving voltage is applied to the sustain electrode 12, surface discharge occurs in the discharge region on the front surface of the front dielectric layer 13 and the passivation layer 14 to generate ultraviolet rays. Colorization is indicated as the fluorescent material of the surrounding phosphor layer 19 is excited by the generated ultraviolet rays.

That is, space charges in the discharge cell are accelerated by the driving voltage applied thereto, and are mainly composed of neon (Ne), an inert mixed gas filled with a pressure of about 400 to 500 Torr in the discharge cell. It collides with the phening mixed gas to which helium (He) and xenon (Xe) gas are added.

Accordingly, 147 nanometers of ultraviolet rays are generated while the inert gas is excited. The generated ultraviolet rays generate visible light as they collide with the fluorescent material of the phosphor layer 19 surrounding the address electrode 16 and the partition wall 18.

2 illustrates a conventional plasma display panel 20.

Referring to the drawings, the plasma display panel 20 includes a front substrate 21 and a back substrate 210.

On the lower surface of the front substrate 21, sustain electrodes 24 made up of common and scan electrodes 22 and 23 in a strip form are formed, and along one edge of the common and scan electrodes 22 and 23, respectively. The bus electrode 25 is formed. The sustain and bus electrodes 24 and 25 are embedded by the front dielectric layer 26, and a protective film layer 27 is coated on the front dielectric layer 26.

An address electrode 220 is formed on the top surface of the rear substrate 210 so as to be orthogonal to the sustain electrode 24, and the address electrode 220 is buried by the rear dielectric layer 230. On the upper surface of the rear dielectric layer 230, a partition wall 240 for partitioning a discharge space is disposed between the address electrodes 220. Red, green, and blue phosphor layers 250 are coated on the inner wall of the partition wall 240 and the surface of the rear dielectric layer 230.

As shown in FIG. 3, the plasma display panel 20 is formed at both ends of the display area A and a display area A for actually displaying an image by forming pixels. It can be divided into a non-display area (B) (C) connected to an external terminal to transmit an electrical signal.

Bus electrodes 22 are formed in the display area A on the front substrate 21 at predetermined intervals, and dummy bus electrodes 32 are formed in the non-display areas B and C, respectively. In this case, although not shown, the sustain electrode 24 is formed on the front substrate 21.

4 is a cross-sectional view of FIG. 3 taken along the line I-I.

Referring to the drawing, a bus electrode 22 having a double layer structure in the display area A is patterned on the substrate 21.

That is, the first bus electrode 22a is formed on the upper surface of the substrate 21. The first bus electrode 22a is formed of a black layer to serve as a light shielding film.

The second bus electrode 22b is formed on the upper surface of the first bus electrode 22a. The second bus electrode 22b is made of a white layer having good conductivity.

The dummy bus electrode 32 is also patterned in a double layer in the non-display areas B and C. As shown in FIG.

That is, the first dummy bus electrode 32a made of the black layer substantially the same as the first and second bus electrodes 22a constituting the bus electrode 22, and the second dummy bus electrode 32b made of the white layer. )

In this case, the dummy bus electrode 32 is an electrode for preventing breakdown of the dielectric layer due to wall charge accumulation in the plasma display panel 20 of FIG. 2. When the wall charges are excessively accumulated inside the panel, the dielectric layer is destroyed. When the dummy bus electrodes 32 are formed in the non-display areas B and C, the wall charges are accumulated toward the dummy bus electrodes 32. It escapes and prevents dielectric breakdown of the dielectric layer due to wall charge accumulation.

There are two kinds of such dummy bus electrodes 32. One is a ground type dummy electrode which grounds the dummy bus electrode 32 to allow the accumulated wall charges to escape, and applies the voltage to push out the accumulated wall charges. There may be a voltage applied dummy electrode to remove.

The wall charge accumulation capability and the wall charge removal capability of the dummy bus electrode 32 depend on the conductivity of the dummy bus electrode.

In other words, when the conductivity of the dummy bus electrode 32 is good, the wall charge accumulation ability is increased, the wall charge removal ability is improved, and the dielectric layer insulation breakdown due to the wall charge accumulation inside the panel is further reduced.

On the other hand, when the conductivity of the dummy bus electrode 32 is poor, the wall charge accumulation capacity is lowered and the wall charge removal capacity is also lowered, resulting in more severe dielectric breakdown of the dielectric layer.

Therefore, the conductivity of the dummy bus electrode 32 should be good so that the wall charge accumulated in the panel from the dummy bus electrode 32 escapes well toward the dummy bus electrode.

However, the conventional plasma display panel 20 has the following problems.

In the case of the bus electrode 22 formed in the display area A, a first bus electrode 22a made of a black layer which serves as a light shielding film is necessary in order to improve contrast.

On the other hand, in the case of the dummy bus electrode 32 in the non-display area (B) (C), the conductivity of the dummy bus electrode 32 itself is reduced due to the low conductivity of the first dummy bus electrode 32a formed of a black layer. There is a problem in that it becomes poor and degrades the ability to remove the wall charges accumulated in the panel.

On the other hand, the manufacturing cost increases due to the formation of the unnecessary black first dummy bus electrode 32a.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and includes a plasma display panel having a different electrode structure capable of preventing dielectric breakdown of a dielectric layer by different electrode structures in a display area and a non-display area on a substrate, and a manufacturing method thereof The purpose is to provide.

In order to achieve the above object, the plasma display panel having different electrode structures according to an aspect of the present invention,

A plurality of substrates facing each other;

An electrode having a double layer structure on a display area for displaying an image on the substrate;

And a dummy electrode disposed in a non-display area partitioned outward from the display area and having a single layer structure.

The electrode may include a first electrode of black color formed on the upper surface of the substrate and a second electrode of white color formed on the first electrode.

Further, the electrode of one of the electrodes of the double layer and the dummy electrode is characterized in that the material is substantially the same.

According to another aspect of the present invention, a plasma display panel having different electrode structures is provided.

Front substrate;

A storage electrode formed on a lower surface of the front substrate;

A bus electrode having a double layer structure electrically connected to the sustain electrode and disposed in a display area for displaying an image;

A dummy bus electrode having a single layer structure disposed in a non-display area partitioned outward from the display area;

A front dielectric layer filling the sustain electrode, the bus electrode, and the dummy bus electrode;

A rear substrate disposed to face the front substrate;

An address electrode formed on an upper surface of the rear substrate;

Barrier ribs formed between the front and rear substrates; And

And red, green, and blue phosphor layers coated in the discharge space partitioned by the partition wall.

According to another aspect of the present invention, a method of manufacturing a plasma display panel having different electrode structures is provided.

Preparing a substrate;

Completely printing a paste for a first bus electrode formed in a display area for displaying an image on the substrate;

Drying the first bus electrode paste;

Simultaneously printing the second bus electrode paste on the upper surface of the first bus electrode paste and the dummy bus electrode paste on the non-display area partitioned outward from the display area;

Drying the printed second bus electrode paste and the dummy bus electrode paste; And

Exposing, developing, and firing the dried second bus electrode paste, the dummy bus electrode paste, and completing a bus electrode having a double layer structure, and a dummy bus electrode having a single layer structure. do.

In addition, the second bus electrode paste and the dummy electrode paste may be entirely printed on the same material.

Hereinafter, a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 illustrates a plasma display panel 50 according to an embodiment of the present invention.

Referring to the drawings, the plasma display panel 50 is provided with a front substrate 51 and a rear substrate 510 disposed to face the front substrate 51.

The bus electrodes 52 are disposed on the bottom surface of the front substrate 51 to be spaced apart from each other by a predetermined interval. The bus electrode 52 is formed in a strip shape. The common electrode 53 of predetermined size and the sustain electrode 55 which consists of the scanning electrode 54 protrude in the direction which opposes from each inner side wall of the pair of bus electrodes 52. In addition, a dummy bus electrode 59 is formed at the outermost side of the bus electrode 52.

The sustain electrode 55 is disposed to be spaced apart by a predetermined interval along the inner wall of the bus electrode 52 in a longitudinal direction, and the common electrode 53 and the region where the scan electrode 54 are formed are discharged in one discharge. Forming a cell. In addition, the region between the pair of bus electrodes 52 in which the common and scan electrodes 53 and 54 constituting the discharge cell are disposed corresponds to the non-discharge region. Although not shown in the non-discharge area, a black mattress layer may be formed.

The front dielectric layer 56 is formed on the front substrate 51 on which the bus electrode 52, the dummy bus electrode 59, and the sustain electrode 55 are formed. On the surface of the front dielectric layer 56, a protective film layer 57 such as a magnesium oxide film is coated on the entire surface.

On the other hand, the address electrode 520 is formed on the upper surface of the back substrate 510 to be spaced apart by a predetermined interval. The address electrode 520 is disposed in a direction orthogonal to the direction in which the bus electrode 52 is formed. The address electrode 520 is located in a discharge cell in a portion where the common and scan electrodes 53 and 54 face each other.

A back dielectric layer 530 is formed on the upper surface of the address electrode 520 to fill it.

A partition wall 540 is formed on an upper surface of the rear dielectric layer 530 to partition a discharge space and prevent cross talk. The partition wall 540 is a first partition wall 550 formed in a direction parallel to the bus electrode 52, and a second partition wall 560 orthogonal to the bus electrode 52 and formed in a direction parallel to the address electrode 520. It includes. The second partition 560 extends from both sidewalls of the first partition 550 and is integrally connected to the second partition 560 to form a lattice. Alternatively, the partition wall 540 is not limited to this shape as long as it partitions a discharge space such as a meander type or a strip type.

Red, green, and blue phosphor layers 570 are formed on the inner side walls of the barrier ribs 540 and the top surface of the back dielectric layer 530 for each discharge cell.

According to a feature of the present invention, the bus electrode 52 has a double layer structure on the substrate 51, and the dummy bus electrode 59 has a single layer structure.

More detailed description is as follows.

Here, the same reference numerals as in the above-described drawings indicate the same members having the same function.

Referring to FIG. 6, the front substrate 51 is formed at both ends of the display area D to display an image by forming pixels, and is connected to an external terminal so as to transfer electrical signals to each other. It may be divided into a non-display area (E) and (F).

In the display area D, strip-shaped bus electrodes 52 are formed at predetermined intervals. The bus electrode 52 has a double layer structure. In addition, although not illustrated as described above, a pair of sustain electrodes are formed on the inner wall of the bus electrode 52, and a black mattress layer is formed in a non-discharge area corresponding to a pair of neighboring bus electrodes. Of course.

The dummy bus electrode 59 is formed in the non-display area E and F in the same direction as the direction in which the bus electrode 52 is disposed. The dummy bus electrode 59 has a single layer structure.

The structure of the bus electrode 51 formed in the display area D and the dummy bus electrode 59 formed in the non-display area E and F will be described with reference to FIG. 7 taken along the line II-II. As shown.

The bus electrode 52 formed in the display area D includes a first bus electrode 52b patterned in a strip shape on an upper surface of the front substrate 51. The first bus electrode 52b is formed of a black layer that serves as a light shielding film to improve contrast. The first bus electrode 52b is formed of ruthenium (Ru), metal such as chromium (Cr), cobalt (Co), or a mixture of frits in an alloy thereof.

On the upper surface of the first bus electrode 52a, a second bus electrode 52b made of a white layer is formed to improve conductivity. The second bus electrode 52b is made of metal such as silver (Ag), aluminum (Al), gold (Au), and copper (Cu).

As such, the bus electrode 51 has a double layer structure in which a first bus electrode 52a and a second bus electrode 52b are formed on an upper surface of the first bus electrode 52a.

The dummy bus electrode 59 is formed in the non-display area E. Unlike the bus electrode 52, the dummy bus electrode 59 has a single layer structure. That is, the dummy bus electrode 59 is a white layer made of a metal material having excellent conductivity, such as silver (Ag), aluminum (Al), gold (Au), or copper (Cu). The dummy bus electrode 59 may be substantially the same material as the second bus electrode 52b.

When comparing the characteristics of the dummy bus electrode according to Examples I to V formed by the applicant's experiment and the dummy bus electrode according to the conventional comparative example is shown in Table 1.

Type of dummy bus electrode Width of dummy bus electrode (w) Thickness of dummy bus electrode (t) resistance Dielectric Layer Defective Rate Example White single layer I 100 μm 5 μm 40Ω / 0.9m 3% White single layer Ⅱ 120 μm 5 μm 32Ω / 0.9m 2% White single layer Ⅲ 140 μm 5 μm 24Ω / 0.9m One% White Single Floor IV 160 ㎛ 5 μm 19Ω / 0.9m 0.6% White Single Floor V 100 μm 6 μm 34 Ω / 0.9m 2.5% White Single Floor VI 100 μm 7㎛ 28Ω / 0.9m 1.5% White single layerⅦ 100 μm 8㎛ 21Ω / 0.9m One% Comparative example Black + White Double Layer 100 μm 6.5㎛ 70 Ω / 0.9m 8%

Referring to Table 1, the dummy bus electrode of the present invention was formed of a single white layer, and the resistance value was measured by varying the width (w) and thickness (t) of each dummy bus electrode, and the dielectric layer was destroyed due to wall charge accumulation. The failure rate was investigated. The conventional dummy bus electrode is formed of a double layer of black and white, and the resistance and the incidence of breakage failure of the dielectric layer were investigated.

When the width (w) of the dummy bus electrode of the present invention was increased in the order of 100 µm, 120 µm, 140 µm, and 160 µm, the resistance value was measured when the thickness t of the dummy bus electrode was 5 µm. /0.9m, 32Ω / 0.9m, 24Ω / 0.9m, 19Ω / 0.9m in order to reduce the failure rate of the dielectric layer was significantly reduced in the order of 3%, 2%, 1%, 0.6%. In other words, it can be seen that as the width of the dummy bus electrode increases, the breakdown of the dielectric layer due to the wall charge accumulation decreases.

When the width w of the dummy bus electrode of the present invention is 100 m and the thickness t of the dummy bus electrode is changed to 6 m, 7 m and 8 m, the resistance value is measured. 28 Ω / 0.9m, 21 Ω / 0.9m was reduced in order, the failure rate of the dielectric layer was reduced in the order of 2.5%, 1.5%, 1%. That is, as the thickness of the dummy bus electrode increases, the breakdown of the dielectric layer due to the wall charge accumulation decreases.

On the contrary, when the resistance value was measured while the width w of the dummy bus electrode of the comparative example was 100 μm and the thickness t of the dummy bus electrode was 6.5 μm, the resistance value was measured as 70 Ω / 0.9 m. As a result, the defective rate of the dielectric layer due to wall charge accumulation was about 8%.

In conclusion, when the dummy bus electrode of the present invention is formed of a single layer of white, the resistance value is reduced, compared to when a black + white double layer of the conventional dummy bus electrode is formed, and the failure rate of the dielectric layer due to the wall charge accumulation is reduced. It can be seen that the decrease significantly. In addition, as the width and thickness of the dummy bus electrode of the present invention increase, the resistance decreases, so that the failure rate of the dielectric layer can be further reduced.

8A to 8F sequentially illustrate a process of forming the bus electrode 52 and the dummy bus electrode 59 according to an exemplary embodiment of the present invention.

First, the paste for the first bus electrode 52a is printed using the squeegee 81 on the upper surface of the front substrate 51. At this time, the paste for the first bus electrode 52a is printed only in the display area and is black. (FIG. 8A)

Next, the paste for the first bus electrode 52a is dried by the IR device 82 (FIG. 8B).

The paste for the second bus electrode 52b is applied onto the dried paste for the first bus electrode 52a by using the squeegee 83. The paste for the second bus electrode 52b fills the first bus electrode 52a.

At this time, in the non-display area divided at both ends of the display area, the paste for the dummy bus electrode 59, which is substantially the same material as the paste for the second bus electrode 52b, is simultaneously printed.

In this manner, the pastes for the second bus electrode 52b and the dummy bus electrode 59 are printed on both the display area and the non-display area, and are made of a conductive white layer. (FIG. 8C).

Next, the pastes for the second bus electrode 52b and the dummy bus electrode 59 are dried by the IR device 84 (FIG. 8D).

After drying the first and second bus electrodes 52a and 52b and the dummy bus electrode 59 paste, the photomask 85 is arranged on the upper portion thereof, and then patterned by ultraviolet rays. 8e)

After the exposure process, a predetermined developer is sprayed and fired, and as shown in FIG. 8F, the black first bus electrode 52a and the white second bus electrode 52b are disposed in the display area D. As shown in FIG. The bus electrode 52 is formed, and at the same time, a white dummy bus electrode 59 is formed in the non-display area (E) (F).

As described above, a plasma display panel having different electrode structures according to the present invention, and a method of manufacturing the same, have electrodes having a double layer structure in the display area and dummy electrodes having a single layer structure in the non-display area. By doing so, the following effects can be obtained.                     

First, since only the dummy electrode having a single white layer having excellent conductivity is formed in the non-display area, the conductivity of the dummy electrode is improved, thereby improving the ability of removing wall charges accumulated in the panel.

Second, as the wall charge removal ability is improved, the dielectric breakdown of the dielectric layer is significantly reduced.

Third, manufacturing costs can be reduced by forming only a dummy electrode made of a single white layer in the non-display area.

Fourth, as the width and thickness of the dummy electrode formed in the non-display area are increased, the failure rate of failure of the dielectric layer can be reduced.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (16)

A plurality of substrates facing each other; An electrode having a double layer structure on a display area for displaying an image on the substrate; And a dummy electrode disposed in a non-display area partitioned outward from the display area, to which power is applied, and having a single layer structure. 2. The method of claim 1, And the electrode comprises a first black electrode formed on the upper surface of the substrate and a second electrode formed on the first electrode and white. The method of claim 2, The first electrode is a plasma display panel having a different electrode structure, characterized in that the frit is mixed with chromium, ruthenium, cobalt or their alloys to improve the contrast. The method of claim 2, And the second electrode is made of any one metal selected from conductive silver, aluminum, gold, and copper. The method of claim 1, The dummy electrode is a plasma display panel having a different electrode structure, characterized in that the conductive electrode is made of any one of metal, silver, aluminum, gold, copper. The method of claim 2, And the second electrode is made of the same material as that of the dummy electrode. The method of claim 1, And the dummy electrodes have a width within 100 to 160 micrometers. The method of claim 1, And the dummy electrodes have a thickness of 5 to 8 micrometers or less. Front substrate; A storage electrode formed on a lower surface of the front substrate; A bus electrode having a double layer structure electrically connected to the sustain electrode and disposed in a display area for displaying an image; A dummy bus electrode disposed in a non-display area partitioned out of the display area and having a single layer structure to which power is applied; A front dielectric layer filling the sustain electrode, the bus electrode, and the dummy bus electrode together; A rear substrate disposed to face the front substrate; An address electrode formed on an upper surface of the rear substrate; Barrier ribs formed between the front and rear substrates; And And a red, green, and blue phosphor layer coated in the discharge space partitioned by the partition wall. The method of claim 9, The bus electrode includes a first bus electrode of black color formed on the upper surface of the substrate and a second bus electrode of white color formed on the upper surface of the first bus electrode. Display panel. The method of claim 9, And the dummy bus electrode is made of a conductive white metal material. The method of claim 10, And the second bus electrode is formed of the same material as the dummy bus electrode. Preparing a substrate; Completely printing a paste for a first bus electrode formed in a display area for displaying an image on the substrate; Drying the first bus electrode paste; Simultaneously printing the second bus electrode paste on the upper surface of the first bus electrode paste and the dummy bus electrode paste on the non-display area partitioned outward from the display area; Drying the printed second bus electrode paste and the dummy bus electrode paste; And Exposing, developing, and firing the dried second bus electrode paste, the dummy bus electrode paste, and completing a bus electrode having a double layer structure, and a dummy bus electrode having a single layer structure. A method of manufacturing a plasma display panel having different electrode structures. The method of claim 13, The method of manufacturing a plasma display panel having different electrode structures, wherein the first bus electrode paste is printed on the entire surface using a black metal material to improve contrast. The method of claim 13, And the second bus electrode paste and the dummy electrode paste are printed on the entire surface of substantially the same material. The method of claim 15, And the second bus electrode paste and the dummy electrode paste are printed using a conductive white metal material.

Images