KR100643920B1 - Method for forming heterostructure field effect transistor - Google Patents

Abstract

A method for manufacturing a hetero-structure FET(Field Effect Transistor) is provided to prevent the degradation of a GaN based device by emitting easily the heat of the GaN based device to the outside using an electroplating layer as a support substrate. A GaN buffer layer(20) and a GaN sacrificial layer(70) are sequentially formed on a sapphire substrate(10). An AlGaN layer(40) and a GaN semi-insulating layer(30) are sequentially formed on the GaN sacrificial layer to form a hetero-junction structure. A mesa etching process is performed on the resultant structure to separate unit FETs from each other. A mask(90) for exposing partially the GaN semi-insulating layer to the outside is formed thereon. An electroplating layer(85) is formed on the exposed GaN semi-insulating layer. Then, the sapphire substrate is removed therefrom.

Description

Manufacturing method of heterostructure field effect transistor

1 is a cross-sectional view showing the structure of a conventional heterostructure field effect transistor.

2A to 2H are cross-sectional views sequentially illustrating a method of manufacturing a heterostructure field effect transistor according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: sapphire substrate 20: GaN buffer layer

30: GaN semi-insulating layer 40: AlGaN layer

50: channel layer 61: source

62: gate 63: drain

70: GaN sacrificial layer 80: crystal core layer

85: electroplating layer 90: mask

The present invention relates to a method for manufacturing a heterostructured field effect transistor, and more particularly, to a method for manufacturing a heterostructured field effect transistor that improves high output characteristics by improving thermal conductivity of the heterostructured field effect transistor.

Recently, the market for electronic devices for wireless communication is growing rapidly, and wireless communication technology for ultra-high speed and large capacity signal transmission is rapidly developing.

In line with this, high-quality electronic devices are being developed. Especially, GaN-based electronic devices are attracting attention as materials for next-generation high-frequency and high-power electronic devices, and are expected to be applied to high power of wireless communication systems.

Among the GaN-based electronic devices, a heterostructure field effect transistor (HFET) using a heterostructure of AlGaN / GaN has been studied the most.

The heterojunction structure of AlGaN / GaN has a high two-dimensional electron mobility and electron concentration distribution, and is known to be suitable for high frequency and high output devices.

In addition, the heterostructured field effect transistor uses sapphire as a substrate, and it will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a structure of a conventional heterostructured field effect transistor. As shown in FIG. 1, a conventional heterostructured field effect transistor includes a substrate 10 and a GaN buffer layer 20 formed on the substrate 10. ) And a GaN semi-insulating layer 30 and an AlGaN layer 40, which are sequentially formed on the GaN buffer layer 20 and in which the channel layer 50 is positioned at the interface therebetween.

In addition, the source 61, the gate 62, and the drain 63 are insulated from each other on the AlGaN layer 40.

Meanwhile, in order to obtain a high frequency and high output characteristic of the heterostructure field effect transistor including the GaN semi-insulating layer and the AlGaN layer, heat generated from the device must be smoothly discharged through the substrate.

In the conventional heterostructure field effect transistor described above, a sapphire substrate is used as a substrate, and the sapphire substrate is hard, electrically nonconductive, and has poor thermal conductivity.

Therefore, the conventional heterostructured field effect transistor has a limitation in dissipating heat generated in the device to the outside due to the low thermal conductivity of the sapphire substrate, thereby lowering the high output characteristics.

Accordingly, an object of the present invention is to provide a metal substrate having excellent thermal conductivity instead of a sapphire substrate in order to solve the above problems, thereby improving the thermal conductivity of the heterostructure field effect transistor to improve the high output characteristics of the device. The present invention provides a method for manufacturing a structured field effect transistor.

In order to achieve the above object, the present invention is a step of sequentially forming a GaN buffer layer and a GaN sacrificial layer on the sapphire substrate, and sequentially forming an AlGaN layer and a GaN semi-insulating layer on the GaN sacrificial layer to form a heterojunction structure And mesa-etching the heterojunction structure, the GaN sacrificial layer, and the GaN buffer layer to a unit field effect transistor size, and exposing a mask exposing the upper portion of the GaN semi-insulating layer on the separated result. Forming an electroplating layer on the GaN semi-insulating layer exposed through the mask, removing the sapphire substrate, and exposing the GaN buffer layer and the GaN sacrificial layer exposed through the removed sapphire substrate. Removing the mask, removing the mask, and forming a source, gate, and drain pattern on the AlGaN layer exposed through the removed GaN sacrificial layer. The method comprising; heterostructure containing provides a method for producing a field effect transistor.

In addition, in the method for manufacturing a heterostructure field effect transistor of the present invention, the mask is preferably formed using a photosensitive material or polyamide, which is to be easily removed through a subsequent development process or a wet etching process. .

In addition, in the method for manufacturing a heterostructure field effect transistor of the present invention, the step of forming an electroplating layer on the GaN semi-insulating layer exposed through the mask, forming a crystal nucleus layer on the separated GaN semi-insulating layer Forming a mask for exposing the upper portion of the seed layer on the resultant layer on which the seed layer is formed, and forming an electroplating layer on the entire upper surface of the resultant product on which the mask is formed using the seed layer exposed through the mask; It is preferred to include a step.

In addition, in the method for manufacturing a heterostructure field effect transistor of the present invention, forming the electroplating layer on the GaN semi-insulating layer exposed through the mask, the crystal nucleus layer on the GaN semi-insulating layer exposed through the mask. And forming an electroplating layer on the entire upper surface of the resultant product in which the mask is formed using the crystal core layer.

In addition, in the method of manufacturing the heterostructure field effect transistor of the present invention, the removing of the sapphire substrate, it is preferable to use a laser lift off method as a removal method.

In addition, in the method of manufacturing the heterostructure field effect transistor of the present invention, the removing of the GaN buffer layer and the GaN sacrificial layer exposed through the removed sapphire substrate, it is preferable to use a chemical mechanical polishing method as a removal method. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like parts throughout the specification.

A method of manufacturing a heterostructure field effect transistor according to an embodiment of the present invention will now be described in detail with reference to FIGS. 2A to 2H.

2A through 2H are cross-sectional views sequentially illustrating a method of manufacturing a heterostructure field effect transistor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, an undoped GaN buffer layer 20 and a GaN sacrificial layer 70 are sequentially formed on the substrate 10. In this case, the undoped GaN buffer layer 20 and the GaN sacrificial layer 70 serve to improve the crystallinity of the nitride-based semiconductor layer to be formed on the substrate 10.

In addition, the substrate 10 may be a substrate suitable for growing a nitride semiconductor single crystal, and may be a heterogeneous substrate such as a sapphire substrate and a silicon carbonate (SiC) substrate, or a homogeneous substrate such as a nitride substrate.

Then, a heterojunction structure composed of an AlGaN layer 40 and a GaN semi-insulating layer 30 is formed on the GaN sacrificial layer 70. In this case, the AlGaN layer 40 is an n-type AlGaN layer doped with n-type impurities, but is not limited thereto, and may be an undoped AlGaN layer, and the GaN semi-insulating layer 30 may be undoped. It is a semi-insulating layer doped with C and Fe in the GaN layer.

Meanwhile, the GaN semi-insulating layer 30 has a channel layer 50 at its interface due to energy band discontinuity with the AlGaN layer 40. Therefore, when voltage is applied, a tunneling phenomenon occurs at the n ⁺ -p ⁺ junction through the channel layer 50, thereby reducing contact resistance.

In addition, since the carrier mobility is ensured in the channel layer 50, the electron mobility can be improved more.

The preferable formation conditions of the channel layer 50 may be explained by the thicknesses of the GaN semi-insulating layer 30 and the AlGaN layer 40 and the Al content of the AlGaN layer 40.

More specifically, the thickness of the GaN semi-insulating layer 30 is preferably in the range of about 50 ~ 500Å in consideration of the tunneling phenomenon of the channel layer 50.

In addition, the thickness of the AlGaN layer 40 may be changed depending on the content of Al, but when the Al content is large, there is a fear that the crystallinity may be reduced, the Al content of the AlGaN layer 40 is 10 to 50% Preferably, the AlGaN layer 40 has a thickness in the range of about 100 to 500 kPa.

Subsequently, as shown in FIG. 2B, the GaN semi-insulating layer 30, the AlGaN layer 40, the GaN sacrificial layer 70, and the GaN buffer layer 20 are exposed so that a portion of the upper surface of the substrate 10 is exposed. A mesa etching process is performed to remove some regions and separated into unit field effect transistors.

Next, as shown in FIG. 2C, a crystal nucleus layer 80 serving as a crystal nucleus is formed on the separated GaN semi-insulating layer 30 in the electroplating process described later. At this time, it is preferable that the crystal nucleus layer 80 is formed using a metal having excellent electrical conductivity and thermal conductivity.

As shown in FIG. 2D, a mask 90 exposing a portion of the upper surface of the nucleus layer 80 is formed on the resultant in which the nucleus layer 80 is formed. In this case, the mask 90 is preferably formed by using a photosensitive material or polyamide, so that the mask 90 can be easily removed through a developing process or a wet etching process after the subsequent substrate 10 removal process.

Then, as shown in FIG. 2E, the electroplating layer 85 is electroplated using the nucleus layer 80 exposed through the mask 90 to form an electroplating layer 85 on the entire surface of the resultant product on which the mask 90 is formed. In this case, the electroplating layer 85 serves as a supporting substrate of the final heterostructure field effect transistor after the process of removing the substrate 10 to be described later. In addition, since the electroplating layer 85 is made of a metal having excellent thermal conductivity, for example, copper, gold, nickel, and the like, heat generated in a heterostructure field effect transistor can be easily released to the outside.

Therefore, the present invention can efficiently release heat through the electroplating layer even when a high current is applied to the heterostructure field effect transistor, thereby improving the high frequency and high output characteristics of the heterostructure field effect transistor.

Subsequently, as illustrated in FIG. 2F, the substrate 10 is removed through a laser lift-off process. At this time, the process of removing the substrate 10 is not limited to the laser lift-off process, and includes all the processes capable of removing the other substrate 10.

As shown in FIG. 2G, the GaN buffer layer 20 and the GaN sacrificial layer 70 exposed through the substrate 10 are removed by chemical mechanical polishing, and then a mask 30 made of photosensitive material or polyamide is removed. ) Is removed through a developing process or a wet etching process.

Then, a nitride-based semiconductor layer is grown on the exposed AlGaN layer 40 through the GaN sacrificial layer 70 to form a source 61, a gate 62, and a drain 62 pattern.

Subsequently, as shown in FIG. 2H, a plurality of unit heterostructure field effect transistors using the electroplating layer 85 as a support substrate are formed by performing a cutting process such as a driver or scribing on the electroplating layer 85. .

Although not shown, when forming the electroplating layer (see FIGS. 2B and 2D), first, a mask is formed on the separated GaN semi-insulating layer to expose a portion of the upper surface of the GaN semi-insulating layer. It is possible to form a crystallization layer on the exposed GaN semi-insulating layer, and then electroplating using the crystallization layer to form an electroplating layer on the entire upper surface of the resultant product on which the mask is formed. That is, even if the manufacturing process to form the electroplating layer proceeds differently as described above does not affect the device characteristics and reliability.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

As described above, the present invention provides a GaN series by forming a basic structure of a GaN-based electronic device on the sapphire substrate, removing the sapphire substrate, and forming an electroplating layer made of a metal having excellent thermal conductivity as a supporting substrate. It is possible to easily discharge the heat generated from the electronic device to the outside through the electroplating layer to prevent the GaN-based device deteriorated by the heat.

Therefore, the present invention has the effect of improving the high frequency and high output characteristics of the heterostructure field effect transistor which is a GaN series device.

Claims (6)

Sequentially forming a GaN buffer layer and a GaN sacrificial layer on the sapphire substrate; Forming a heterojunction structure by sequentially forming an AlGaN layer and a GaN semi-insulating layer on the GaN sacrificial layer; Separating the heterojunction structure, the GaN sacrificial layer, and the GaN buffer layer by mesa-etching to a unit field effect transistor size; Forming a mask on the separated result, exposing a top portion of the GaN semi-insulating layer; Forming an electroplating layer on the GaN semi-insulating layer exposed through the mask; Removing the sapphire substrate; Removing the GaN buffer layer and the GaN sacrificial layer exposed through the removed sapphire substrate; Removing the mask; And Forming a source, a gate, and a drain pattern on the AlGaN layer exposed through the removed GaN sacrificial layer. The method of claim 1, The mask is a method of manufacturing a heterostructure field effect transistor, characterized in that formed using a photosensitive material or polyamide. The method of claim 1, Forming an electroplating layer on the GaN semi-insulating layer exposed through the mask, Forming a crystal nucleus layer on the separated GaN semi-insulating layer; Forming a mask exposing the upper portion of the seed layer on the resultant seed layer; And Forming an electroplating layer on the entire upper surface of the resultant product on which the mask is formed by using the crystal nucleus layer exposed through the mask; and manufacturing a heterostructure field effect transistor. The method of claim 1, Forming an electroplating layer on the GaN semi-insulating layer exposed through the mask, Forming a nucleus layer on the GaN semi-insulating layer exposed through the mask; and forming an electroplating layer on the entire upper surface of the resultant product on which the mask is formed using the nucleus layer. Method of manufacturing a field effect transistor. The method of claim 1, The removing of the sapphire substrate, the method of manufacturing a heterostructure field effect transistor, characterized in that using a laser lift off method as a removal method. The method of claim 1, Removing the GaN buffer layer and the GaN sacrificial layer exposed through the removed sapphire substrate, using a chemical mechanical polishing method as a removal method.

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