KR100642484B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to reduce difference of polishing rate between an edge unit and a center unit of a wafer by performing a first and a second CMP(Chemical Mechanical Polishing) whose pressure rate is 50% to 100%. A dielectric(120) having a groove(123) is formed on a predetermined structure(110) of a wafer(100). A barrier metal layer(130) and a copper layer(140) are formed in turn on the dielectric and the groove. The copper layer is planarized to expose the barrier metal layer by a first CMP(Chemical Mechanical Polishing) process. Surfaces of the barrier metal layer and the dielectric are etched by a second CMP process. The first and the second CMP process are performed by using a CMP apparatus. The CMP apparatus includes a head unit and a polishing unit. The wafer is attached to the head unit. The polishing unit is located under the head unit and connected to the wafer to polish it. First pressure is applied to the head unit by the CMP apparatus. Second pressure is applied to a rear of the wafer by the CMP apparatus. The value of the second pressure/the first pressure is greater than 50% and less than 100% in the CMP process.

Description

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

1 to 3 are diagrams illustrating manufacturing steps of a semiconductor device according to one embodiment of the present invention.

4 is a schematic diagram of a CMP apparatus used in a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 illustrates a correlation between second CMP process time and in-wafer uniformity (WIWNU).

FIG. 6 is a diagram illustrating a correlation between an etching amount, a uniformity, and a yield of an insulating film in a second CMP process.

7 is a diagram illustrating a first CMP process time according to a pressure ratio.

8A is an end point detection (EPD) graph when the pressure ratio is 33%, and FIG. 8B is an EPD graph when the pressure ratio is 75%.

FIG. 9A is a diagram illustrating a result of 2-variance analysis on the etching amount of the insulating film when the pressure ratio in the first CMP process is 33% and when the pressure ratio is 75%, and FIG. 9B is a pressure ratio 33 in the second CMP process. Fig. 2 shows the results of 2-variance analysis on the etching amount of the insulating film in the case of% and 75%.

FIG. 10 is a graph comparing yields of wafers subjected to a first CMP and a second CMP process under various conditions with respect to various types of devices R1, R2, R3, and R4.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a metal wiring of a semiconductor device using a dual damascene process.

In general, metal wirings of semiconductor devices are formed for connection between devices or for connection between external circuits and devices. Metal wiring is formed by the following process.

First, contact holes are formed in the insulating film on the lower conductive film, and metal plugs are formed in the contact holes using barrier metal and tungsten. Then, a metal thin film is formed on the insulating film, and patterned to form a metal wiring connected to the metal plug.

In forming a metal interconnection by a photolithography process, it is difficult to form a fine metal interconnection due to a decrease in the critical dimension (CD) of the metal interconnection due to miniaturization of a semiconductor device. The process introduced to form such a fine metal wiring is a damascene process.

The damascene process forms a tungsten plug in the contact hole of the insulating film, and then deposits an upper insulating film such as an oxide film on the insulating film, and removes only the upper insulating film of the portion where the metal wiring pattern is to be formed by a photolithography process, and the metal thin film on the upper portion thereof. After depositing the planar metal thin film to form a fine metal wiring. In recent years, a dual damascene process has been introduced in which metal wirings integrally connected to the lower conductive film are formed without the formation of metal plugs such as tungsten plugs.

The dual damascene process proceeds as follows. First, after the etch stop layer and the insulating layer are stacked in duplicate, an etching process is performed using an etch selectivity of the etch stop layer and the insulating layer to form contact holes and trenches. The barrier metal and the metal layer are deposited on the contact hole, the trench and the insulating layer, and the metal layer is planarized by a chemical mechanical polishing (CMP) process to form metal wiring, for example, copper wiring.

However, when the surface uniformity of the metal layer planarized by such a CMP process is low, the manufacturing process speed becomes slow and a yield falls.

An object of the present invention is to provide a method for manufacturing a semiconductor device for improving the polishing uniformity in a wafer.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming an insulating film having a groove on a predetermined structure on a wafer, sequentially forming a barrier metal layer and a copper layer in the insulating film and the groove, planarizing the copper layer A first CMP step of exposing the barrier metal layer, a second CMP step of etching the surfaces of the barrier metal layer and the insulating film, wherein the first CMP step and the second CMP step are performed by using a CMP apparatus, and The CMP apparatus includes a head portion to which the wafer is attached, a polishing portion positioned below the head portion and in contact with the wafer to polish the wafer, wherein the pressure applied to the head portion by the CMP apparatus is a first pressure. When the pressure applied to the back surface of the wafer is called a second pressure, the value of the second pressure / first pressure in the first CMP step is greater than 50% and 100%. Smaller is preferred.

In addition, the value of the second pressure / first pressure in the second CMP step is preferably greater than 50% and less than 100%.

In addition, the rotational speed of the head portion is preferably greater than the rotational speed of the polishing portion.

In addition, the groove is preferably made of a via hole and a trench.

In addition, the trench may be formed on the via hole, and may be formed wider than the via hole.

In addition, the head portion is connected to the injection tube, it is preferable that the pressure of the air injected through the injection tube is the second pressure.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part "directly" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 to 3 are diagrams illustrating manufacturing steps of a semiconductor device according to one embodiment of the present invention, and FIG. 4 is a diagram illustrating a CMP apparatus used in the method of manufacturing a semiconductor device according to an embodiment of the present invention. Schematic drawing.

As shown in FIG. 1, in the method of manufacturing a semiconductor device according to an exemplary embodiment, an insulating layer 120 having a groove 123 is formed on a predetermined structure 110 on a wafer 100. The groove 123 is formed of a via hole 121 and a trench 122. The trench 122 is formed on the via hole 121 and is wider than the via hole 121.

 The barrier metal layer 130 is formed on the insulating film 120 and the groove 123. The copper layer 140 is thickly formed on the barrier metal layer 130 by an electrochemical plating process.

Next, as shown in FIG. 2, the first CMP process is performed to planarize the thickly deposited copper layer 140 to expose the barrier metal layer 130. At this time, the first CMP process is performed using the CMP apparatus.

As shown in FIG. 4, the CMP apparatus includes a head portion 10 to which the wafer 100 is attached, a polishing portion positioned below the head portion 10 and in contact with the wafer 100 to polish the wafer 100. (30).

The head portion 10 is directly pressed against the polishing portion 30 and the wafer 100 is brought into contact with the polishing portion 30 while the head portion 10 and the polishing portion 30 are relatively rotated at a constant speed. (100) is polished. In addition, an injection tube 51 is connected to the head part 10, and air is injected through the injection tube 51 to pressurize the wafer 100.

A supply pipe 52 for supplying a slurry is connected to the polishing unit 30. A slurry refers to a mixture of solid and liquid or a suspension in which fine solid particles are suspended in water. This slurry is supplied on the wafer 100 during polishing of the wafer 100 to facilitate the planarization process of the wafer 100.

Uniformity includes in-wafer-non-uniformity (WIWNU) and wafer-to-wafer-non-uniformity (WTWNU).

The in-wafer polishing uniformity WIWNU by the first CMP process depends on the pressurization conditions, the relative rotational speed, the slurry supply amount, and the like of the wafer 100. In addition, the uniformity (WIWNU) of the surface of the wafer 100 is an important factor in determining the yield of the wafer 100.

When the pressure that directly presses the head portion 10 is the first pressure AP1 and the pressure applied to the back surface of the wafer 100 by the air injected through the injection pipe 51 is called the second pressure AP2, The value of the second pressure / first pressure is preferably greater than 50% and less than 100%, more preferably when the pressure ratio is 75%.

In addition, the rotational speed of the head portion 10 of the CMP apparatus is preferably larger than the rotational speed of the polishing portion 30.

In the first CMP process, the thickly deposited copper layer 140 may be removed at a high speed, and the planarization process should be stopped when the barrier metal layer 130 is exposed. Therefore, it is preferable to use a high selectivity slurry. .

Next, as shown in FIG. 3, the second CMP process is performed to etch the surfaces of the barrier metal layer 130 and the insulating film 120. This is to separate the copper layer 140 into the copper wiring 145 by filling the trench 122 and the via hole 11. At this time, the value of the second pressure / first pressure is preferably larger than 50% and smaller than 100%, more preferably when the pressure ratio is 75%.

In the second CMP process, three layers, that is, the copper layer 140, the barrier metal layer (Ta / TaN) 130, and the insulating layer (p-SiH 4) 120 must be removed at the same time, so that a low selectivity slurry can be obtained. Is preferably used.

The polishing uniformity WIWNU in the wafer 100 by the second CMP process depends on the pressing conditions, the relative rotational speed, the slurry supply amount, and the like of the wafer 100. In addition, the uniformity (WIWNU) of the surface of the wafer 100 is an important factor in determining the yield of the wafer 100.

FIG. 5 shows the correlation between the second CMP process time and the in-wafer uniformity (WIWNU). As shown in FIG. 5, the longer the second CMP process time, the better the WIWNU.

6 illustrates the correlation between the etching amount, uniformity, and yield of the insulating film in the second CMP process. In FIG. 6, the horizontal axis represents yield and the vertical axis represents etching amount of the insulating layer. As shown in FIG. 6, the yield is improved as the amount of etching of the insulating film 120 increases in the second CMP process. In addition, as the variation in yield (3 sigma) between the wafers 100 becomes smaller, the yield also improves. In other words, a small variation in yield between the wafers 100 means that the uniformity in the wafer 100 is improved. On the contrary, the wafer 100 having good uniformity shows a high yield and a small yield variation between the wafers 100. Therefore, in order to improve the yield, it is desirable to improve the uniformity.

Polishing uniformity in the wafer 100 is a ratio of the pressure (first pressure) directly pressurizing the head portion 10 and the pressure (second pressure) applied to the back surface of the wafer 100 by air injected through the injection pipe. Depends on. In addition, the polishing uniformity in the wafer 100 depends on the ratio of the rotational speed of the head portion 10 and the rotational speed of the polishing portion 30.

Table 1 shows the polishing uniformity in the wafer 100 when the CMP process was performed while varying the pressure ratio and the rotational speed ratio.

TABLE 1

WIWNU Rotation speed ratio 50% 75% 107% Pressure ratio 75% 6.8 6.2 6.1 50% 7.5 7.5 8.4 33% 10.3 9.3 9.8

As shown in Table 1, it can be seen that WIWNU improves as the pressure ratio and the rotation speed ratio increase. In addition, it can be seen that the pressure ratio has a greater influence on the WIWNU than the rotation speed ratio.

FIG. 7 shows a first CMP process time according to the pressure ratio, FIG. 8A shows an end point detection (EPD) graph when the pressure ratio is 33%, and FIG. 8B shows an EPD graph when the pressure ratio is 75%. Is shown.

As shown in FIG. 7, the first CMP process time when the pressure ratio is 75% is reduced by 10 to 16% compared to when the pressure ratio is 33% in the first CMP process. That is, the first CMP process time when the pressure ratio is 75% is about 15 seconds shorter than when the pressure ratio is 33% in the first CMP process. As the pressure ratio increases, the difference in polishing rate between the edge portion and the center portion of the wafer 100 decreases, so that the end point detection time is shortened, as shown in FIGS. 8A and 8B, and the first CMP. This is because the uniformity of the process is improved. In FIGS. 8A and 8B, the horizontal axis represents the time axis, the vertical axis represents the thickness, and three lines in the figure represent the thickness change of the wafer between the edge portion, the center portion, and the edge portion between the edge portion and the center portion.

In FIG. 8A, each line is changed at a predetermined interval from each other. In FIG. 8B, since each line is changed to be almost the same, the end point detection time is shortened when the pressure ratio is 75%. That is, in FIG. 8A where the pressure ratio is 33%, the end point detection time takes 84.6 seconds, whereas in FIG. 8B where the pressure ratio is 75%, the end point detection time takes 72.3 seconds. In FIG. 8A and FIG. 8B, the time at the upper right represents the total CMP process time, and FIG. 8B also reduces the total CMP process time. This tendency is the same regardless of the layer of copper wiring through which the CMP process proceeds.

Therefore, the larger the pressure ratio in the first CMP process and the second CMP process, the better the WIWNU.

On the other hand, the 2-variance method is used to test the difference of the average value according to the pressure ratio conditions in the first and second CMP process.

9A shows the results of 2-variance analysis on the etching amount of the insulating film when the pressure ratio in the first CMP process is 33% and the 75%. In FIG. 9B, the pressure ratio in the second CMP process is 33%. The results of 2-variance analysis on the etching amount of the insulating film in the case of 75% and the case shown are shown. In the 2-variance analysis, if the P value is less than 0.05, the factor is determined to be significant.

As shown in FIG. 9A, the dispersion of the average value of the etching amount of the insulating film in the case where the first CMP process is performed at the pressure ratio of 75% is better than that in the first CMP process at the pressure ratio of 33%, and the sigma ( The dispersion of σ) values is small. Good dispersion of the average value of the etching amount of the insulating film means that WTWNU is good, and small dispersion of the sigma value means that WIWNU is good. That is, since the P value of F-TEST is 0.029 and the P value of Levene's TEST is 0.011, the first CMP process is performed at 75% pressure ratio than the first CMP process at 33% pressure ratio. It means good.

In addition, as shown in FIG. 9B, the dispersion of the average value of the etching amount of the insulating film when the second CMP process is performed at a pressure ratio of 75% is better than when the second CMP process is performed at a pressure ratio of 50%, The distribution of sigma (σ) values is small. Good dispersion of the average value of the etching amount of the insulating film means that WTWNU is good, and small dispersion of the sigma value means that WIWNU is good. That is, since the P value of F-TEST is 0.008 and the P value of Levene's TEST is 0.001, the second CMP process is performed at 75% pressure ratio than the case where the second CMP process is performed at 50% pressure ratio. It means good.

In addition, a 2 way ANOVA method is used to identify significant factors in the first and second CMP processes and to test the interaction between the first and second CMP processes. Each confidence interval was 95%.

In the analysis results using the 2 way ANOVA method, if the P value is less than 0.05, the factor is determined to be significant. Since the P value of the first CMP process is 0 and the P value of the second CMP process is 0.033, both the first and second CMP processes are significant factors, and the first CMP process is more significant than the second CMP process. I can figure it out. In addition, since the P value of the interaction is 0.023, which is larger than 0.05, it is possible to determine that the first and second CMP processes do not have an interaction.

FIG. 10 is a graph comparing yields of wafers subjected to a first CMP and a second CMP process under various conditions with respect to various types of devices R1, R2, R3, and R4. Here, condition A is when the pressure ratio of the first CMP process is 33%, pressure ratio of the second CMP process is 50%, and condition B is the pressure ratio of the first CMP process is 33%, and the pressure ratio of the second CMP process is 75%. C condition is when the pressure ratio of the first CMP process is 75%, the pressure ratio of the second CMP process is 75%, D condition is the pressure ratio of the first CMP process is 75%, the pressure ratio of the second CMP process is 50%.

As shown in FIG. 10, it can be seen that the yield of the wafer 100 subjected to the first and second CMP processes by applying the B, C, or D conditions is higher than the A condition.

In addition, it can be seen that the yield of the wafer 100 to which the pressure ratio of 75% is applied to both the first and second CMP processes is higher than when the pressure ratio of 75% is applied to only one of the first and second CMP processes. .

The method of manufacturing a semiconductor device according to an embodiment of the present invention improves WIWNU by allowing the pressure ratio of the first and second CMP processes to be 50% to 100%. In other words, the difference in polishing rate between the edge portion and the center portion of the wafer is small, thereby improving the polishing uniformity in the wafer.

In addition, the greater the pressure ratio, the shorter the first and second CMP process times, thereby improving productivity and yield.

In addition, the larger the pressure ratio, the smaller the rate of change of the etching amount of the insulating film in the second CMP process, thereby improving WIWNU.

Although the preferred embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims (6)

Forming an insulating film having a groove on a predetermined structure on the wafer, Sequentially forming a barrier metal layer and a copper layer on the insulating film and the groove; A first CMP step of planarizing the copper layer to expose the barrier metal layer, A second CMP step of etching surfaces of the barrier metal layer and the insulating layer Including, The first CMP step and the second CMP step are performed using a CMP apparatus, wherein the CMP apparatus includes a head portion to which the wafer is attached, a polishing portion positioned below the head portion and in contact with the wafer to polish the wafer. Including, When the pressure applied to the head portion by the CMP apparatus is a first pressure and the pressure applied to the back surface of the wafer is a second pressure, And wherein the value of the second pressure / first pressure in the first CMP step is greater than 50% and less than 100%. In claim 1, And wherein said second pressure / first pressure value in said second CMP step is greater than 50% and less than 100%. In claim 1, The rotation speed of the head portion is larger than the rotation speed of the polishing portion. In claim 1, The groove is a semiconductor device manufacturing method of the via hole and the trench. In claim 4, The trench is formed on the via hole, the method of manufacturing a semiconductor device wider than the via hole. In claim 1, An injection tube is connected to the head, and the pressure of air injected through the injection tube is the second pressure.

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