KR100641543B1 - Circuit for protection electrostatics discharge - Google Patents

Circuit for protection electrostatics discharge Download PDF

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KR100641543B1
KR100641543B1 KR1020050131527A KR20050131527A KR100641543B1 KR 100641543 B1 KR100641543 B1 KR 100641543B1 KR 1020050131527 A KR1020050131527 A KR 1020050131527A KR 20050131527 A KR20050131527 A KR 20050131527A KR 100641543 B1 KR100641543 B1 KR 100641543B1
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South Korea
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ground terminal
diode
nmos transistors
gate
protection circuit
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KR1020050131527A
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Korean (ko)
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송상수
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An ESD(electrostatics discharge) protect circuit is provided to reducing ESD fail by partially turning on of a GGNMOS. The ESD(electrostatics discharge) protect circuit is located between a pad(110) and a ground terminal(Vss), and discharges electrostatics to the ground terminal. The ESD protect circuit is comprised of a plurality of NMOS transistors(n1-n10) and a diode. The plurality of NMOS transistors are connected between the pad and the ground terminal parallel. The each NMOS transistors are connected to a gate and a source commonly. A body of the NMOS transistor is connected to the ground terminal. A diode is commonly connected between a gate-source of the NMOS transistors and the ground terminal. The diode is n-type diode and is connected forward between the gate-source of the NMOS transistors and the ground terminal.

Description

ＥＳＤ 보호 회로{Circuit for protection Electrostatics discharge}ESD protection circuit {Circuit for protection Electrostatics discharge}

도 1은 종래의 ESD 보호 회로를 나타낸 도면이다.1 is a view showing a conventional ESD protection circuit.

도 2는 본 발명의 ESD 보호 회로를 나타낸 도면이다.2 is a view showing an ESD protection circuit of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100 : ESD 보호 회로 110 : 패드 n1∼n10 : GGNMOS100: ESD protection circuit 110: pads n1 to n10: GGNMOS

본 발명은 ESD(Electrostatics discharge) 보호 회로에 관한 것으로, 보다 구체적으로는 다수의 GGNMOS(gate ground NMOS) 트랜지스터로 구성되는 ESD 보호 회로에 관한 것이다.The present invention relates to an electrostatics discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit composed of a plurality of gate ground NMOS (GGNMOS) transistors.

반도체 집적 회로는 그 구동을 위하여 외부로부터 전압을 인가받는다. 이때 전압을 인가받을 때, 패드를 통하여 급격히 크거나 작은 정전기 전압이 입력될 수 있다. 이러한 정전기 전압은 상술한 바와 같이 반도체 집적 회로의 구동 전압 보다 급격히 크거나 작음에 따라, 이러한 정전기 전압이 반도체 집적 회로에 필터링없이 입력되면, 소자가 파손된다. 이러한 문제점을 방지하기 위하여, 종래에는 급격히 큰 정전기 전압이 입력되는 경우 이를 반도체 내부 회로에 전달시키지 않도록 하는 ESD 보호 회로가 반도체 집적 회로의 입력단에 설치되고 있다. The semiconductor integrated circuit receives a voltage from the outside for its driving. At this time, when a voltage is applied, a large or small static voltage may be input through the pad. As the electrostatic voltage is rapidly larger or smaller than the driving voltage of the semiconductor integrated circuit as described above, when such electrostatic voltage is input to the semiconductor integrated circuit without filtering, the device is broken. In order to prevent such a problem, conventionally, an ESD protection circuit is installed at an input terminal of a semiconductor integrated circuit so as not to transfer a large electrostatic voltage to a semiconductor internal circuit.

도 1은 현재 주로 사용되고 있는 GGNMOS(gate ground NMOS) 방식의 ESD 보호 회로를 나타낸다.FIG. 1 illustrates an ESD protection circuit using a gate ground NMOS (GGNMOS) method.

도 1을 참조하면, ESD 보호 회로(10)는 패드(15)와 접지단(Vss) 사이에 8개 내지 10개 정도의 NMOS 트랜지스터(N1∼N10)가 병렬로 연결된다. Referring to FIG. 1, in the ESD protection circuit 10, 8 to 10 NMOS transistors N1 to N10 are connected in parallel between the pad 15 and the ground terminal Vss.

NMOS 트랜지스터는 그것의 게이트와 소스 및 바디가 모두 접지단과 공통 연결되어 GGNMOS 형태를 갖는다. 이러한 ESD 보호 회로(10)는 정전기가 유입되지 않을 시에는 오픈된 상태로 동작되고, 정전기 유입시에는 패드에 가해지는 정전기를 접지단(Vss)으로 배출시키게끔 설계되어 있다. An NMOS transistor has a GGNMOS form with its gate, source and body all connected in common with the ground terminal. The ESD protection circuit 10 operates in an open state when static electricity does not flow, and is designed to discharge static electricity applied to a pad to the ground terminal Vss when static electricity flows.

종래의 ESD 보호 회로는 면역 레벨, 즉, 정전기가 유입되는 경우 상기 8개 내지 10개의 NMOS 트랜지스터가 모두 동작한다는 전제하에 구성된다. 그러나, 상기 ESD 보호 회로의 레이아웃이나 그 밖의 변수에 의해 상기 NMOS 트랜지스터가 모두 동작하지 않는 경우가 빈번하며, 이렇게 모든 NMOS 트랜지스터가 한꺼번에 동작되지 않고 몇 개의 NMOS 트랜지스터만이 동작되는 경우, 정전기가 모두 배출되지 않아 페일이 발생될 수 있다. Conventional ESD protection circuitry is constructed on the premise that all of the eight to ten NMOS transistors operate at an immune level, i. However, due to the layout of the ESD protection circuit and other variables, all of the NMOS transistors are frequently not operated. Thus, when all the NMOS transistors are not operated at once and only a few NMOS transistors are operated, all of the static electricity is discharged. Failing may occur.

따라서, 본 발명의 목적은 부분적인 NMOS 트랜지스터의 턴온을 방지하여, ESD 페일을 방지할 수 있는 ESD 보호 회로를 제공하는 것이다.Accordingly, it is an object of the present invention to provide an ESD protection circuit that can prevent partial turn-on of NMOS transistors, thereby preventing ESD failure.

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 패드와 접지단사이에 위치되어 패드에 인가되는 정전기를 접지단으로 배출시키는 ESD 보호 회로로서, 상기 패드와 접지단 사이에 병렬로 연결되는 게이트와 소스가 공통 접속된 다수의 NMOS 트랜지스터, 및 상기 각각의 NMOS 트랜지스터의 게이트-소스단과 접지단 사이에 공통으로 연결되는 다이오드를 포함한다.In order to achieve the above object of the present invention, the present invention is an ESD protection circuit which is disposed between the pad and the ground terminal to discharge the static electricity applied to the pad to the ground terminal, which is connected in parallel between the pad and the ground terminal. A plurality of NMOS transistors having a gate and a source connected in common, and a diode commonly connected between the gate-source terminal and the ground terminal of each NMOS transistor.

상기 다이오드는 n 타입 다이오드이고, 상기 다이오드는 NMOS 트랜지스터의 게이트-소스단과 접지단 사이에 순방향으로 연결된다.The diode is an n-type diode, which is forward connected between the gate-source and ground terminals of the NMOS transistor.

본 발명에 의하면, 상기한 다이오드에 의해 정전기 유입시 어느 하나의 GGNMOS가 턴온되더라도 상기 다이오드의 전위차에 의해 나머지 GGNMOS도 모두 턴온되므로써, 부분적인 GGNMOS의 턴온으로 인한 ESD 페일을 줄일 수 있다.According to the present invention, even if any one of the GGNMOS is turned on during the inflow of static electricity by the diode, all the remaining GGNMOS is turned on by the potential difference of the diode, thereby reducing the ESD failure due to the partial turn-on of the GGNMOS.

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2는 본 발명에 따른 ESD 보호 회로를 나타낸 것이다.2 shows an ESD protection circuit in accordance with the present invention.

도 2를 참조하여, 본 발명의 ESD 보호 회로(100)를 설명하면, 상기 패드(110)와 접지단(Vss) 사이에 다수의 NMOS 트랜지스터, 예컨대 8개 내지 10개의 NMOS 트랜지스터가 병렬로 연결된다. 참고로 본 실시예에서는 10개의 NMOS 트랜지스터(n1∼n10)로 ESD 보호 회로를 구성하였다.Referring to FIG. 2, in the ESD protection circuit 100 of the present invention, a plurality of NMOS transistors, for example, 8 to 10 NMOS transistors are connected in parallel between the pad 110 and the ground terminal Vss. . For reference, in this embodiment, an ESD protection circuit is composed of ten NMOS transistors n1 to n10.

상기 각각의 NMOS 트랜지스터는 그것의 게이트(g)와 소오스(s)가 모두 공통으로 묶여진다. 또한, 상기 NMOS 트랜지스터의 바디는 접지단(Vss)에 접속된다. Each NMOS transistor has its gate g and source s all tied together in common. In addition, the body of the NMOS transistor is connected to the ground terminal Vss.

각 NMOS 트랜지스터의 게이트-소오스(g-s)와 상기 접지단(Vss) 사이에 n타입 다이오드(120)가 공통으로 연결된다. 상기 n 타입 다이오드(120)는 순방향으로 연 결된다. The n-type diode 120 is commonly connected between the gate source g-s and the ground terminal Vss of each NMOS transistor. The n-type diode 120 is connected in the forward direction.

이와 같은 구성을 갖는 본 발명의 ESD 보호 회로는, 상기한 NMOS 트랜지스터(n1∼n10)중 한 개의 NMOS 트랜지스터라도 동작되면, 게이트-소스 접합 부분(A)과 접지단(B) 사이에 설치된 다이오드(120)는 순방향 전위차가 발생된다. The ESD protection circuit of the present invention having such a configuration has a diode provided between the gate-source junction portion A and the ground terminal B when any one of the above-described NMOS transistors n1 to n10 is operated. 120, a forward potential difference is generated.

그러면, 상기 전위차는 아직 동작하지 않는 다른 모든 NMOS 트랜지스터의 게이트에 일시에 제공되어, ESD 보호 회로를 구성하는 모든 NMOS 트랜지스터를 모두 구동시키게 된다. 따라서, 전체 NMOS 트랜지스터가 구동되므로서, ESD 페일을 방지할 수 있다. The potential difference is then temporarily provided to the gates of all other NMOS transistors not yet operating, driving all of the NMOS transistors constituting the ESD protection circuit. Thus, the entire NMOS transistor is driven, thereby preventing ESD failure.

이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형이 가능하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 게이트-소스가 공통 접속되는 GGNMOS 타입의 ESD 보호 회로에 있어서, 소수의 GGNMOS의 턴온을 방지하기 위하여, 각각의 GGNMOS의 게이트-소스단과 접지단 사이에 공통으로 다이오드를 설치한다. As described above in detail, according to the present invention, in the GGNMOS type ESD protection circuit in which the gate-source is commonly connected, in order to prevent the turn-on of a small number of GGNMOS, the gate-source end and the ground end of each GGNMOS are prevented. Install a diode in common.

그러면, 정전기 유입시 어느 하나의 GGNMOS가 턴온되더라도 상기 다이오드의 전위차에 의해 나머지 GGNMOS도 모두 턴온되므로써, 부분적인 GGNMOS의 턴온으로 인한 ESD 페일을 줄일 수 있다.Then, even when any one of the GGNMOS is turned on during the inflow of static electricity, the remaining GGNMOS is turned on by the potential difference of the diode, thereby reducing the ESD failure due to the partial turn-on of the GGNMOS.

Claims (3)

패드와 접지단사이에 위치되어 패드에 인가되는 정전기를 접지단으로 배출시키는 ESD 보호 회로로서,An ESD protection circuit located between the pad and the ground terminal to discharge static electricity applied to the pad to the ground terminal. 상기 패드와 접지단 사이에 병렬로 연결되는 게이트와 소스가 공통 접속된 다수의 NMOS 트랜지스터; 및A plurality of NMOS transistors having a common gate and a source connected in parallel between the pad and the ground terminal; And 상기 각각의 NMOS 트랜지스터의 게이트-소스단과 접지단 사이에 공통으로 연결되는 다이오드를 포함하는 ESD 보호 회로. And a diode commonly connected between the gate-source and ground terminals of each of the NMOS transistors. 제 1 항에 있어서, 상기 다이오드는 n 타입 다이오드인 것을 특징으로 하는 ESD 보호 회로.The ESD protection circuit according to claim 1, wherein the diode is an n-type diode. 제 1 항에 있어서, 상기 다이오드는 NMOS 트랜지스터의 게이트-소스단과 접지단 사이에 순방향으로 연결되는 ESD 보호 회로. 2. The ESD protection circuit of claim 1, wherein the diode is forward connected between the gate-source and ground terminals of the NMOS transistor.
KR1020050131527A 2005-12-28 2005-12-28 Circuit for protection electrostatics discharge KR100641543B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117081025A (en) * 2023-10-12 2023-11-17 芯耀辉科技有限公司 Power clamp protection circuit and chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117081025A (en) * 2023-10-12 2023-11-17 芯耀辉科技有限公司 Power clamp protection circuit and chip

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