KR100639018B1 - Non-reducing dielectric ceramic compositions for compensation of temperature and laminated ceramic capacitors having the same - Google Patents

Non-reducing dielectric ceramic compositions for compensation of temperature and laminated ceramic capacitors having the same Download PDF

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KR100639018B1
KR100639018B1 KR1020050084226A KR20050084226A KR100639018B1 KR 100639018 B1 KR100639018 B1 KR 100639018B1 KR 1020050084226 A KR1020050084226 A KR 1020050084226A KR 20050084226 A KR20050084226 A KR 20050084226A KR 100639018 B1 KR100639018 B1 KR 100639018B1
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윤중락
송재용
손창길
장운석
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삼화콘덴서공업주식회사
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Abstract

Provided are a reduction-resistant ceramic dielectric composition for temperature compensation which can be applied to a layered chip ceramic capacitor as a dielectric having a small thickness, and a layered chip ceramic capacitor using the composition. The ceramic dielectric composition comprises a main component represented by (1-x)CaZrO3-xBa5Nb4O15; and a side component which comprises at least one selected from the group consisting of calcium titanate, strontium zirconate and CaO-B2O3-SiO2-Li2O-MnO2-MoO3-based glass frit, wherein 0.07<=x<=0.20; and the amounts of calcium titanate, strontium zirconate and the glass frit to the main component are 5 wt% or less, 10 wt% or less and 3 wt% or less, respectively.

Description

온도보상용 내환원성 유전체 조성물 및 이를 적용한 적층 칩 세라믹 캐패시터{Non-Reducing Dielectric Ceramic Compositions for Compensation of Temperature and Laminated Ceramic Capacitors having the Same}Non-Reducing Dielectric Ceramic Compositions for Compensation of Temperature and Laminated Ceramic Capacitors having the Same}

도 1은 본 발명의 세라믹 유전체 조성물로 제조된 적층 세라믹 캐패시터를 나타낸 도면이다.1 is a view showing a multilayer ceramic capacitor made of the ceramic dielectric composition of the present invention.

본 발명은 환원성 분위기에서 소결 가능한 유전체 조성물 및 이를 이용한 적층 칩 세라믹 캐패시터에 관한 것으로, 보다 구체적으로는 Cu나 Ni 내부전극을 적용하여 유전특성과 소결특성뿐 아니라 절연특성도 우수한 온도보상용 적층 칩 세라믹 캐패시터에 적용 가능한 유전체 조성물에 관한 것이다.The present invention relates to a dielectric composition that can be sintered in a reducing atmosphere and a multilayer chip ceramic capacitor using the same. More specifically, by applying a Cu or Ni internal electrode, a multilayer chip ceramic for temperature compensation having excellent dielectric and sintering characteristics as well as insulation characteristics The present invention relates to a dielectric composition applicable to a capacitor.

적층 칩 세라믹 캐패시터는 전자회로에서 신호 차단, 결합, by-pass등의 역할을 하는 것으로 정전용량을 형성하기 위하여 서로 대향하는 다수의 내부전극 사이에 유전체 세라믹 층을 형성한 것이다. 일반적으로 세라믹 유전체는 온도특성과 유전율에 따라 온도보상용, 고 유전율계로 구분할 수 있다. 온도보상용의 경우 유 전율이 10∼100의 특성을 가지며, 고 유전율계는 BaTiO3를 주성분으로 하며 유전율은 2,000∼20,000 정도의 값을 가진다. Multilayer chip ceramic capacitors play a role of signal blocking, coupling, and by-pass in an electronic circuit. A dielectric ceramic layer is formed between a plurality of internal electrodes facing each other to form capacitance. In general, ceramic dielectrics can be classified into temperature compensation and high permittivity meters according to temperature characteristics and dielectric constant. In the case of temperature compensation, the dielectric constant is 10 to 100. The high dielectric constant is BaTiO 3 and the dielectric constant is about 2,000 to 20,000.

온도 보상용 유전체의 대표적인 조성물로서 대기중에서만 소결이 가능한 유전율 20대인 MgTiO3-CaTiO3계, 유전율 30∼40대인 BaTi4O9계, (Zr,Sn)TiO4계가 있으며 유전율 60∼100대인 Ba-Nd-Ti 산화물계가 있다. 이들 조성물들은 대기중에서는 우수한 특성을 나타내지만 산소 결핍인 환원성 분위기에서는 산화물의 일부가 소결중에 환원이 되어 절연저항이 감소하고 유전특성이 나빠지므로 내부 전극으로 Ni 또는 Cu를 적용할 수 없다.Typical compositions for temperature compensation dielectrics include MgTiO 3 -CaTiO 3 based on 20 dielectric constants that can be sintered only in the air, BaTi 4 O 9 based on dielectric constants between 30 and 40, and BaZ (Zr, Sn) TiO 4 based on dielectric constants of 60 to 100 -Nd-Ti oxide type. These compositions show excellent properties in the air, but in a reducing atmosphere that is oxygen deficient, some of the oxides are reduced during sintering, resulting in reduced insulation resistance and poor dielectric properties, so Ni or Cu cannot be applied as internal electrodes.

하지만, 최근 적층 칩 세라믹 캐패시터는 저가격화의 요구에 따라 캐패시터 제작비용의 30%이상을 점유하는 Ag-Pd, Pd와 같은 귀금속에서 저가의 Ni, Cu와 같은 비(卑)금속을 내부전극으로 사용하는 비중이 증가하고 있다. Ni이나 Cu와 같은 금속을 적층 칩 캐패시터에 적용시 Ni이나 Cu의 산화를 방지하기 위해 환원성 분위기에서 소결하여야 하므로 내환원성 특성을 가진 유전체 재료가 필요하다.However, in recent years, multilayer chip ceramic capacitors use inexpensive non-metals such as Ni and Cu as internal electrodes in precious metals such as Ag-Pd and Pd, which occupy more than 30% of the capacitor manufacturing cost due to the demand for low cost. The share is increasing. When a metal such as Ni or Cu is applied to a laminated chip capacitor, it is necessary to sinter in a reducing atmosphere in order to prevent oxidation of Ni or Cu, and thus a dielectric material having reduction resistance is required.

현재, 니켈(Ni) 내부 전극을 사용한 온도 보상용 유전체 조성물의 대표적인 예는 미국 특허 제6,118,648호와 일본 공개특허 평10-90751호 등에서 보고되고 있으며 A.sato등은 Key Engineering Materials(Vols,1, 157-158 (1999))에 "Low Frequency Dielectric Dispersion in(CaSr)(TiZr)O3 Compositions Fired in a Reducing Atmosphere"라는 제목으로 논문을 발표하였다. 상기 특허는 주성분인 [(CaXSr1-X)m(TiYZr1-Y)O3]계에 첨가물로 산화망간(MnO2), 알루미나(또는 산화알루미 늄, Al2O3, (BaCa)SiO3-glass를 함유하는 유전체 조성물에 관한 것으로 우수한 유전특성을 나타내지만, 유전율이 30∼40 정도로서 다소 낮아 고용량의 적층 칩 캐패시터나 고압용 적층 칩 캐패시터 제작시 유전체의 두께가 커지는 문제점을 가지고 있다. Currently, representative examples of temperature compensation dielectric compositions using nickel (Ni) internal electrodes are reported in US Pat. No. 6,118,648 and Japanese Patent Application Laid-open No. Hei 10-90751. A.sato et al. 157-158 (1999) published a paper entitled "Low Frequency Dielectric Dispersion in (CaSr) (TiZr) O3 Compositions Fired in a Reducing Atmosphere". The patent is an additive to the main component [(Ca X Sr 1-X ) m (Ti Y Zr 1-Y ) O 3 ] based manganese oxide (MnO 2 ), alumina (or aluminum oxide, Al 2 O 3 , ( It is a dielectric composition containing BaCa) SiO 3 -glass and shows excellent dielectric properties, but has a low dielectric constant of about 30 to 40 and has a problem of increasing dielectric thickness when fabricating a high capacity multilayer chip capacitor or a high voltage multilayer chip capacitor. have.

이러한 사정으로, 유전율이 40 이상으로 매우 높고 유전율의 온도계수, 품질개수 등의 유전특성이 우수한 적층 칩 세라믹 캐패시터에 적용할 수 있는 유전체 조성물의 개발에 대한 요구는 여전히 필요한 실정이다.For this reason, there is still a need for the development of a dielectric composition that can be applied to a multilayer chip ceramic capacitor having a very high dielectric constant of 40 or more and excellent dielectric properties such as temperature coefficient and quality factor of dielectric constant.

따라서, 본 발명은 이러한 사정을 감안하여 이루어진 것으로, 그 목적은 Ni나 Cu와 같은 저가의 금속을 내부전극으로 사용할 수 있을 뿐만 아니라 적층 칩 캐패시터 제작시 유전체의 두께를 얇게 할 수 있는 우수한 유전특성과 소결특성을 발휘하는 온도보상용 내환원성 세라믹 유전체 조성물 및 이를 적용한 적층 칩 세라믹 캐패시터를 제공하고자 하는 것이다.Accordingly, the present invention has been made in view of the above circumstances, and an object thereof is not only to use a low-cost metal such as Ni or Cu as an internal electrode, but also to provide excellent dielectric properties that can reduce the thickness of a dielectric when manufacturing a laminated chip capacitor. It is to provide a temperature-compensating, reduction-resistant ceramic dielectric composition exhibiting sintering characteristics and a multilayer chip ceramic capacitor using the same.

이러한 목적을 달성하기 위하여, 본 발명에 따르면, 주성분과 부성분으로 구성되는 온도보상용 내환원성 세라믹 유전체 조성물로서, 상기 주성분은, Ba5Nb4O15의 몰분율을 x라 할 때, 일반식 (1-x) CaZrO3-x Ba5Nb4O15으로 표시되며, 상기 x는 0.07≤x≤0.20 범위의 값을 가지며, 상기 부성분은 티탄산칼슘, 지르콘산 스트론튬, 그리고 CaO-B2O3-SiO2-Li2O-MnO2-MoO3계 유리프릿 중 적어도 어느 하나를 포함하며, 상 기 주성분에 대하여, 티탄산칼슘, 지르콘산 스트론튬 및 상기 유리프릿의 첨가량은, 각각 5wt% 이하, 10wt% 이하, 및 3wt% 이하인 것을 특징으로 하는 온도보상용 내환원성 세라믹 유전체 조성물이 제공된다.In order to achieve the above object, according to the present invention, as a temperature-compensation-resistant ceramic dielectric composition composed of a main component and a subcomponent, the main component, when the mole fraction of Ba 5 Nb 4 O 15 is x, -x) is expressed as CaZrO 3 -x Ba 5 Nb 4 O 15 , wherein x has a value in the range 0.07≤x≤0.20, the minor components are calcium titanate, strontium zirconate, and CaO-B 2 O 3 -SiO At least one of 2 -Li 2 O-MnO 2 -MoO 3- based glass frit, the addition amount of calcium titanate, strontium zirconate and the glass frit to the main components, respectively, 5wt% or less, 10wt% or less And a 3 wt% or less temperature-compensating, reduction resistant ceramic dielectric composition is provided.

또한, 본 발명에 따르면, 유전체 재료로서 상기 온도보상용 세라믹 유전체 조성물을 가지는 적층 칩 세라믹 캐패시터가 제공된다.Further, according to the present invention, there is provided a laminated chip ceramic capacitor having the temperature compensation ceramic dielectric composition as a dielectric material.

본 발명에서는 온도보상용 세라믹 유전체 조성물로 지금까지 알려져 온 CaZrO3에 온도 보상용이라는 규격에 적합한 온도특성을 만족하는 재료를 검토하던 중, Ba5Nb4O15가 유전율 39, 유전율의 온도계수가 -100ppm/℃로서 대기중에서 우수한 유전특성을 나타내는 것으로 보고되어 이를 선택하게 되었다.In the present invention, while CaZrO 3 , which has been known as a temperature compensating ceramic dielectric composition, has been studied for a material satisfying a temperature characteristic suitable for the temperature compensation standard, Ba 5 Nb 4 O 15 has a dielectric constant of 39 and a dielectric constant of- It was reported that it shows excellent dielectric properties in the air at 100 ppm / ° C and was selected.

한편, 본 발명에서는 주성분으로 CaZrO3에 Ba5Nb4O15를 몰비율을 변경하여 첨가함으로써 유전율 및 유전율의 온도계수를 조정하는 것이 가능하다. 구체적으로, (1-x) CaZrO3-x Ba5Nb4O15계 조성을 기본으로 하며 특히, Ba5Nb4O15의 몰분율 x가 0.07∼0.20 일 때 유전특성 및 절연저항 특성이 온도보상용으로 적절하며, Ba5Nb4O15을 0.07 미만으로 첨가한 경우 유전율 감소는 억제되나 절연저항 특성 및 품질계수(유전손실의 역수)특성이 저하되어 적층 칩 캐패시터의 사용에는 적절치 않다. 한편, Ba5Nb4O15의 몰분율 x가 0.20을 초과할 시에는 품질계수 및 유전율이 오히려 저하되어 본 발명의 목적에 부합하지 않는다.On the other hand, in the present invention, it is possible to adjust the dielectric constant and the temperature coefficient of the dielectric constant by adding Ba 5 Nb 4 O 15 to CaZrO 3 as a main component by changing the molar ratio. Specifically, based on the (1-x) CaZrO 3 -x Ba 5 Nb 4 O 15- based composition, in particular, when the mole fraction x of Ba 5 Nb 4 O 15 is 0.07 ~ 0.20 dielectric properties and insulation resistance properties for temperature compensation When Ba 5 Nb 4 O 15 is added below 0.07, the dielectric constant decreases, but the insulation resistance and the quality factor (inverse of the dielectric loss) are deteriorated, which is not suitable for the use of the multilayer chip capacitor. On the other hand, when the mole fraction x of Ba 5 Nb 4 O 15 exceeds 0.20, the quality factor and dielectric constant are rather lowered, which does not meet the object of the present invention.

한편, 본 발명의 조성물에 첨가되는 부성분으로 티탄산칼슘(CaTiO3), 지르콘 산 스트론튬(SrZrO3)을 첨가함으로 유전율의 향상 및 유전율의 온도계수의 조절이 가능하였으며, 구체적으로는 티탄산칼슘(CaTiO3)을 5wt%까지 첨가한 경우 유전율을 향상시킬 수 있으며, 지르콘산 스트론튬(SrZrO3)을 10wt%까지 첨가한 경우 유전율의 온도계수 및 품질계수를 향상시킬 수 있다.On the other hand, by adding calcium titanate (CaTiO 3 ), strontium zirconate (SrZrO 3 ) as an additional ingredient added to the composition of the present invention, the dielectric constant was improved and the temperature coefficient of the dielectric constant could be adjusted. Specifically, calcium titanate (CaTiO 3) ) Is added to 5wt% can improve the dielectric constant, and when strontium zirconate (SrZrO 3 ) is added to 10wt% can improve the temperature coefficient and quality factor of the dielectric constant.

또한, 또다른 부성분으로 첨가되는 유리프릿(glass frit)을 첨가하면 소성 온도가 낮아지며, 유리프릿 조성내에 산화망간(MnO2), 산화몰리(MoO3)를 첨가함으로 환원 분위기 소성중 원자가 보상으로 인하여 경시 변화에 의한 고온 절연저항특성이 개선되며 또한, 결정립계 사이에 액상의 절연층이 형성됨으로써 상온에서의 절연 저항(insulated resistance, IR) 특성이 개선된다. 유리프릿(glass frit)의 첨가량의 경우 3wt%까지는 상온 IR(25℃에서의 절연 저항)과 고온 IR(125℃에서의 절연 저항)이 동시에 증가하지만, 그 이상 첨가 시에는 상온 IR은 증가하는 경향을 보인다. 따라서 일반적으로 IR 값은 신뢰성과 연관이 있는 것으로 알려져 있으며, 특히 고온 IR 값이 저하되면 특성 열화가 나타난다는 사실을 고려할 때 고온 IR이 크게 감소하면 바람직하지 못하다.In addition, the addition of glass frit, which is added as another minor component, lowers the firing temperature, and adds manganese oxide (MnO 2 ) and molybdenum oxide (MoO 3 ) to the glass frit composition to compensate for valence during firing in a reducing atmosphere. The high temperature insulation resistance characteristic by the change with time is improved, and the insulation resistance (IR) characteristic at normal temperature is improved by forming a liquid insulation layer between grain boundaries. In the case of the addition of glass frit, the room temperature IR (insulation resistance at 25 ° C) and the high temperature IR (insulation resistance at 125 ° C) increase simultaneously up to 3wt%, but at higher temperatures, the room temperature IR tends to increase. Seems. Therefore, in general, the IR value is known to be related to the reliability, and it is not preferable to considerably reduce the high temperature IR, in view of the fact that the deterioration of the characteristic occurs especially when the high temperature IR value decreases.

본 발명에서 유리프릿(glass frit) 함량이 3wt% 까지는 품질계수 및 절연저항이 증가됨을 확인할 수 있는데, 이와 같은 결과는 유리프릿(glass frit)에 의한 입계의 손실보다는 유리프릿(glass frit)에 포함된 산화망간(MnO2), 산화몰리(MoO3)의 첨가에 의한 것으로 예상된다. 또한 유리프릿(glass frit) 제작시, 종래의 경우 산화망간(MnO2), 산화몰리(MoO3)등을 첨가물 단독으로 사용하는 경우가 대부분이나 본원발명에서는 유리프릿 첨가시 산화망간과 산화몰리를 동시에 첨가하여 혼합함으로써 첨가물의 균일성을 높이고자 하였다. In the present invention, it can be seen that the glass frit content up to 3wt% increases the quality coefficient and insulation resistance. Such a result is included in the glass frit rather than the loss of grain boundaries due to the glass frit. It is expected by the addition of manganese oxide (MnO 2 ) and molybdenum oxide (MoO 3 ). In addition, in the manufacture of glass frit, manganese oxide (MnO 2 ), molybdenum oxide (MoO 3 ), etc. are used as additives alone in the conventional case, but in the present invention, manganese oxide and molybdenum oxide are added when glass frit is added. Simultaneous addition and mixing were intended to increase the uniformity of the additives.

유리프릿(glass frit)의 조성에서도 종래에는 내환원성 유리프릿 조성으로 산화칼슘(CaO)-산화붕소(B2O3)-산화규소(SiO2)-산화리튬(Li2O)을 주 조성으로 이용하였으나, 본 발명의 경우, 상기 조성에 더하여 산화망간(MnO2), 산화몰리(MoO3)를 동시에 첨가한 결과 우수한 유전특성 및 소결특성을 나타내었다.In the composition of glass frit, the main composition mainly consists of calcium oxide (CaO) -boron oxide (B 2 O 3 ) -silicon oxide (SiO 2 ) -lithium oxide (Li 2 O). In the present invention, however, in addition to the above composition, manganese oxide (MnO 2 ) and molybdenum oxide (MoO 3 ) were added simultaneously, and showed excellent dielectric and sintering characteristics.

그리고, 소결온도를 낮추기 위해서는 액상소결을 하는 것이 일반적이며,유리프릿의 첨가에 의해 액성형성을 900도 이하에서 가능하도록 하였다.In order to lower the sintering temperature, liquid phase sintering is generally performed. The addition of glass frit allows liquid formation to be possible at 900 degrees or less.

이를 위하여 본 발명의 유리프릿에서는 MnO2와 MoO3를 각각, 8몰%와 4몰%로 고정하였을 경우, 20몰%≤CaO≤35몰%, B2O3는 30몰% 이하, 35몰%≤SiO2≤55몰%, Li2O는 15몰% 이하인 조성물로 하여 유리프릿의 융점을 1300∼1500℃ 범위로 조절하였다. 이렇게 성분을 제한한 것은 제한된 범위를 벗어나는 경우 액상 형성온도가 900도 이상이 되거나 유리프릿 제작시 흐름성이 없어 유리 제조공정상의 어려운 점이 있다. To this end, in the glass frit of the present invention, when MnO 2 and MoO 3 are fixed at 8 mol% and 4 mol%, respectively, 20 mol% ≦ CaO ≦ 35 mol%, and B 2 O 3 is 30 mol% or less and 35 mol The melting point of the glass frit was adjusted to a range of 1300 to 1500 ° C. using a composition having% ≦ SiO 2 ≦ 55 mol% and Li 2 O of 15 mol% or less. This limited component has a difficulty in the glass manufacturing process because the liquid formation temperature is more than 900 degrees or flowability when manufacturing the glass frit outside the limited range.

이하, 본 발명을 실시예를 통하여 보다 상세히 설명하기로 한다. Hereinafter, the present invention will be described in more detail with reference to Examples.

본 발명에서 이용되는 유리프릿은 산화망간(MnO2), 산화몰리(MoO3), 산화칼슘(CaO), 산화붕소(B2O3), 산화규소(SiO2)를 아래의 표 1과 같은 비율로 평량한 후 알루미나(Al2O3)볼을 이용하여 6시간 건식혼합한 후, 조성에 따라 백금 도가니를 이용하여 1300∼1500℃ 범위에서 0.5∼10 시간 용융한 후 급랭시켜 제조하였다. 제조된 유리프릿은 볼 밀 또는 다이노 밀을 이용하여 분말 크기(D50)를 0.5∼1.0㎛로 조절한 후 주조성에 3wt% 이하로 첨가하였다.The glass frit used in the present invention includes manganese oxide (MnO 2 ), molybdenum oxide (MoO 3 ), calcium oxide (CaO), boron oxide (B 2 O 3 ), and silicon oxide (SiO 2 ) as shown in Table 1 below. After the basis weight in a ratio and dry mixing for 6 hours using an alumina (Al 2 O 3 ) ball, using a platinum crucible according to the composition was melted for 0.5 to 10 hours in the range of 1300 ~ 1500 ℃ and prepared by quenching. The prepared glass frit was added to 3 wt% or less in castability after adjusting the powder size (D 50 ) to 0.5-1.0 μm using a ball mill or a dyno mill.

표 1은 각각의 유전체 조성물의 조성을 나타내었는데, 표 1에서의 *는 본 발명의 범위를 벗어나는 조성범위이다. 즉, CaZrO3, Ba5Nb4O15, CaTiO3, SrZrO3 및 유리프릿을 목적하는 조성이 되도록 평량한 후 그 원료들을 순수 물(DI water)을 용매로 하여 24 시간 습식혼합하였다. 습식 혼합한 원료는 건조하여 600∼900℃에서 하소한 후 다시 분쇄하여 분말 크기(D50)를 0.3∼0.8㎛가 되도록 준비하였다. Table 1 shows the composition of each dielectric composition, where * in Table 1 is a composition range outside the scope of the present invention. That is, CaZrO 3 , Ba 5 Nb 4 O 15 , CaTiO 3, SrZrO 3 and the glass frit were weighed to a desired composition, and then the raw materials were wet mixed for 24 hours using pure water (DI water) as a solvent. The wet mixed raw materials were dried, calcined at 600 to 900 ° C., and then ground again to prepare a powder size (D 50 ) of 0.3 to 0.8 μm.

준비된 분말에 PVB(Poly Vinyl Butyral) 및 톨루엔/에탄올 용매와 함께 지르코니아(ZrO2) 볼을 이용하여 볼밀한 후 슬러리(slurry)를 제조하였다. 상기 슬러리는 소정의 코팅 방식 (닥터 블레이드(doctor blade) 또는 Die-Coating)을 이용하여 3∼50㎛의 세라믹 그린시트(ceramic green sheet)를 형성하였다. 그린시트를 1 mm 두께로 여러 장 적층한 후 압착하여 디스크 형태의 시편을 준비하였으며, 이를 내환원성 분위기에서 소결 후 전극을 형성하여 유전 특성을 확인하였다.The prepared powder was ball milled using a zirconia (ZrO 2 ) ball with PVB (Poly Vinyl Butyral) and toluene / ethanol solvent to prepare a slurry. The slurry formed a ceramic green sheet having a thickness of 3 to 50 µm using a predetermined coating method (doctor blade or die-coating). Several sheets of green sheet were laminated to a thickness of 1 mm and pressed to prepare disk-shaped specimens, and the dielectric properties were confirmed by forming electrodes after sintering in a reducing resistance atmosphere.

Figure 112005050595980-pat00001
Figure 112005050595980-pat00001

한편, 도 1은 본 발명의 유전체 조성물로 만들어진 적층 세라믹 캐패시터를 각각 나타낸 단면도로서, 도시된 바와 같이 커패시터는 복수의 내부전극(2)이 적층된 세라믹 소체(1)와, 상기 세라믹 소체의 양측에 형성되어 외부로 다소 돌출된 내부전극과 연결된 외부전극(3)으로 이루어져 있다. 적층 칩 캐패시터의 제조는 3∼50㎛의 세라믹 그린시트 위에 0.1∼0.3um의 CaZrO3를 세라믹 공제로 사용한 니켈 페이스트(Ni paste)를 프린트하여 내부 전극을 형성하였으며, 전극패턴이 인쇄된 그린시트를 원하는 전기적 특성에 따라 적층한 후 압착하였고, 압착한 바를 절단하였다. 절단한 제품에서 유기물을 없애기 위하여 250∼350℃의 온도범위에서 바인더를 탈지(burn-out)한 후 환원분위기에서 1260∼1320℃의 범위에서 소결하였다.1 is a cross-sectional view showing a multilayer ceramic capacitor made of the dielectric composition of the present invention, respectively, and as shown in FIG. 1, a capacitor includes a ceramic body 1 in which a plurality of internal electrodes 2 are stacked, and both sides of the ceramic body. It consists of an external electrode (3) formed and connected to the inner electrode slightly protruding to the outside. In the manufacture of multilayer chip capacitors, an internal electrode was formed by printing a nickel paste using 0.1 to 0.3 μm of CaZrO 3 as a ceramic additive on a ceramic green sheet having a thickness of 3 to 50 μm. The laminate was pressed after lamination according to the desired electrical properties, and the pressed bars were cut. In order to remove organic matter from the cut products, the binder was burned out at a temperature in the range of 250 to 350 ° C., and then sintered in the range of 1260 to 1320 ° C. in a reducing atmosphere.

상기 소결한 제품에 외부전극을 형성하기 위하여 소결 칩을 연마하였으며, 연마 후 60∼100% 구형(spherical type)과 0∼40% 판상(flake type)의 구성비를 갖는 구리(Cu) 페이스트를 적용하여 외부 전극을 형성한 후, 환원 분위기에서 800∼900℃ 범위에서 외부전극을 소성하였다. The sintered chip was polished to form an external electrode on the sintered product, and after polishing, copper (Cu) paste having a composition ratio of 60 to 100% spherical type and 0 to 40% flake type was applied. After the external electrode was formed, the external electrode was calcined in the range of 800 to 900 ° C. in a reducing atmosphere.

상기 외부전극(3; Cu)을 형성한 후 납땜성 및 내부식성을 위하여 니켈 도금을 하고, 그 외부에 주석 도금을 하였다. After forming the external electrode 3 (Cu), nickel plating was performed for solderability and corrosion resistance, and tin plating was performed on the outside thereof.

적층 칩 캐패시터의 유전특성인 유전율과 품질 계수는 1MHz, 1Vrms, 25℃의 조건에서 측정하였으며, 용량 변화율은 -55∼125℃의 범위에서 측정하여 계산하였다. 절연 저항(insulated resistance)은 25℃(상온절연저항으로 칭함)와 125℃(고온 절연저항으로 칭함)의 두 온도에서 100V, 1분간 충전 후 "고 저항 측정기(HP사, 4329A, High Resistance Meter)"를 이용하여 측정하였다. The dielectric constant and quality factor, which are the dielectric properties of the multilayer chip capacitor, were measured under the conditions of 1 MHz, 1 V rms and 25 ° C., and the capacity change rate was calculated by measuring in the range of −55 to 125 ° C. Insulated resistance is 100V at two temperatures of 25 ° C (referred to as room temperature insulation resistance) and 125 ° C (referred to as high temperature insulation resistance) after charging for 1 minute. "High resistance meter (HP, 4329A, High Resistance Meter) Was measured using ".

이상의 결과를 표 2에 나타내었다.The above result is shown in Table 2.

Figure 112005050595980-pat00002
Figure 112005050595980-pat00002

표 2에서 보는 바와 같이, 본 발명에 따른 유전체 조성물은 유전율이 40∼70 정도의 높은 값을 나타내고, 품질계수도 대략 500을 상회하고 있어 우수한 유전특성을 보이고 있으며, 절연저항 특성은 상온 절연저항(25℃)이 1.00E+12 이상이고, 고온 절연저항(125℃)이 대략 1.00E+10을 상회하고 있으며, 또한 유전율의 온도계수도 ±300ppm/℃의 범위내에서 변화하고 있다. 이러한 사실로부터 본 발명의 유전체 조성물은 적층 칩 세라믹 캐패시터에 적용되는 종래의 유전체 재료를 대체 가능한 정도의 유전특성과 절연특성을 나타내는 것을 확인할 수 있다.As shown in Table 2, the dielectric composition according to the present invention exhibits a high dielectric constant of about 40 to 70, a quality factor of about 500, and shows excellent dielectric properties. 25 ° C) is 1.00E + 12 or higher, the high temperature insulation resistance (125 ° C) exceeds approximately 1.00E + 10, and the temperature coefficient of dielectric constant is also changed within a range of ± 300 ppm / ° C. From these facts, it can be seen that the dielectric composition of the present invention exhibits dielectric and insulating properties that can replace conventional dielectric materials applied to multilayer chip ceramic capacitors.

이상으로, 본 발명에 따르면, Cu 또는 Ni 등과 같은 저가의 금속을 내부전극으로 사용하여 동시 소성할 수 있을 뿐 아니라 유전율이나 유전율의 온도계수 등과 같은 유전특성과 전기 절연특성이 우수하여 적층 칩 세라믹 캐패시터에서 적용시 유전체의 두께를 얇게 할 수 있는 온도보상용 내환원성 유전체 세라믹 조성물이 될수 있다.As described above, according to the present invention, a low-cost metal such as Cu or Ni, etc. can be used for internal firing, as well as excellent dielectric and electrical insulation properties, such as dielectric constant and dielectric constant temperature coefficient, multilayer chip ceramic capacitors. It can be a temperature-compensating, reducing-resistant dielectric ceramic composition that can reduce the thickness of the dielectric when applied in.

이상에서는 본 발명을 특정의 바람직한 실시예를 예로 들어 도시하고 설명하였으나, 본 발명은 상기한 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.In the above, the present invention has been illustrated and described with reference to specific preferred embodiments, but the present invention is not limited to the above-described embodiments and the general knowledge in the technical field to which the present invention pertains without departing from the spirit of the present invention. Various changes and modifications will be made by those who possess.

Claims (3)

주성분과 부성분으로 구성되는 온도보상용 내환원성 세라믹 유전체 조성물로서, A temperature compensation reduction ceramic dielectric composition composed of a main component and a subcomponent, 상기 주성분은, Ba5Nb4O15의 몰분율을 x라 할때, 일반식 (1-x) CaZrO3 - x Ba5Nb4O15으로 표시되며, 상기 x는 0.07≤x≤0.20 범위의 값을 가지며,The main component, Ba 5 Nb 4 O 15 when referred to the mole fraction of x, formula (1-x) CaZrO 3 - x Ba 5 Nb 4 O 15 is shown, the x value is in the range 0.07≤x≤0.20 Has, 상기 부성분은 티탄산칼슘, 지르콘산 스트론튬, 그리고 CaO-B2O3-SiO2-Li2O-MnO2-MoO3계 유리프릿 중 적어도 어느 하나를 포함하며, 상기 주성분에 대하여, 티탄산칼슘, 지르콘산 스트론튬 및 상기 유리프릿의 첨가량은, 각각 5wt% 이하, 10wt% 이하, 및 3wt% 이하인 것을 특징으로 하는 온도보상용 내환원성 세라믹 유전체 조성물.The minor component includes at least one of calcium titanate, strontium zirconate, and CaO-B 2 O 3 -SiO 2 -Li 2 O-MnO 2 -MoO 3 -based glass frit, with respect to the main component, calcium titanate and zircon The amount of the strontium acid and the glass frit added is 5 wt% or less, 10 wt% or less, and 3 wt% or less, respectively. 제 1 항에 있어서,The method of claim 1, 상기 유리프릿의 조성은 MnO2와 MoO3를 각각, 8몰%와 4몰%로 고정하였을 경우,When the composition of the glass frit is fixed to MnO 2 and MoO 3 , 8 mol% and 4 mol%, respectively, 20몰%≤CaO≤35몰%, B2O3는 30몰% 이하,20 mol% ≤ CaO ≤ 35 mol%, B 2 O 3 is 30 mol% or less, 35몰%≤SiO2≤55몰%, Li2O는 15몰% 이하,35 mol% ≤ SiO 2 ≤ 55 mol%, Li 2 O is 15 mol% or less, 인 것을 특징으로 하는 온도보상용 내환원성 세라믹 유전체 조성물.A temperature-compensating, reduction-resistant ceramic dielectric composition, characterized in that. 청구항 1의 세라믹 유전체 조성물을 유전체 재료로 사용하는 것을 특징으로 하는 적층 칩 세라믹 캐패시터.A multilayer chip ceramic capacitor, comprising using the ceramic dielectric composition of claim 1 as a dielectric material.
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KR100359721B1 (en) 1999-05-07 2002-11-04 (주)세렉트론 Dielectric Ceramic Compositions able to be cofired with metal

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100359721B1 (en) 1999-05-07 2002-11-04 (주)세렉트론 Dielectric Ceramic Compositions able to be cofired with metal

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