KR100638998B1 - Lsi circuit - Google Patents

Abstract

The present invention relates to a semiconductor circuit for limiting the increase in off-leak current of the transistor due to variation in the threshold voltage of the transistor.

In the circuit block 20, the source of the PM0S transistors QP2 and QP4 which are turned off in the standby state is connected to the third power supply line Vcci. In the circuit block 20, the NMOS transistors QNl, QN3, QN5 which are turned off in the standby state are connected to the source of the fourth power supply line Vssi. Each voltage of the third and fourth power lines Vcci and Vssi is controlled to be changed by a power supply control circuit 10 according to a change in the threshold voltage of the transistor, so that the gate-source voltage Vgs of the transistor is changed. And the difference voltage Vgs-Vt of the threshold voltage Vt of the transistor can be held at a constant value. As a result, the off-leak current of the transistor in the standby state of the circuit block 20 is small and Limited to a certain value.

Description

Semiconductor Circuits {LSI CIRCUIT}

The present invention relates to the improvement of semiconductor circuits, in particular semiconductor circuits of high speed and low power consumption composed of fine elements.

Recently, with the rapid spread of portable devices and the like, there is a demand for lower power consumption of LSI. In order to realize a low power consumption type LSI, a decrease in the internal power supply voltage is progressing. However, a decrease in the internal power supply voltage causes a rapid decrease in the operation speed of the circuit. As an effective method for solving this problem, the low threshold value (Low-Vt) of a transistor is mentioned. However, lowering the transistor makes it possible to increase the current flowing through the transistor and to increase the operating speed. However, a disadvantage arises in that the off-leak current in standby or active increases. In addition, when an imbalance occurs in the threshold voltage of the transistor due to variations in the manufacturing process of the transistor, a new problem arises that the imbalance width greatly affects a small threshold voltage.

Regarding the problem of an increase in the off-leakage current of the standby, for example, as described in Japanese Patent Application Laid-open No. Hei 6-208790, the direction in which the leakage current decreases the potential of the source node with respect to the transistor blocked in standby. There is a technique of reducing the leakage current flowing in the circuit during standby by changing to.

However, in the above conventional technology, since the potential of the source note of the transistor is changed assuming that the threshold voltage of the transistor is a constant value, the threshold of the transistor is changed according to the variation of the manufacturing process or the temperature change in the use of the product. The imbalance of the value voltage is generated, and the larger the threshold voltage, the slower the operation speed of the circuit, while the smaller the threshold voltage, the greater the problem that the off-leak current of the transistor increases.

It is a first object of the present invention to provide a semiconductor circuit which suppresses an increase in leakage current or a decrease in operating speed due to an imbalance in a threshold voltage of a transistor.

Moreover, the 2nd objective of this invention is providing the semiconductor circuit which can reduce the leakage current of a transistor not only in standby of a circuit but also in an active state.

In order to achieve the first object, in the present invention, the leakage current of the transistor is proportional to the difference voltage Vgs-Vt of the gate-source voltage Vgs of the transistor and the threshold voltage Vt of the transistor. Therefore, by switching the gate-source voltage Vgs as the threshold voltage Vt varies, that is, by changing the source voltage (power supply voltage) of the transistor, the off-leak current of the transistor is made smaller and constant. Shall be maintained.

In addition, in order to achieve the second object, the present invention is to forcibly control a part of the period in a state of low power consumption when the circuit is in an active state.

That is, the semiconductor circuit of the invention according to claim 1 is a semiconductor circuit that is switched between an active state and a standby state, comprising: a transistor to be cut off in the standby state, a power supply line connected to the transistor, and a voltage of the power supply line It characterized in that it comprises a power supply control circuit for controlling to change according to the variation of the threshold voltage of the transistor.

According to a second aspect of the present invention, in the semiconductor circuit according to the first aspect, the power supply control circuit controls to change the voltage of the power supply line in response to a change in a threshold voltage of the transistor according to a change in a manufacturing process of the transistor. Characterized in that.

According to a third aspect of the invention, in the semiconductor circuit according to the first aspect, the power supply control circuit includes a threshold voltage detection transistor that monitors the threshold voltage of the transistor.

According to a fourth aspect of the present invention, in the semiconductor circuit of the first aspect, the power supply control circuit includes a difference voltage (Vgs-Vt) between a gate-source voltage (Vgs) of the transistor and a threshold voltage (Vt) of the transistor. The voltage of the power supply line is changed so that) always becomes a constant value.

According to a fifth aspect of the present invention, in the semiconductor circuit according to the first aspect, the reference voltage level of the power supply line is set to a different voltage value in the active state and the standby state.

A semiconductor circuit of the invention according to claim 6 includes a circuit block connected to first and second power lines, third and fourth power lines, first, second, third and fourth power lines, and the circuit block. PMOS transistors and NMOS transistors that are built-in and connected to either one of the third and fourth power supply lines, and the voltage of the third power supply line is adapted to the variation of the threshold voltage of the PMOS transistor based on the voltage of the first power supply line. And a power supply control circuit for changing the voltage of the fourth power supply line in accordance with the variation of the threshold voltage of the NMOS transistor on the basis of the voltage of the second power supply line.

According to a seventh aspect of the present invention, in the semiconductor circuit of the sixth aspect, the power supply control circuit has a voltage difference between a gate-source voltage of the PMOS transistor and a threshold voltage of the PMOS transistor. The voltage of the fourth power supply line is changed so as to be always a constant value, and the voltage difference between the gate-source voltage of the NMOS transistor and the threshold voltage of the NMOS transistor is always changed to be a constant value.

According to an eighth aspect of the invention, in the semiconductor circuit of the sixth aspect, the reference voltage levels of the third and fourth power lines are set to different voltage values in the active state and the standby state, respectively.

A semiconductor circuit according to the ninth aspect of the present invention is a semiconductor circuit having a circuit block that is switched between an active state and a standby state, wherein a low power consumption circuit that makes the semiconductor circuit lower power consumption than the active state when in the standby state. And a pseudo standby circuit for forcing a part of a period of the active state during the active state into a pseudo standby state such as a standby state in which power consumption is lowered by the low power consumption circuit. .

According to a tenth aspect of the present invention, in the semiconductor circuit according to the ninth aspect, the circuit block includes a transistor to cut off in the standby state, a power line connected to the transistor is provided, and the low power consumption circuit is used in the standby state. And a power supply control circuit for controlling the voltage of the power supply line to change in response to a change in the threshold voltage of the transistor.

In the semiconductor circuit according to claim 10, the power supply control circuit includes a difference voltage between a gate-source voltage Vgs of the transistor of the circuit block and a threshold voltage Vt of the transistor. The voltage of the power supply line is changed so that (Vgs-Vt) is always a constant value.

According to a twelfth aspect of the present invention, in the semiconductor circuit of the ninth, tenth, or eleventh aspect, the pseudo standby circuit comprises: a signal generation circuit for generating a set signal; And a set circuit forcing the circuit block into the pseudo standby state when the set signal is no longer received.

According to a thirteenth aspect of the invention, in the semiconductor circuit of the ninth aspect, the semiconductor circuit according to the ninth aspect includes a signal holding circuit which holds a value of a signal output from the circuit block immediately before the pseudo standby state. It is done.

The invention according to claim 14 is the semiconductor circuit according to claim 13, wherein the signal holding circuit generates a latch signal for holding an output signal of the circuit block when the signal holding circuit is in the active state; And a latch circuit for latching an output signal of the circuit block in response to a latch signal of the generation circuit.

According to a fifteenth aspect of the present invention, in the semiconductor circuit according to the tenth aspect, the reference voltage level of the power supply line is set to a different voltage value in the active state and the standby state.

In the semiconductor circuit according to claim 16 or 17, in the semiconductor circuit according to claim 12 or 14, the signal generation circuit inputs an input signal to the circuit block, and generates a set signal or a latch signal based on the input signal. Characterized in that.

With the above arrangement, in the invention of claims 1 to 8, the voltage of the power supply line connected to the transistor to be cut off in the standby state is changed in accordance with the variation of the threshold voltage of the transistor, so that the threshold voltage of the transistor is changed in the manufacturing process. Even if it is fluctuated due to the fluctuation, the gate-source voltage of the transistor can be kept at a constant value, and therefore the off-leak current of the transistor in the standby state can be suppressed to a small and small value.

In the inventions described in claims 9 to 17, when the circuit is in the active state, a part of the period of the active state is forcibly brought to a pseudo standby state such as a standby state of low power consumption by the pseudo standby circuit. Even in a state, low power consumption can be achieved.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

(Example)

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)

1 shows a semiconductor circuit of a first embodiment according to the present invention.

In Fig. 1, Vcc is, for example, a first power supply line having a voltage of 1.0V, Vss is a second power supply line which is a ground line, Vcci is a third power supply line, and Vssi is a fourth power supply line. CS is a chip activation signal, INV1-INV5 is an inverter circuit, Comprising: One PMOS transistor QP1-QP5 and one NMOS transistor QN1-QN5 are connected in series, respectively.

Numeral 20 is a circuit block, which is composed of a logical product circuit 25 that takes an AND of the input signal IN and the chip activation signal CS, and a circuit in which inverter circuits INV1 to INV5 are cascaded. When the chip activation signal CS is at a high level, the AND circuit 25 inputs the input signal IN to the first inverter circuit INV1 to make the circuit block 20 active, while the chip When the activation signal CS is at the low level, the input signal IN is prevented from being input to the inverter circuit INV1 at the first stage, and the circuit block 20 is placed in the standby state.

In the present embodiment, the inverter circuits INV1 to INV5 are described as an example, but any logic circuit composed of at least an NMOS transistor or a PMOS transistor may be used.

In the inverter circuits INV1 to INV5 of each stage in the circuit block 20, the output of the AND circuit 25 when the circuit block 20 is in a standby state, that is, when the chip activation signal CS is at a low level. Becomes low level and the input signals of the inverter circuits INV1, INV3, INV5 of the first, third, and fifth stages are at the low level, while the inverter circuits INV2, INV4 of the second and fourth stages are low. ) Input signal becomes high level. Therefore, in the standby state, the NMOS transistors QN1, QN3, QN5 and the PMOS transistors QP2, QP4 are turned off. In order to change the gate-source voltage Vgs of these NMOS transistors QN1, QN3, and QN5, a fourth power supply line Vssi is connected to the source of these NMOS transistors. In order to change the gate-source voltage Vgs of these PMOS transistors QP2 and QP4, a third power supply line Vcci is connected to the source of these PMOS transistors.

The power supply control circuit 10 is provided to change the voltage of the third power line Vcci and the voltage of the fourth power line Vssi. The power supply control circuit 10 inputs the first power supply line Vcc, the second power supply line Vss, and the chip activation signal CS, and the threshold voltage Vt of the transistors QP1 to QP5 and QN1 to QN5. ) And the voltages of the third power line Vcci and the fourth power line Vssi according to the standby state or the active state determined by the chip activation signal CS.

3 shows a voltage waveform diagram of the third power supply line Vcci and the fourth power supply line Vssi by the power supply control circuit 10. As shown in FIG. 3A, the reference voltage level of the third power supply line Vcci is controlled to be equal to the voltage of the first power supply line Vcc in the active state, and in order to reduce the leakage current during standby. The reference voltage level is lower than the reference voltage level in the active state. On the other hand, the reference voltage level of the fourth power supply line Vssi is controlled to be equal to the voltage of the second power supply line Vss in the active state, and is less than the reference voltage level in the active state in order to reduce the leakage current during standby. The voltage is controlled to a high reference voltage level. With the above configuration, the gate-source voltage Vgs of the transistors QN1, QN3, QN5, QP2, and QP4 that are turned off in the standby state is smaller than the gate-source voltage in the active state. ) And the difference voltage (Vgs-Vt) between the threshold voltage Vt of the transistor also becomes a small value. Therefore, the leakage current of the transistor flowing in proportion to the difference voltage also decreases. As a result, the amount of leakage current flowing in this standby state is smaller than that of the active state, resulting in low power consumption.

As described above, the fourth power supply line Vssi is connected to the inverter circuits INV1, INV3, and INV5 whose inputs are at the low level in the standby state. The voltage of the fourth power supply line Vssi is due to the variation in the manufacturing process of the threshold voltage Vtn of the NMOS transistors QN1 to QN5 in the circuit block 20 as shown in FIG. When larger than a desired value, it is controlled by the power supply control circuit 10 so that the threshold voltage may become smaller than the reference voltage level shown by a solid line. As a result, in each of the active state and the standby state, as the threshold voltage Vtn of the NMOS transistors QN1 to QN5 increases, the gate-source voltage Vgs of the NMOS transistor increases, so that the gate-of the NMOS transistor The value of the difference Vgs-Vtn between the source-to-source voltage Vgs and the threshold voltage Vtn is kept constant, thereby suppressing the leakage current in the standby state while making the operating speed in the active state constant. The effect can be obtained.

Similarly, as shown in FIG. 3B, the threshold voltage Vtn of the NMOS transistors QN1 to QN5 constituting the inverter circuit in the circuit block 20 is smaller than the desired value due to variations in the manufacturing process. If so, the voltage of the fourth power supply line Vssi is controlled by the power supply control circuit 10 so that the voltage of the fourth power supply line Vssi is increased by the amount smaller than the reference level. As a result, in the active state and the standby state, as the threshold voltage Vtn of the NMOS transistors QN1 to QN5 decreases, the gate-source voltage Vgs of the NMOS transistor decreases, and thus the Vgs- of the NMOS transistor. The value of Vtn is kept constant, whereby the leakage current is kept small in the standby state, while the operating speed of the inverter circuit becomes constant during active operation, and the improvement in operating performance can be achieved.

In the semiconductor circuit of this embodiment, the threshold voltage correction is not particularly performed with respect to the PMOS transistors QP1, QP3, and QP5 with respect to the inverter circuits INV1, INV3, and INV5 whose inputs are at a low level in the standby state. However, this means that in standby mode, the leakage currents of the NMOS transistors QN1, QN3, and QN5 determine the leakage current of the semiconductor circuit, and when active, the operating speed (on current) of these NMOS transistors determines the operating speed of the semiconductor circuit. This is because the circuit configuration to determine is taken.

On the other hand, as described above, the third power supply line Vcci is connected to the inverter circuits INV2 and INV4 at which the input becomes high in the standby state. The voltage of the third power supply line Vcci is due to the variation in the manufacturing process of the threshold voltage Vtp of the PMOS transistors QP1 to QP5 in the circuit block 20 as shown in FIG. When larger than a desired value, it is controlled by the power supply control circuit 10 so that the threshold voltage may become larger by the amount larger than the reference voltage level shown by a solid line. On the contrary, when the threshold voltage Vt of the PMOS transistors QP1 to QP5 is smaller than the desired value, the power supply control circuit 10 is made smaller than the reference voltage level indicated by the solid line by the smaller amount. Is controlled by As a result, in each of the active state and the standby state, the gate-source voltage Vgs of the PMOS transistor also changes as the threshold voltage Vtp of the PMOS transistors QP1 to QP5 varies. The value of the difference between the gate-source voltage Vgs and the threshold voltage Vtp (Vgs-Vtp) is kept constant, whereby the operating speed in the active state is kept constant while suppressing the leakage current in the standby state. Can get the effect.

Next, a specific example of the power supply control circuit 10 is shown in FIG. The power supply control circuit 10 may have any circuit configuration as long as the operation described above is satisfied. The power supply control circuit 10 shown in FIG. 4 includes two threshold detection circuits 70a and 70b and two voltage generation circuits 80a and 80b for generating the voltage of the third power supply line Vcci. It consists of two threshold detection circuits 100a and 100b and two voltage generation circuits 110a and 110b for generating voltage of the power supply line Vssi. The threshold detection circuits 70a and 100a and the voltage generation circuits 80a and 110a are active, and the threshold detection circuits 70b and 100b and the voltage generation circuits 80b and 110b are for standby. In FIG. 4, CS is a chip activation signal for switching between standby and active states of a semiconductor circuit as in FIG. 1, and is used for standby when the chip activation signal CS is at a low level, and the chip activation signal CS is at a high level. Is switched to active.

The basic operation of the power supply control circuit 10 generates a potential proportional to the threshold voltages of the transistors QP1 to QP5 and QN1 to QN5 by the threshold detection circuits 70a, 70b, 100a, and 100b. The voltage is held by the voltage generating circuits 80a, 80b, 110a, and 110b and outputs the potential as the voltage of the third power line Vcci or the voltage of the fourth power line Vssi. Hereinafter, the operation will be described in detail.

In FIG. 4, the active threshold detection circuit 70a and the voltage generation circuit 80a for controlling the voltage of the third power supply line Vcci will be described. The node ref1 of the threshold detection circuit 70a will be described. The potential of is determined by the ratio of the threshold voltages of the two resistors R1 and R2 and the threshold voltage detection transistor QP1 in the threshold detection circuit 70a. The threshold voltage detection transistor QP1 is a transistor manufactured in the same process as the transistors QP1 to QP5 and QN1 to QN5 of the circuit block 20. The potential of the node ref1 rises when the threshold voltage of the threshold voltage detection transistor QP1 rises and decreases when it goes down. The values of the resistors R1 and R2 are selected such that the potential of the node ref1 at room temperature becomes the reference level of the voltage of the third power supply line Vcci at the time of activation shown in Fig. 3A. The voltage generating circuit 80a is constituted by the current mirror circuit 120 and the charging transistor QP4, and the third power supply line is controlled by controlling the on / off of the charging transistor QP4 by the current mirror circuit 120. The voltage of Vcci is maintained at the same potential as that of the node ref1. That is, when the threshold voltage of the threshold voltage detection transistor QP1 increases, the potential of the node ref1 increases, and when the threshold voltage decreases, the potential of the node ref1 also drops, and accordingly, the third power line Vcci The voltage will also change.

Also, in the threshold detection circuit 70b for standby, the values of the two resistors R1 'and R2' are set to the potential of the node ref1 'with the voltage of the third power supply line Vcci in standby as the reference potential. By selecting so as to be the reference potential of the voltage of the third power supply line Vcci in standby, the voltage of the third power supply line Vcci in standby can be generated by the voltage generating circuit 80b. The two threshold detection circuits 100a and 100b and the two voltage generation circuits 110a and 110b generating the voltage of the fourth power supply line Vssi are the same as described above, and thus description thereof will be omitted.

Therefore, by embedding the power supply control circuit 10 shown in FIG. 4 into the chip, even if the threshold voltage of the transistor in the circuit block 20 becomes a voltage value other than the desired value according to the variation of the manufacturing process, the third power supply line Vcci ) And the voltage of the fourth power supply line Vssi can be changed to a voltage value according to the changed threshold voltage, and at the same time as the temperature change when the circuit block 20 is used, Even if the threshold voltage fluctuates, the voltage of the third power source line Vcci and the voltage of the fourth power source line Vssi can be satisfactorily changed in response to this fluctuation.

In addition, in this embodiment, the power supply control circuit 10 including the threshold voltage detection transistor QP1 is provided to respond to variations in the threshold voltage of the transistor due to temperature change when the circuit block 20 is used. The voltage of the third power supply line Vcci and the voltage of the fourth power supply line Vssi are changed. In addition, for example, the threshold voltages of the transistors embedded in the chips are measured in advance for each chip, and the information on the threshold voltages is measured. The voltage of the third power supply line Vcci and the voltage of the fourth power supply line Vssi may be controlled based only on. In this case, it is not possible to control the power supply voltage corresponding to the variation of the threshold voltage according to the temperature change.

The effect of the semiconductor circuit of this embodiment is shown in FIG. 2 is a distribution diagram in which the leakage current normalized on the horizontal axis is taken, and the number of chips is taken on the vertical axis. The point at which the standardized leakage current is "1" is that the operating speed of the circuit and the leakage current flowing are good quality chips traded off. At a value smaller than the point of "1", the transistor has a large threshold voltage and a small leakage current, but a low operating speed. On the other hand, a value larger than the point of "1" is a smaller threshold voltage of the transistor and a higher operating speed. Leakage current is a big chip. As shown in Fig. 2, in the conventional case where the power supply control circuit 10 of the present embodiment is not used, the leakage current imbalance is large, whereas when the power supply control circuit 10 of the present embodiment is used, Imbalance is suppressed small. This is the effect of this embodiment in that the value of the voltage Vgs-Vt is kept constant. It is understood that the operating speed is also stabilized along with the suppression of the leakage current.

(2nd Example)

Next, a second embodiment of the present invention will be described.

FIG. 5 shows a semiconductor circuit of a second embodiment of the present invention, and FIG. 6 shows an operation timing chart of the semiconductor circuit of FIG. In the first embodiment, the leakage current during standby is reduced, but in the present embodiment, the leakage current is also reduced during active in addition to standby.

The semiconductor circuit of FIG. 5 includes a power supply control circuit 10, first to fourth power supply lines Vcc, Vss, Vcci, and Vssi, and a circuit block 30. The power supply control circuit (low power consumption circuit) 10 adopts the same configuration as the power supply control circuit 10 shown in Fig. 1 of the first embodiment. In addition, the circuit block 30 is comprised by the sub circuit block 40 which consists of an NMOS transistor and a PMOS transistor, the set circuit 50, and the latch circuit 60. As shown in FIG. The power supply control circuit 10 is controlled by the CS signal. In addition, the set circuit 50 is composed of an AND circuit, input signal IN1, the SET signal SET, and the chip activation signal CS are inputted to take an AND of these, and the resultant signal is sub-block. Output to (40). The latch circuit 60 is controlled by the latch signal LAT, and latches the output signal from the output node node1 of the sub circuit block 40, and outputs the latched signal from the output terminal OUT. do. 70 is a SET and LAT signal generation circuit (signal generation circuit) for inputting an input signal IN1 and generating a set signal SET and a latch signal LAT based on the input signal IN1.

Hereinafter, the operation of the semiconductor circuit of this embodiment will be described with reference to FIGS. 5 and 6.

In the present semiconductor circuit, the circuit block 30 is controlled in the active state and the standby state by the chip activation signal CS. The input signal IN1 and the set signal SET are input to the input terminal of the set circuit 50 while the chip activation signal CS is at a high level and the circuit block 30 is in an active state. The latch signal LAT is input to 60.

Now, when the set signal SET is at the low level, the output of the set circuit 50 is fixed at the low level regardless of the state of the chip activation signal CS, and the circuit block 30 is in the standby state. In order to suppress the leakage current in this standby state to a predetermined value, the voltage levels of the third and fourth power supply lines Vcci and Vssi are controlled in the power supply control circuit 10 as described in the first embodiment. When the circuit block 30 is in the active state, the MOS transistors QP1 and QN2 when the input signals of the inverter circuits INV1, INV3, INV5 are at a high level and the input signals of the other inverter circuits INV2, INV4 are at a low level. Since leakage current flows to QP3, QN4, and QP5, the leakage current in this active state cannot be suppressed only by the structure of the sub circuit block 40. FIG.

On the other hand, if the input signal IN1 is input to the set circuit 50 when the set signal SET is at the high level when the chip activation signal CS is at the high level, the input signal IN1 is set to the set circuit 50. It is input to the sub circuit block 40 through. The signal input to the sub circuit block 40 propagates in the sub circuit block 40, changes the state of the internal node node1, and is input to the latch circuit 60. The signal input to the latch circuit 60 is latched by the latch circuit 60 only when the latch signal LAT becomes high level, and the voltage of the output terminal OUT is a waveform as shown in FIG. Becomes By latching the signal in the latch circuit 60, the latch circuit 60 also occurs when the set signal SET of the set circuit 50 transitions from high to low and the output of the set circuit 50 is forcibly changed to the low level. ) Will not change output.

As described above, in the semiconductor circuit of the present embodiment, when the set signal is high level in the situation where the chip activation signal CS is at a high level, the sub circuit block 40 becomes active, but when the set signal becomes low level, the sub circuit block ( 40 is in a standby state, and the internal node node1 is fixed at a low level. Therefore, when the period of the "H" level of the set signal SET is set to be shorter than the period of the "H" level of the input signal IN1, a part of the period in which the sub circuit block 40 is in the active state is forcibly added. It can be made into a standby state. Therefore, the pseudo standby circuit 80 is constituted by the set circuit 50 and the SET and LAT signal generation circuits 70. Even in the period of the pseudo standby state, the output signal of the sub circuit block 40 is latched by the latch circuit 60, so that the sub circuit block 40 is apparently in an active state. The latch circuit 60 and the SET and LAT signal generation circuits 70 constitute a signal holding circuit 90 which holds the value of the output signal of the sub circuit block 40 in the pseudo standby state.

Since the pseudo standby state is the same state as the standby state, as described in the first embodiment, the transistors constituting the subcircuit block 40 are turned off during the active standby state of the subcircuit block 40 as described in the first embodiment. It is possible to suppress the leakage current less and to suppress the increase in the current consumption in the active state.

7 shows a specific configuration of the SET and LAT signal generation circuit 70. In Fig. 7, the SET and LAT signal generation circuit 70 inputs an input signal IN1 to the set circuit 50, detects the "H" input of the input signal IN1, and detects the set signal SET and This circuit generates a latch signal LAT.

8 shows an operation timing chart of the SET and LAT signal generation circuits 70. An internal configuration of the SET and LAT signal generation circuit 70 of FIG. 7 will be described using the timing chart of FIG. 8. In Fig. 7, 80 and 90 are delay circuits constituted by an inverter chain, and control timing of signals at each node N1, N2, N5. The delay circuit 80 is an odd number of inverters, and the delay circuit 90 is composed of an even number of inverters, respectively. The nodes N1 and N2 are output terminals of the odd-numbered inverters counting from the input terminal NO of the input signal IN1.

When the input signal IN1 is input to the node N0, a signal delayed by the time a and the time b from the input signal IN1 is propagated to the nodes N1 and N2, respectively. Here, the two times a and b are adjusted by the number of stages of the inverter of the delay circuit 80. The NAND circuit 150 generates pulses of the "L" level in the period a, and the pulses are inverted by the inverter INV1. As a result, the set signal SET which is the "H" level in the period a. ) Is generated.

The NAND circuit 151 and the NOR circuit 152 generate pulses having a width of time b at the nodes N3 and N4, respectively, and the NOR circuit 153 outputs the NAND circuit 151. And an output in which the output of the NOR circuit 152 is inverted by the inverter INV2, and the output signal becomes a latch signal LAT via the delay circuit 90. Here, the timing of the latch signal LAT can be adjusted by the number of stages of the inverter of the delay circuit 90. The pulse generated by the NAND circuit 151 among the latch signals LAT is a signal for latching the pulse of the output node node1 of the sub circuit block 40, and the pulse generated by the NOR circuit 152 is latched. This is a signal for resetting the potential of the output node OUT of the circuit 60.

It is possible to automatically generate the operation timing of the set circuit 50 and the latch circuit 60 by the SET and LAT signal generation circuits 70 based on the input signal IN1, and the input signal IN1 does not change. If not, the signal generation circuit 70 does not operate, and further lower power consumption can be achieved. In addition, as long as this SET and LAT signal generation circuit 70 shown in FIG. 7 performs the same operation, what kind of structure may be sufficient.

As described above, according to the semiconductor circuit of the invention of claims 1 to 8, since the voltage of the power supply line connected to the transistor to be cut off in the standby state is changed in accordance with the variation of the threshold voltage of the transistor, the threshold value of the transistor. Even if the voltage fluctuates due to variations in the manufacturing process, the gate-source voltage of the transistor can be held at a constant value, and therefore the off-leak current of the transistor in the standby state can be suppressed to a small and small value. Effect.

According to the semiconductor circuit of the invention of claims 9 to 17, when the circuit is in an active state, a partial standby period of the active state is forcibly performed by a pseudo standby circuit such as a standby state such as a standby state of low power consumption. In this case, it is possible to achieve low power consumption even in the active state.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the present invention as set forth in the appended claims.

1 is a diagram showing a semiconductor circuit of a first embodiment of the present invention.

Fig. 2 is a distribution diagram of leak current in the semiconductor circuit of the first embodiment of the present invention.

3A is an explanatory diagram of reference levels of voltages of the third and fourth power supply lines of the semiconductor circuit of the first embodiment of the present invention.

Fig. 3B is an explanatory diagram of control for changing the voltage Vssi of the fourth power supply line.

FIG. 3C is an explanatory diagram of control for changing the voltage Vcci of the third power supply line. FIG.

4 is a diagram showing an internal configuration of a power supply control circuit included in the semiconductor circuit of the first embodiment of the present invention.

Fig. 5 shows the semiconductor circuit of the second embodiment of the present invention.

Fig. 6 is a diagram showing operation timings of the semiconductor circuit of the second embodiment of the present invention.

Fig. 7 is a diagram showing the internal structure of a SET and LAT signal generation circuit included in the semiconductor circuit of the second embodiment of the present invention.

Fig. 8 is a diagram showing operation timings of the semiconductor circuit of the second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

QN1 to QN5: NMOS transistor QP1 to QP5: PMOS transistor

Vcc: first power line Vss: second power line

Vcci: third power line Vssi: fourth power line

10: power supply control circuit (low power consumption circuit)

QP1: Transistor for threshold voltage detection

IN1: Input signal CS: Chip enable signal

SET: Set signal LAT: Latch signal

20, 30: circuit block 40: sub circuit block

50: set circuit 60: latch circuit

70: SET, LAT signal generation circuit (signal generation circuit)

70a, 70b, 100a, 100b: threshold detection circuit

80: pseudo standby circuit

80a, 80b, 110a, 110b: voltage generating circuit

90: signal holding circuit

Claims (17)

A semiconductor circuit that is switched between an active state and a standby state, A transistor blocked when in the standby state; A power supply line connected to the transistor, And a power supply control circuit for controlling the voltage of the power supply line to change in response to a change in a threshold voltage of the transistor. The method of claim 1, The power supply control circuit, And controlling the voltage of the power supply line to change in response to a change in a threshold voltage of the transistor according to a change in a manufacturing process of the transistor. The method of claim 1, The power supply control circuit, And a threshold voltage detection transistor for monitoring the threshold voltage of the transistor. The method of claim 1, The power supply control circuit, And the voltage of the power supply line is varied so that the difference voltage (Vgs-Vt) between the gate-source voltage (Vgs) of the transistor and the threshold voltage (Vt) of the transistor is always a constant value. The method of claim 1, And the reference voltage level of the power line is set to a different voltage value in the active state and the standby state. First and second power lines, The third and fourth power lines, A circuit block connected to the first, second, third and fourth power lines; A PMOS transistor and an NMOS transistor embedded in the circuit block and connected to either one of the third and fourth power supply lines; The voltage of the third power line is changed in accordance with the variation of the threshold voltage of the PMOS transistor based on the voltage of the first power line, and the voltage of the fourth power line is referenced based on the voltage of the second power line. And a power supply control circuit for changing in accordance with the variation of the threshold voltage of the NMOS transistor. The method of claim 6, The power supply control circuit, The voltage of the third power line is changed so that the difference voltage between the gate-source voltage of the PMOS transistor and the threshold voltage of the PM0S transistor is always a constant value, and the voltage of the fourth power line is changed to the gate- of the MMOS transistor. And a voltage difference between the source voltage and the threshold voltage of the NMOS transistor so that the voltage is always a constant value. The method of claim 6, The reference voltage levels of the third and fourth power supply lines are set to different voltage values in the active state and the standby state, respectively. A semiconductor circuit having a circuit block switched between an active state and a standby state, A low power consumption circuit for making the semiconductor circuit lower in power consumption than the active state in the standby state; And a pseudo standby circuit for forcing a part of the period of the active state when the active state is in a pseudo standby state such as a standby state brought to low power consumption by the low power consumption circuit. Semiconductor circuits. The method of claim 9, The circuit block has a transistor for blocking in the standby state, and a power supply line connected to the transistor is provided. The low power consumption circuit, And a power supply control circuit for controlling the voltage of the power supply line to change in response to a change in a threshold voltage of the transistor when in the standby state. The method of claim 10, The power supply control circuit, The voltage of the power supply line is changed so that the difference voltage Vgs-Vt between the gate-source voltage Vgs of the transistor of the circuit block and the threshold voltage Vt of the transistor is always a constant value. Semiconductor circuits. The method according to any one of claims 9, 10 and 11, The pseudo standby circuit is, A signal generation circuit for generating a set signal, And a set circuit forcing the circuit block into the pseudo standby state when the circuit block is in an active state and when the set signal of the signal generation circuit is no longer received. The method of claim 9, And a signal holding circuit holding a value of a signal output from the circuit block immediately before the pseudo standby state when in the pseudo standby state. The method of claim 13, The signal holding circuit, A signal generation circuit for generating a latch signal for holding an output signal of the circuit block when in the active state; And a latch circuit for receiving a latch signal of the signal generation circuit and latching an output signal of the circuit block. The method of claim 10, And the reference voltage level of the power line is set to a different voltage value in the active state and the standby state. The method of claim 12, The signal generation circuit, And an input signal to the circuit block to generate a set signal or a latch signal based on the input signal. The method of claim 14, The signal generation circuit, And inputting an input signal to the circuit block to generate a set signal or a latch signal based on the input signal.

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