KR100638893B1 - Quadrature prescaler using body bias control - Google Patents

Abstract

A quadrature prescaler using body bias control is provided to reduce power consumption by automatically controlling the bias according to the input signal level of a divider without considering a design margin against an environment change, even though the input signal level is changed when designing VCO. A quadrature prescaler using body bias control comprises an input signal detector(100), a bias circuit(200) and a divider(300). The input signal detector(100) detects the minimum value of an input signal and outputs a body bias voltage corresponding to the minimum value. The bias circuit(200) controls the bias required at the dividing operation according to the body voltage of the input signal detector. The divider(300) is operated according to the bias formed by the bias circuit(200), divides the first and second input signals into two portions and provides the first, the second, the third and the forth.

Description

QUADRATURE PRESCALER USING BODY BIAS CONTROL}

1 is a circuit diagram of a conventional quadrature prescaler.

2 is a graph of input signal-tolerance range characteristics of the prescaler of FIG.

3 is a graph of dispensing characteristics of the prescaler of FIG. 1.

4 is a circuit diagram of a quadrature prescaler according to the present invention;

5 is a circuit diagram of an input signal detector of FIG. 4.

FIG. 6 is a diagram of a body voltage detected by a waveform and a signal detector of the input signal of FIG. 5; FIG.

7 is a signal timing chart of the quadrature prescaler of the present invention.

8 is a graph of dispensing characteristics of the prescaler of the present invention.

Explanation of symbols on the main parts of the drawings

100: input signal detection unit 110: differential transistor circuit unit

120: capacitor circuit portion 200: bias circuit portion

300: Dispenser CLK, RMBAR CLK: First and second input signals

± I: first and second output signals ± Q: third and fourth output signals

Vbody: Body Voltage Q11: First Transistor

Q12: second transistor C11: first capacitor

C12: second capacitor IS: current source

Q20: transistor

The present invention relates to a quadrature prescaler applied to a frequency synthesizer. In particular, the present invention relates to a quadrature prescaler that has a linear division characteristic even when the level of an input signal is changed. The present invention relates to a quadrature prescaler using body bias control that can automatically adjust bias according to a divider input signal level, thereby reducing power consumption of an oscillator (VCO).

In general, a quadrature prescaler is applied to a frequency synthesizer, and in order to compare the phase with a reference frequency, four signals having different phases (± I) are divided by dividing the frequency of the oscillator (VCO) at a predetermined division ratio. Quadrature divider giving. ± Q).

Such quadrature divider should have a linear characteristic against environmental changes such as temperature change and have low power consumption.

1 is a circuit diagram of a conventional quadrature prescaler.

Referring to FIG. 1, in the conventional quadrature prescaler, a bias is formed by a bias circuit unit 10 and a bias circuit unit 10 for forming a bias required for a division operation, and thus, the first and second input signals CLK, And a dividing unit 20 which divides the RMBAR CLK into two and provides the first and second output signals ± I and the third and fourth output signals ± Q.

The bias circuit unit 10 is a fixed bias circuit and includes a current source IS and a transistor Q connected to a source.

The divider 20 has two first and second latches LAT1 and LAT2 in a ring structure, and the first latch LAT1 is formed at a rising edge of the first input signal CLK. It receives an input and provides an output at a rising edge of the second input signal RMBAR CLK. The second latch LAT2 receives an input at a rising edge of the second input signal RMBAR CLK and provides an output at a rising edge of the first input signal CLK.

By this operation, the first and second output signals (+ I and -I) have a phase difference (inverse phase) of 180 degrees to each other, and the third and fourth output signals (+ Q and -Q) are 180 to each other. It has a phase difference of degrees, and the first output signal + I and the third output signal + Q have a phase difference of 90 degrees.

FIG. 2 is a graph illustrating an input signal-tolerance range characteristic of the prescaler of FIG. 1.

In Figure 2, the horizontal axis is the frequency (Fin) of the input signal, the vertical axis is the minimum voltage (Vmin) of the input signal, the secondary curve (G) is a sensitivity graph of the divide. An area between two points where the second curve G meets the predetermined minimum voltage Vpp is a frequency allowable area in which frequency division operation is allowed in the frequency divider.

Referring to FIG. 2, when the level of the input signal changes, the frequency tolerance region, which is an area between two points that meet the secondary curve G and the predetermined minimum voltage Vpp, also changes, so that the level of the input signal changes. In this case, since the frequency tolerance is changed, in the worst case, there is a problem that the frequency division operation of the prescaler may be out of the frequency tolerance.

In addition, the operation principle of the above-described conventional prescaler is divided into two first and second latches (LAT1, LAT2) in a master-slave manner, each latch is a first, second, Since the bias of the input signals CLK and RMBAR CLK is fixed, a normal switch operation cannot be performed when the magnitude of the input signal is small. This will be described with reference to FIG. 3.

3 is a graph of dispensing characteristics of the prescaler of FIG. 1.

Referring to FIG. 3, as a simulation result graph of an operation region of a conventional prescaler, referring to the G1 (1.2V), G2 (1V), and G3 (800mV) graphs shown in FIG. 3, the conventional prescaler is 1.0 V or more. Although it has a linear division characteristic, there is a problem that the normal operating region is reduced for a signal of approximately 1.0V or less.

The present invention has been proposed to solve the above problems, and the object of the present invention is to implement a linear division characteristic even when the level of the input signal changes, so it is necessary to design margin considering the environment change in the oscillator (VCO) design. It is possible to automatically adjust the bias according to the divider input signal level so as to reduce the power consumption of the oscillator (VCO) to provide a quadrature prescaler using body bias adjustment.

In order to achieve the above object of the present invention, the quadrature prescaler using the body bias adjustment of the present invention, the input signal detector for detecting a minimum value of the input signal, and outputs a body voltage corresponding to the minimum value; A bias circuit unit that adjusts a bias required for the division operation according to the body voltage of the input signal detector; And dividing the first and second input signals by two to provide the first and second output signals (± I) and the third and fourth output signals (± Q). Characterized in that it comprises a divider.

The input signal detector may include a first transistor having the first input signal connected to a drain and a gate, and a second transistor having the second input signal connected to the drain and a gate, wherein the first and second transistors cross each other. A differential transistor circuit coupled to provide a diffuser body voltage through a common source of the first and second transistors; And a capacitor circuit including a first capacitor connected to ground at the source of the first transistor, and a second capacitor connected to ground at the source of the second transistor.

The bias circuit unit includes a current source for supplying a constant constant current; And a transistor connected between the current source and the ground and adjusting the divided bias by the body voltage of the input signal detector.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings referred to in the present invention, components having substantially the same configuration and function will use the same reference numerals.

4 is a circuit diagram of a quadrature prescaler according to the present invention.

Referring to FIG. 4, the quadrature prescaler according to the present invention includes an input signal detector 100 for detecting a minimum value of an input signal and outputting a body voltage Vbody corresponding to the minimum value, and the input signal detector 100. The bias circuit unit 200 adjusts the bias required for the frequency division operation according to the body voltage Vbody of the?, And operates according to the bias formed by the bias circuit unit 200, and the first and second input signals CLK and RMBAR And a dividing unit 300 which divides the CLK into two and provides the first and second output signals ± I and the third and fourth output signals ± Q.

FIG. 5 is a circuit diagram of an input signal detector of FIG. 4.

Referring to FIG. 5, the input signal detector 100 includes a differential transistor circuit 110 and a capacitor circuit 120.

The differential transistor circuit unit 110 may include a first transistor Q11 having the first input signal CLK connected to a drain and a gate, and a second transistor having the second input signal RMBAR CLK connected to the drain and a gate. Q12), and the first and second transistors Q11 and Q12 are cross-coupled with each other to provide the body voltage Vbody through a common source of the first and second transistors Q11 and Q12. do.

The capacitor circuit unit 120 includes a first capacitor C11 connected to ground at the source of the first transistor Q11, and a second capacitor C12 connected to ground at the source of the second transistor Q12. do.

In addition, the bias circuit unit 200 is connected between the current source IS for supplying a constant constant current, the current source IS, and the ground, and is divided by the body voltage Vbody of the input signal detection unit 100. It includes a transistor (Q20) to control the.

6 is a diagram of a body voltage detected by the waveform and signal detector of the input signal of FIG. 5.

In FIG. 6, the vertical axis is an input voltage, the vertical axis is time, and when an input signal as shown in FIG. 6 is input, the body voltage Vbody corresponding to the minimum level of the input signal is determined by the signal detector of the present invention. Is detected.

7 is a signal timing chart of the quadrature prescaler of the present invention.

In FIG. 7, CLK is the first input signal, RMBAR CLK is the second input signal, LAT10-D is the input waveform of the first latch LAT10, + I is the first output signal, and -I is the second. It is an output signal, + Q is a third output signal, and -Q is a fourth output signal.

8 is a graph of dispensing characteristics of the prescaler of the present invention.

In FIG. 8, the frequency of the input signal in the range of about 3 GHz to 6 GHz is divided to show a frequency of division in the range of about 1.5 GHz to 3 GHz, wherein the input signal is respectively about 600 mV, 800 mV, 1 V, 1.2 V and 1.4 V. Dispensing characteristics are shown.

Hereinafter, the operation and effects of the present invention will be described in detail with reference to the accompanying drawings.

The basic contents of the present invention are to automatically adjust the division bias of the first and second input signals CLK and RM BAR CLK by sensing the magnitude of the input signal, which will be described in detail with reference to FIGS. 4 to 8. .

4 to 8, the operation of the quadrature prescaler of the present invention will be described. First, in FIG. 4, the input signal detection unit 100 of the present invention detects a minimum value of an input signal and corresponds to the minimum value. The body voltage Vbody is output to the bias circuit unit 200.

In this case, the bias circuit unit 200 adjusts the bias required for the division operation of the division unit 300 of the present invention according to the body voltage Vbody of the input signal detection unit 100.

The division unit 300 operates according to the bias formed by the bias circuit unit 200, divides the first and second input signals CLK and RMBAR CLK into two parts as shown in FIG. 7. The first and second output signals ± I and the third and fourth output signals ± Q are provided.

In this case, the first and second output signals (± I) and the third and fourth output signals (± Q) are divided by two frequencies of the input signal, and each has a different phase as described above.

The input signal detector 100 will be described with reference to FIG. 5.

Referring to FIG. 5, the input signal detector 100 includes a differential transistor circuit unit 110 and a capacitor circuit unit 120. The differential transistor circuit unit 110 includes the first and second input signals CLK, A voltage proportional to the minimum value of the RMBAR CLK is detected and output as a body voltage Vbody proportional to the detection voltage through a common source of the first and second transistors Q11 and Q12. In this case, the body voltage Vbody is stabilized by the first and second capacitors C11 and C12 of the capacitor circuit unit 120.

As described above, according to the input signal detection unit 100 of the present invention, the body voltage Vbody corresponding to the minimum value of the input signal is output to the bias circuit unit 200.

Referring to FIG. 4, the operation of the bias circuit unit 200 will be described in more detail. The current source IS of the bias circuit unit 200 always generates a constant constant current and supplies it to the transistor Q20.

In this case, the transistor Q20 adjusts the bias of the frequency division operation according to the body voltage Vbody. When the bias adjustment is described in detail, when the body voltage Vbody changes, the body voltage Vbody The internal threshold voltage of the transistor Q20 is changed. As the internal turnover voltage of the transistor Q20 is changed, the bias is changed.

As described above, the change in the minimum value of the input signal is detected by the change in the body voltage Vbody, and the change in the input signal detected by the body voltage Vbody causes a change in the takeover voltage of the transistor, and thus the divider 300 Bias is adjusted, and the bias of the switch for performing the frequency division operation in the division unit 300 is adjusted.

In other words, the body voltage Vbody corresponding to the minimum value of the input signal is detected by sensing the magnitude of the input signal. In this case, the detected body voltage value also changes according to the change of the input signal. In other words, when the magnitude of the input signal decreases, the body voltage becomes large, and thus the threshold voltage decreases due to the body voltage.

As described above, when the threshold voltage is lowered for a constant reference current, the gate DC voltage of the switch element such as a transistor is lowered, thereby enabling normal on / off operation for a small input value.

The simulation results of the prescaler of the present invention are as shown in FIG. Can be.

As described above, the present invention relates to a divider by 2 that lowers the signal of the VCO to a low frequency in a frequency synthesizer. The divider is divided according to the magnitude of the input signal in the sensitivity of divider characteristic. The permissible region of divider is determined.

Usually, the operating area of the divider is set to have sufficient margin in consideration of changes caused by various environments. At this time, the VCO output signal increases in size and power consumption of the VCO increases, and thus VCO + The power consumption of the block of the PLL is increased. In addition, a VCO with a wide tuning range may not be able to perform normal divider operation due to the magnitude of the signal varying with frequency. Therefore, by designing a divider that can automatically change the sensitivity (sensitivity) to changes in the environment, it is easy to design by reducing power consumption and the difficulty of excessive margin design.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, but is defined by the claims, and the apparatus of the present invention may be substituted, modified, and modified in various ways without departing from the spirit of the present invention. It is apparent to those skilled in the art that modifications are possible.

According to the present invention as described above, in the quadrature prescaler applied to the frequency synthesizer, even if the input signal level is implemented to have a linear division characteristics, it is necessary to design margins considering the environmental changes in the design of the oscillator (VCO) The bias can be automatically adjusted according to the input signal level of the divider so that the power consumption of the oscillator (VCO) can be reduced.

Claims (3)

An input signal detector for detecting a minimum value of the input signal and outputting a body voltage corresponding to the minimum value; A bias circuit unit that adjusts a bias required for the division operation according to the body voltage of the input signal detector; And Operating according to the bias formed by the bias circuit unit, and divides the first and second input signals by two to provide the first and second output signals (± I) and the third and fourth output signals (± Q). housewife Quadrature prescaler using a body bias adjustment comprising a. The method of claim 1, wherein the input signal detector A first transistor having a first input signal connected to a drain and a gate, and a second transistor connected to the drain and gate connected to the first input signal, wherein the first and second transistors are cross-coupled with each other; A differential transistor circuit portion for providing an diffuser body voltage through a common source of the first and second transistors; And A capacitor circuit including a first capacitor connected to ground at the source of the first transistor, and a second capacitor connected to ground at the source of the second transistor Quadrature prescaler using a body bias adjustment comprising a. The method of claim 1, wherein the bias circuit unit, A current source for supplying a constant constant current; And A transistor connected between the current source and ground, the dividing bias being adjusted by a body voltage of the input signal detector; Quadrature prescaler using a body bias adjustment comprising a.

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