KR100636968B1 - Image sensor for improving horizontal line noise - Google Patents

Abstract

The present invention is to provide a high-resolution image sensor by improving the horizontal line noise, the present invention for this purpose includes a first load transistor connected to the column address bus of a plurality of pixels; A second load transistor connected in series with the first load transistor; A first bias transistor configured to receive a bias current from a first bias current source to form a current mirror with the first load transistor; And a second bias transistor unit configured to receive a bias current from a second bias current source and form a current mirror together with the second load transistor.

Image sensor, readout circuit, load transistor, parasitic capacitance, horizontal line noise

Description

Image sensor for improving horizontal line noise {IMAGE SENSOR FOR IMPROVING HORIZONTAL LINE NOISE}             

1 is a picture capturing the screen of the horizontal line noise generated in the 1.3 million pixel class products currently under development.

2 is a configuration of an image sensor having a typical m x n pixel array.

3 is a timing diagram for output voltage and current of a column address bus and Vbias.

4 is a view showing only the Vbias voltage of FIG.

5 is a diagram illustrating a configuration of an image sensor according to an embodiment of the present invention.

Figure 6 is a simulation of the effect on the horizontal line noise by applying an image sensor having a current code of the cascode form according to the present invention to the existing 2.1Mega product.

* Explanation of symbols for the main parts of the drawings

200: second bias transistor portion

300: first load transistor unit

400: second load transistor unit

The present invention relates to an image sensor, and more particularly, to an image sensor for improving horizontal line noise in a CMOS image sensor or a bulk charge modulated device (BCMD) image sensor.

CIF (352 x 288) or VGA (640 x 480) class has been mainstream in the application of conventional image sensors. However, in recent years, a high resolution image sensor of 1 million pixels or more has become mainstream in the application market. .

As the resolution has surpassed the 1 Mega level, problems that did not occur in the conventional CIF or VGA class have started to occur one by one. One of them is horizontal noise. Vertical noise in the image sensor is largely due to fixed pattern noise (FPN), which can be largely eliminated by technologies such as correlated double sampling (CDS), but horizontal noise has begun to occur in high-resolution products.

FIG. 1 is a picture capturing a screen of horizontal line noise generated in a 1.3 megapixel (1.3 Mega) product under development. As shown in FIG. 1, horizontal line noise is a phenomenon in which horizontal lines appear in a horizontal direction of an area where a bright subject is located on a screen. This phenomenon occurs because the code values of the normal pixels in the same row as the bright subject are smaller than the code values of other pixels (Pixel) above or below the horizontal line due to the influence of the bright subject. .

FIG. 2 shows a configuration of an image sensor having a typical m x n pixel array, and shows a read out circuit for obtaining a code value from a pixel through a column analog bus.

In the mega pixel image sensor, more than 1024 pixels are arranged in a row direction to form an m x n pixel array. In such a configuration, all pixels of one row of the pixel array deliver pixel signals to CDS circuits provided for each column at the same time (same clock), and each CDS circuit sequentially analog signals in response to the column address. It is delivered to the processing circuit.

To describe the CDS (Correlated Double Sampling) operation in more detail, first, reset the voltage of the floating diffusion (FD) node, which is the sensing node of the pixel, by resetting the reset transistor (RX) On to reset the voltage of the FD node. Read through the column analog bus to store the reset value. Subsequently, when the transfer transistor TX is turned on, the voltage of each photo-detector is transferred to the FD nodes, and the voltage of the FD node is read through the column address bus to store data values. Subsequently, the data value of each CDS pixel is calculated using the voltage difference between the previously stored reset value and the subsequently stored data value.

A readout circuit connected to the column analog bus reads the reset and data values, and the CDS circuitry stores the read values. The read circuit is configured as a load transistor ML connected to the column address bus and a transistor MF together with the load transistor ML to form a current mirror.

On the other hand, conventionally, the ratio of the transistors MF and ML is set to 1: 1 so that the same current flows through the column analog bus.

In the operation as described above, the voltage of each photo detector is determined according to the brightness of the ambient light. For example, the photo detector exposed to bright light has a low voltage, and the photo detector exposed to dark light has a relatively high voltage. As such, the voltage of the FD node forms a source-follower structure by the driver transistor DX of the pixel and the load transistor ML constituting the read circuit, and the output voltage Vp <m: of each column address bus. 0> is determined by the voltage of the FD node and the current Ibias * x flowing through the load transistor ML.

However, as mentioned above, in the image sensor of more than 1 million pixels (1 Mega), the horizontal line noise appears in a specific environment, which is caused by the parasitic capacitance Cp <m: 0>.

3 is a timing diagram for output voltage and current of a column address bus and Vbias (gate node voltage of a load transistor).

As shown in the figure, when the change in pixel voltage is large, as the Vbias voltage decreases, the Ibias current flowing between the source and drain of the load transistor decreases, and when the Ibias current decreases, the Vgs voltage generated in the driver transistor DX decreases.

Since this state is not stabilized until the time when the signal voltage is stored, the Vbias voltage is about 94% and the Ibias flows only 50%, so that the code value is determined to be smaller than the voltage difference of the general pixel, so that the dark streaks appear on the screen. Noise is generated.

In other words, in principle, the output voltage Vp of the column analog bus should only be influenced by the current Ibias of the transistor MF constituting the readout circuit, but in reality the overlap between the drain and the gate of the transistor ML (overlap) Vbias voltage fluctuates while the voltage of the column analog bus node changes from the reset voltage to the data voltage by the capacitance Cp <m: 0>, and the voltage of the load transistor gate driving line (Vbias) at the time of storing the data voltage. ) Is not stabilized, so a horizontal line appears on the screen.

In addition, the reason why the Vbias voltage is not stabilized faster than the previous VGA or CIF class is that the capacitive load in which the Ibias current must be driven is the gate capacitance of the transistor (MF) and the load transistor (ML <m: 0>), the sum of the gate capacitance and the parasitic capacitance of the Vbias node, etc., as the resolution increases horizontally as it goes beyond 1 million pixels. to be.

FIG. 4 is a diagram illustrating only the Vbias voltage of FIG. 3 in detail. When the unbiased Vbias voltage τ (τRC) is reduced to increase the Ibias current of the transistor MF, the voltage is stabilized until the write time wrt_sig.

However, in order to increase the Ibias current of the transistor MF in this manner, it takes a long time because the simulation must be performed according to the pixel and the Ibias current is adjusted accordingly.

In addition, if the Ibias current of the transistor MF is increased, the current of each column analog bus is also increased, thereby reducing the dynamic range of the pixel and deteriorating optical characteristics.

The present invention has been proposed to solve the above problems of the prior art, and has an object to provide a high resolution image sensor by improving horizontal line noise.

According to an aspect of the present invention, a first load transistor connected to a column address bus of a plurality of pixels, a second load transistor connected in series with the first load transistor, and a first bias current supply source are provided. A first bias transistor configured to receive a first bias current to form a current mirror together with the first load transistor, and a second bias current supplied from a second bias current source to form a current mirror together with the second load transistor. And a bias voltage applied to the second load transistor, wherein the bias voltage applied to the second load transistor is a saturation voltage that determines the output current of the column address bus by a current mirror structure. To serve.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a diagram illustrating a configuration of an image sensor according to an exemplary embodiment of the present invention.

Referring to FIG. 5, an image sensor according to an exemplary embodiment of the present invention is connected to a pixel 100 and a column address bus (Column Analog Bus <0>,…, Column Analog Bus <m>) of the pixel 100. The first load transistor receives a bias current from the first load transistor unit 300, the second load transistor unit 400 connected in series with the first load transistor unit 300, and the first bias current source Ibias1. A first bias transistor MF2 constituting the current mirror together with the unit 300 and a bias current are applied from the second bias current supply source Ibias2 to form the current mirror together with the second load transistor unit 400. The second bias transistor unit 200 includes a read circuit for reading data of the pixel 100.

Since the bias voltage Vbias applied to the second load transistor unit 400 becomes a saturation voltage that determines the output current I of the column address bus by the current mirror structure, the first bias current supply source. The determination of (Ibias1) allows Vg to have Vds + Vth + ΔV.

Therefore, the image sensor according to the present invention further includes the second bias transistor unit 200 and the second load transistor unit 400, so that the output current I is caused by the existing parasitic capacitance Cp <m: 0>. Ensure that it remains stable and unaffected.

6 is a diagram simulating the effect on the horizontal line noise by applying an image sensor having a current mirror of the cascode form according to the present invention to the existing 2.1Mega product.

As shown in the figure, even when the change in the pixel voltage is large, the Vbias voltage is kept stable, and the Ibais is also maintained at 99.5%. The Vg voltage is affected by the change in pixel voltage, but it is stabilized to 99.9% at the writing time wrt_sig.

As such, the image sensor according to the exemplary embodiment implements the readout circuit using the current mirror implemented in the form of a cascode, and thus is not affected by the overlap capacitance Cp <m: 0> between the drain and the gate of the load transistor. Instead, the amount of current flowing through the load transistor is kept constant to remove horizontal line noise.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above implements a read circuit using a current mirror implemented in a cascode form, thereby eliminating horizontal line noise by maintaining a constant amount of current flowing through the load transistor without being affected by the overlap capacitance between the drain and the gate of the load transistor. do.

Claims (2)

delete A first load transistor coupled to a column address bus of the plurality of pixels; A second load transistor connected in series with the first load transistor; A first bias transistor configured to receive a first bias current from a first bias current source to form a current mirror with the first load transistor; And A second bias transistor unit configured to receive a second bias current from a second bias current source to form a current mirror together with the second load transistor, And a bias voltage applied to the second load transistor unit is a saturation voltage that determines an output current of the column address bus by a current mirror structure.

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