KR100632474B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided. The semiconductor memory device may include a first voltage line, a second voltage line having a noise characteristic complementary to that of the first voltage line, a reference voltage line transferring a reference voltage, which is a reference for a plurality of input signals input from the outside, to the input buffer; And a first decoupling capacitor electrically connecting the first voltage line and the reference voltage line, and a second decoupling capacitor electrically connecting the second voltage line and the reference voltage line.

Parasitic Capacitors, Decoupling Capacitors, Noise

Description

Semiconductor memory devices

1 is an equivalent circuit diagram illustrating a semiconductor memory device for reducing noise of a conventional reference voltage.

2 is a diagram illustrating a reference voltage of the semiconductor memory device of FIG. 1.

3 is an equivalent circuit diagram of a semiconductor memory device for reducing noise of a reference voltage according to an embodiment of the present invention.

4 is a diagram illustrating a reference voltage of the semiconductor memory device of FIG. 3.

5A to 5H are diagrams illustrating noise characteristics of voltages used in semiconductor memory devices.

6 is an equivalent circuit diagram of a semiconductor memory device for reducing noise of a reference voltage according to another embodiment of the present invention.

7 is an equivalent circuit diagram of a semiconductor memory device for reducing noise of a reference voltage according to another embodiment of the present invention.

 (Explanation of symbols for the main parts of the drawing)

10, 11, 12: semiconductor memory device C3: parasitic capacitor

C4, C5, C6: Decoupling Capacitors

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for reducing noise of a reference voltage.

In general, a synchronous semiconductor memory device provides a reference voltage Vref from an external source to provide a reference for determining a high / low of an input signal. In addition, the reference voltage Vref and the input signal are received from the input buffer, and the difference is amplified and output.

Therefore, in order to clearly determine the high / low of the input signal, it is necessary to reduce or eliminate the noise present in the reference voltage Vref. The reference voltage Vref mainly includes kick back noise, interconnect coupling noise, and the like. Kickback noise means that the output signal fluctuated by the overlap capacitor of the input buffer affects the reference voltage Vref. Interconnect coupling noise refers to noise generated by coupling the reference voltage Vref and an input signal.

1 is an equivalent circuit diagram illustrating a semiconductor memory device for reducing noise of a conventional reference voltage. 2 is a diagram illustrating a reference voltage of the semiconductor memory device of FIG. 1.

Referring first to FIG. 1, a semiconductor memory device 1 for reducing noise of a conventional reference voltage Vref includes a parasitic capacitor C1 and a decoupling capacitor C2. The parasitic capacitor C1 refers to noise coupled to another input signal SN to affect the reference voltage Vref, and the decoupling capacitor C2 has a capacitance sufficiently larger than that of the parasitic capacitor C1 (C1 < <C2), Artificially install to reduce noise. In the equivalent circuit diagram of FIG. 1, the capacitance of the parasitic capacitor C1 uses 2fF, and the capacitance of the decoupling capacitor C2 uses 0.5pF.

Here, the decoupling capacitor C2 is electrically connected to a power supply line PW used in a DRAM such as an external power supply voltage VCC, a back bias voltage VBB, and a ground voltage VSS. However, since the power supply line PW generally contains a lot of noise, this noise affects the reference voltage Vref.

That is, the noise of the reference voltage Vref is determined by the amplitude of the input signal SN, the amplitude of the power supply line PW, the parasitic capacitor C1 and the decoupling capacitor C2 as shown in Equation 1 below. It can be seen that the noise of the reference voltage Vref is larger by ΔPW due to the influence of the power supply line PW.

Referring to FIG. 2, in the case of the conventional semiconductor memory device (b), the noise of the power supply line PW electrically connected to the decoupling capacitor C2 is compared with the reference voltage without filtering. Vref). That is, it can be seen that a peak of about 200mV is generated. As such, the noise present in the reference voltage Vref makes it difficult to distinguish the point of change (high to low transition or low to high transition) of the input signal SN, resulting in poor setup and hold characteristics. . In addition, since the amplitude of the input signal SN must be large so that the input buffer can provide an accurate output signal, the signal margin of the input signal SN is bad.

An object of the present invention is to provide a semiconductor memory device for reducing noise of a reference voltage line.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In accordance with an aspect of the present invention, a semiconductor memory device may include a first voltage line, a second voltage line having a noise characteristic complementary to that of a first voltage line, and a plurality of input signals input from the outside. A reference voltage line for transferring a reference voltage as a reference to the input buffer, a first decoupling capacitor electrically connecting the first voltage line and the reference voltage line, and a second decoupling capacitor electrically connecting the second voltage line and the reference voltage line It includes.

According to another aspect of the present invention, a semiconductor memory device may transmit a regulated third voltage line without noise and a reference voltage serving as a reference for a plurality of input signals input from the outside to an input buffer. And a third decoupling capacitor electrically connecting the reference voltage line, the third voltage line, and the reference voltage line.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

3 is an equivalent circuit diagram of a semiconductor memory device for reducing noise of a reference voltage according to an embodiment of the present invention. 4 is a diagram illustrating a reference voltage of the semiconductor memory device of FIG. 3.

Referring to FIG. 3, a semiconductor memory device 10 for reducing noise of a reference voltage according to an embodiment of the present invention may include a parasitic capacitor C3, a first decoupling capacitor C4, and a second decoupling capacitor C5. It includes.

The parasitic capacitor C3 refers to noise coupled to the other input signal SN1 to affect the reference voltage Vref.

The first and second decoupling capacitors C4 and C5 have a capacitance sufficiently larger than the parasitic capacitor C3 (C3 << C4, C3 << C5), and are artificially installed to reduce noise. In the equivalent circuit diagram of FIG. 3, the capacitance of the parasitic capacitor C3 uses 2fF, and the capacitance of the first and second decoupling capacitors C4 and C5 uses 0.25 pF.

Here, the first decoupling capacitor C4 electrically connects the first voltage line and the reference power supply line, and the second decoupling capacitor C5 references the second voltage line having a noise characteristic complementary to that of the first voltage line. Connect with the line. When the first voltage line and the second voltage line have complementary noise characteristics, noise that affects the reference voltage Vref may cancel each other. The first voltage PW1 may be an internal power supply voltage IVCA for the array, and the second voltage PW2 may be an array ground voltage VSSA.

5A to 5H are diagrams illustrating noise characteristics of voltages used in semiconductor memory devices.

5A to 5H illustrate an internal voltage IVCA for an array, an earth voltage VSSA for an array, an internal voltage IVC for a peri, a global ground voltage VSS, and a ground used during a write operation. Noise characteristics of the voltage VSSW, the array power supply voltage VDDA, the external power supply voltage VDD, and the boosted voltage VPP are shown.

Here, it can be seen that the voltages representing the relatively complementary noise characteristics are the internal voltage IVCA for the array and the ground voltage VSSA for the array of FIG. 5A.

Referring back to FIG. 4, it can be seen that the fluctuation of the reference voltage Vref is greatly reduced by connecting to the first and second voltages exhibiting complementary noise characteristics. That is, it can be seen that only noise of about 40 mV exists. Therefore, the timing of change of the input signal SN1 can be clearly determined, and setup and hold characteristics can be improved. In addition, even if the input signal is weak, the input buffer can provide a strong output signal, thereby improving the signal margin of the input signal SN1.

6 is an equivalent circuit diagram of a semiconductor memory device for reducing noise of a reference voltage according to another embodiment of the present invention. The same reference numerals are used for constituent elements that are substantially the same as in FIG. 3, and a detailed description of the corresponding constituent elements will be omitted.

Referring to FIG. 6, a semiconductor memory device 11 for reducing noise of a reference voltage according to another embodiment of the present invention may electrically connect a first decoupling capacitor C4 and a second decoupling capacitor C5 with a reference voltage line. It further comprises a resistor (R) connected to.

As shown in FIG. 4, the first voltage PW1 and the second voltage PW2 exhibit relatively complementary noise characteristics, but are not completely complementary. Therefore, a minute section in which the first and second voltages PW1 and PW2 are not complementary may create sharp peak noise at the reference voltage Vref. Therefore, the resistor R serves to filter this noise.

However, it may be considered to electrically connect a resistor between the first and second decoupling capacitors C4 and C5 and the first and second voltages PW1 and PW2, respectively. In this case, the first and second decoupling capacitors C4 and C5 and the resistor serve as a low pass filter. In general, the noise of the power line used inside the DRAM is mostly due to low frequency components. However, when the low pass filter is used, it is not preferable because the high frequency component is not quickly dissipated and a sharp peak occurs at the reference voltage Vref.

7 is an equivalent circuit diagram of a semiconductor memory device for reducing noise of a reference voltage according to another embodiment of the present invention.

Referring to FIG. 7, a semiconductor memory device 12 for reducing noise of a reference voltage according to another embodiment of the present invention includes a parasitic capacitor C3 and a third decoupling capacitor C6. The capacitance of the third decoupling capacitor C6 is sufficiently large compared to the capacitance of the parasitic capacitor C3 (C3 << C6). Here, the third decoupling capacitor C6 electrically connects the regulated third voltage line and the reference voltage line without noise.

In this case, since the third voltage line has no noise, the noise of the reference voltage Vref is determined by the amplitude of the input signal SN, the parasitic capacitor C1, and the decoupling capacitor C2 as shown in Equation 2.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the semiconductor memory device as described above has one or more of the following effects.

First, the noise of the reference voltage line can be reduced.

Second, since the timing of change of the input signal can be clearly determined, setup and hold characteristics are improved.

Third, the signal margin of the input signal is improved.

Claims (4)

A reference voltage line transferring a reference voltage, which is a reference for a plurality of input signals input from the outside, to the input buffer; First and second voltage lines having complementary noise characteristics; A first decoupling capacitor electrically connecting the first voltage line and the reference voltage line; And And a second decoupling capacitor electrically connecting the second voltage line and the reference voltage line. The semiconductor memory device of claim 1, wherein the first voltage is an internal power supply voltage for the array, and the second voltage is a ground voltage for the array. The semiconductor memory device of claim 1, further comprising a resistor electrically connecting the first decoupling capacitor and the second decoupling capacitor to the reference voltage line. A regulated third voltage line free of noise; A reference voltage line transferring a reference voltage, which is a reference of a plurality of input signals input from the outside, to the input buffer; And And a third decoupling capacitor electrically connecting the third voltage line and the reference voltage line.

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