KR100626858B1 - 단일 적재 워드를 형성하기 위해서 별개의 저장 버퍼 엔트리들로부터의 개별 바이트들의 전송을 적재하는 저장 시스템 - Google Patents
단일 적재 워드를 형성하기 위해서 별개의 저장 버퍼 엔트리들로부터의 개별 바이트들의 전송을 적재하는 저장 시스템 Download PDFInfo
- Publication number
- KR100626858B1 KR100626858B1 KR1020017003691A KR20017003691A KR100626858B1 KR 100626858 B1 KR100626858 B1 KR 100626858B1 KR 1020017003691 A KR1020017003691 A KR 1020017003691A KR 20017003691 A KR20017003691 A KR 20017003691A KR 100626858 B1 KR100626858 B1 KR 100626858B1
- Authority
- KR
- South Korea
- Prior art keywords
- storage
- load
- byte
- queue
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/158,465 | 1998-09-22 | ||
| US09/158,465 US6141747A (en) | 1998-09-22 | 1998-09-22 | System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010073182A KR20010073182A (ko) | 2001-07-31 |
| KR100626858B1 true KR100626858B1 (ko) | 2006-09-22 |
Family
ID=22568258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020017003691A Expired - Fee Related KR100626858B1 (ko) | 1998-09-22 | 1999-04-03 | 단일 적재 워드를 형성하기 위해서 별개의 저장 버퍼 엔트리들로부터의 개별 바이트들의 전송을 적재하는 저장 시스템 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6141747A (enExample) |
| EP (1) | EP1116103B1 (enExample) |
| JP (1) | JP3871884B2 (enExample) |
| KR (1) | KR100626858B1 (enExample) |
| DE (1) | DE69932066T2 (enExample) |
| WO (1) | WO2000017746A1 (enExample) |
Families Citing this family (88)
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| US20070288725A1 (en) * | 2006-06-07 | 2007-12-13 | Luick David A | A Fast and Inexpensive Store-Load Conflict Scheduling and Forwarding Mechanism |
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| US8447911B2 (en) * | 2007-07-05 | 2013-05-21 | Board Of Regents, University Of Texas System | Unordered load/store queue |
| US7849290B2 (en) * | 2007-07-09 | 2010-12-07 | Oracle America, Inc. | Store queue architecture for a processor that supports speculative execution |
| US8645670B2 (en) * | 2008-02-15 | 2014-02-04 | International Business Machines Corporation | Specialized store queue and buffer design for silent store implementation |
| US8627047B2 (en) * | 2008-02-15 | 2014-01-07 | International Business Machines Corporation | Store data forwarding with no memory model restrictions |
| JP5426684B2 (ja) * | 2008-10-30 | 2014-02-26 | ヒューレット−パッカード デベロップメント カンパニー エル.ピー. | 独立ディスク冗長アレイ(raid)の書き込みキャッシュサブアセンブリ |
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| US10157060B2 (en) | 2011-12-29 | 2018-12-18 | Intel Corporation | Method, device and system for control signaling in a data path module of a data stream processing engine |
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| US9619382B2 (en) | 2013-08-19 | 2017-04-11 | Intel Corporation | Systems and methods for read request bypassing a last level cache that interfaces with an external fabric |
| US9665468B2 (en) | 2013-08-19 | 2017-05-30 | Intel Corporation | Systems and methods for invasive debug of a processor without processor execution of instructions |
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| US9483409B2 (en) | 2015-02-05 | 2016-11-01 | International Business Machines Corporation | Store forwarding cache |
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| US10514925B1 (en) | 2016-01-28 | 2019-12-24 | Apple Inc. | Load speculation recovery |
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| US10416999B2 (en) | 2016-12-30 | 2019-09-17 | Intel Corporation | Processors, methods, and systems with a configurable spatial accelerator |
| US10572376B2 (en) * | 2016-12-30 | 2020-02-25 | Intel Corporation | Memory ordering in acceleration hardware |
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| US10387319B2 (en) | 2017-07-01 | 2019-08-20 | Intel Corporation | Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features |
| US10469397B2 (en) | 2017-07-01 | 2019-11-05 | Intel Corporation | Processors and methods with configurable network-based dataflow operator circuits |
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| US11086816B2 (en) | 2017-09-28 | 2021-08-10 | Intel Corporation | Processors, methods, and systems for debugging a configurable spatial accelerator |
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| US11175924B2 (en) | 2017-10-06 | 2021-11-16 | International Business Machines Corporation | Load-store unit with partitioned reorder queues with single cam port |
| US10606590B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Effective address based load store unit in out of order processors |
| US10606591B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
| US10572256B2 (en) | 2017-10-06 | 2020-02-25 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
| US10579387B2 (en) | 2017-10-06 | 2020-03-03 | International Business Machines Corporation | Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor |
| US10394558B2 (en) | 2017-10-06 | 2019-08-27 | International Business Machines Corporation | Executing load-store operations without address translation hardware per load-store unit port |
| US10417175B2 (en) | 2017-12-30 | 2019-09-17 | Intel Corporation | Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator |
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| US11200186B2 (en) | 2018-06-30 | 2021-12-14 | Intel Corporation | Apparatuses, methods, and systems for operations in a configurable spatial accelerator |
| US10891240B2 (en) | 2018-06-30 | 2021-01-12 | Intel Corporation | Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator |
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| US11029927B2 (en) | 2019-03-30 | 2021-06-08 | Intel Corporation | Methods and apparatus to detect and annotate backedges in a dataflow graph |
| US10965536B2 (en) | 2019-03-30 | 2021-03-30 | Intel Corporation | Methods and apparatus to insert buffers in a dataflow graph |
| US10817291B2 (en) | 2019-03-30 | 2020-10-27 | Intel Corporation | Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator |
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| US11907713B2 (en) | 2019-12-28 | 2024-02-20 | Intel Corporation | Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator |
| US11379241B2 (en) * | 2020-07-30 | 2022-07-05 | International Business Machines Corporation | Handling oversize store to load forwarding in a processor |
| US12086080B2 (en) | 2020-09-26 | 2024-09-10 | Intel Corporation | Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits |
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| DE69429612T2 (de) * | 1993-10-18 | 2002-09-12 | Via-Cyrix, Inc. | Schreibpuffer für einen superskalaren Mikroprozessor mit Pipeline |
| US5471598A (en) * | 1993-10-18 | 1995-11-28 | Cyrix Corporation | Data dependency detection and handling in a microprocessor with write buffer |
| US5878245A (en) * | 1993-10-29 | 1999-03-02 | Advanced Micro Devices, Inc. | High performance load/store functional unit and data cache |
| US5588126A (en) * | 1993-12-30 | 1996-12-24 | Intel Corporation | Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system |
| US5784586A (en) * | 1995-02-14 | 1998-07-21 | Fujitsu Limited | Addressing method for executing load instructions out of order with respect to store instructions |
| US5832297A (en) * | 1995-04-12 | 1998-11-03 | Advanced Micro Devices, Inc. | Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations |
| US5802588A (en) * | 1995-04-12 | 1998-09-01 | Advanced Micro Devices, Inc. | Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer |
| US5835747A (en) * | 1996-01-26 | 1998-11-10 | Advanced Micro Devices, Inc. | Hierarchical scan logic for out-of-order load/store execution control |
| US6021485A (en) * | 1997-04-10 | 2000-02-01 | International Business Machines Corporation | Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching |
-
1998
- 1998-09-22 US US09/158,465 patent/US6141747A/en not_active Expired - Lifetime
-
1999
- 1999-04-03 DE DE69932066T patent/DE69932066T2/de not_active Expired - Lifetime
- 1999-04-03 JP JP2000571340A patent/JP3871884B2/ja not_active Expired - Fee Related
- 1999-04-03 EP EP99916331A patent/EP1116103B1/en not_active Expired - Lifetime
- 1999-04-03 WO PCT/US1999/007332 patent/WO2000017746A1/en not_active Ceased
- 1999-04-03 KR KR1020017003691A patent/KR100626858B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6141747A (en) | 2000-10-31 |
| EP1116103A1 (en) | 2001-07-18 |
| KR20010073182A (ko) | 2001-07-31 |
| JP2002525742A (ja) | 2002-08-13 |
| JP3871884B2 (ja) | 2007-01-24 |
| EP1116103B1 (en) | 2006-06-21 |
| WO2000017746A1 (en) | 2000-03-30 |
| DE69932066T2 (de) | 2007-06-21 |
| DE69932066D1 (en) | 2006-08-03 |
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