KR100622227B1 - Transistor for driving organic light emitting diode and pixel circuit and display device using the same - Google Patents

Abstract

The present invention relates to a transistor in which a channel of a driving transistor has a multi-current movement path, and a pixel and a light emitting display device which can improve the image quality of a display device by increasing the uniformity of transistors in a panel. A transistor according to the present invention is formed in a closed loop shape on a substrate, the first semiconductor layer having a channel having at least two current movement paths and a source and a drain connected to both ends of the channel, and formed in contact with the channel. And a gate facing the channel with the gate insulating layer interposed therebetween.

Light Emitting Display, Transistor, Crystallization Process, Multi-Current Moving Path

Description

Transistor for driving organic light emitting diode and pixel circuit and display device using the same}             

1 is a plan view of a transistor according to an embodiment of the present invention.

2 is a plan view illustrating a case where a high density defect part is formed in a transistor according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of the transistor taken along the line III-III of FIG. 1.

4A to 4G are plan views illustrating modified examples of the transistor according to the exemplary embodiment of the present invention.

5 is a layout diagram of pixels of a light emitting display device employing a transistor according to an exemplary embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of the pixel of FIG. 5.

FIG. 7 is a cross-sectional view of the pixel taken along line VI-VI of FIG. 5.

8 is a circuit diagram of another pixel circuit that may employ a transistor according to an embodiment of the present invention.

9 is a configuration diagram of a light emitting display device employing a transistor according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 transistor 110 a semiconductor layer

120: channel 130: source / drain electrodes

140: drain / source electrode 150: non-channel region

160: gate electrode

300: pixel 310: scanning line

320: data line 330: power line

340: First transistor 350: Capacitor

360: second transistor 370: light emitting element

700: light emitting display device 710: scan driver

720: data driver 730: image display unit

740 pixels

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to transistors, pixels, and light emitting displays. More particularly, the present invention relates to transistors having multiple channels, and to pixels and light emitting displays that can improve image quality of display devices by increasing uniformity of transistors in panels.

In general, an organic light emitting diode display is a self-luminous display that electrically excites fluorescent or phosphorescent organic compounds to emit light, and can be driven at a low voltage, is easy to thin, and is pointed out in a liquid crystal display such as a wide viewing angle and a fast response speed. It is attracting attention as the next generation display that can solve the problem.

The organic light emitting diode display is classified into an active matrix (AM) method (hereinafter referred to as an active driving method) and a passive matrix (PM) method according to the driving method thereof. Among them, the organic light emitting diode display of the active driving method includes at least two thin film transistors (hereinafter, referred to as TFTs) for each pixel. These thin film transistors are used as switching elements for controlling the operation of each pixel and as driving elements for driving the pixels.

The above-described thin film transistor includes a semiconductor layer having a drain region and a source region doped with a high concentration of impurities on a substrate, and a channel region formed between the drain region and the source region, a gate insulating film formed on the semiconductor layer, and a gate A gate electrode formed over the channel region of the semiconductor layer with an insulating film interposed therebetween, and a drain electrode and a source electrode connected to the drain region and the source region through a contact hole with an interlayer insulating film interposed therebetween on the gate electrode.

On the other hand, when the uniformity of the characteristics of the driving transistor in the panel of the organic light emitting display of the active driving method decreases, random mura increases in the panel, and according to the excimer laser annealing (ELA) line according to the manufacturing process. Mura appears and the picture quality deteriorates. The nonuniformity in the characteristics of the above-described driving transistor is caused by the distribution of the uneven energy generated unexpectedly in the laser beam and the direction of travel of the laser beam of the ELA in the ELA process. This increases the nonuniformity for the drive transistors in the panel.

Accordingly, in the organic light emitting diode display of the conventional active driving method, various compensation circuits are applied to each pixel circuit as a method for improving the uniformity of the driving transistor to compensate for the threshold voltage of the driving transistor.

However, the above-described conventional method has a problem that the pixel is complicated, the aperture ratio is decreased, and the yield is reduced by the complicated pixel structure.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to form a current movement path to another channel region even when a high density defect portion is increased in a specific channel region of a transistor due to unstable conditions in the manufacturing process. It is to provide a transistor that can keep the overall current flow substantially constant.

Another object of the present invention is to provide a light emitting display device and a pixel thereof that can improve image quality by employing a transistor having a channel having multiple current movement paths.

In order to achieve the above object, according to an aspect of the present invention, a channel, a channel formed in a closed loop shape on the substrate, and having at least two current movement paths and a source and a drain connected to both ends of the channel. Provided is a transistor including a first semiconductor layer having a gate, a gate insulating layer formed in contact with the channel, and a gate facing the channel with the gate insulating layer interposed therebetween.

Preferably, the above-described transistor further includes a second semiconductor layer which forms an additional current path in a bridge shape inside the first semiconductor layer.

The second semiconductor layer may interconnect the source and the drain. In addition, the second semiconductor layer may interconnect the current movement paths. In addition, the second semiconductor layer may connect at least one of the source and the drain and at least one of the current paths. In addition, the second semiconductor layer may be formed in a T shape. In addition, the second semiconductor layer may interconnect the source, the drain, and the current path. In addition, the second semiconductor layer may have a cross shape.

In addition, the first and second semiconductor layers are formed of a polysilicon layer. In addition, the first and second semiconductor layers are formed by a crystallization process of crystallizing an amorphous silicon layer. In addition, the crystallization process may include an excimer laser annealing process.

According to another aspect of the present invention, a first transistor for transmitting a data signal, a capacitor for storing a voltage corresponding to the data signal, a second transistor for supplying a current corresponding to the voltage of the capacitor, and the current A second light emitting element comprising a light emitting device correspondingly emitting light, wherein the second transistor is formed in a closed loop shape on a substrate and has a channel having at least two current paths and a source and a drain connected to both ends of the channel; A pixel of a light emitting display device including a semiconductor layer, a gate insulating layer formed in contact with the channel, and a gate facing the channel with the gate insulating layer interposed therebetween is provided.

Preferably, the above-described pixel of the light emitting display device includes a second semiconductor layer that forms an additional current path in a bridge shape inside the first semiconductor layer.

According to another aspect of the present invention, a plurality of scan lines for transmitting a scan signal, a plurality of data lines for transmitting a data signal, and a transistor according to an embodiment of the present invention, the plurality of scan lines and the plurality of A light emitting display device including a plurality of pixels connected to data lines, respectively, is provided.

Preferably, the pixel includes a first transistor for transmitting a data signal, a capacitor for storing a voltage corresponding to the data signal, a second transistor for supplying a current corresponding to the voltage of the capacitor, and the current. It includes a light emitting element for emitting light. In addition, the light emitting device includes an organic light emitting device having an organic material as a light emitting layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, parts irrelevant to the present invention have been omitted for clarity, and like reference numerals denote like parts throughout the specification.

1 is a plan view of a transistor according to an embodiment of the present invention. In the present embodiment, the transistor 100 may be formed of a thin film transistor.

Referring to FIG. 1, the transistor 100 according to an embodiment of the present invention may maintain substantially the entire current flow even when a high density defect occurs in a channel in a manufacturing process. To this end, the transistor 100 includes a channel 120 having multiple current movement paths and a semiconductor layer 110 having a source 116 and a drain 118 connected across the channel 120. In addition, the transistor 100 includes a gate electrode 160 facing the channel 120 with a gate insulating layer (not shown) therebetween.

In addition, the semiconductor layer 110 is formed in a window shape having a plurality of non-channel regions 150. In detail, the semiconductor layer 110 includes a first semiconductor layer 112 forming a closed loop in a substantially rectangular ring shape, and a second semiconductor forming at least one bridge inside the first semiconductor layer 112. Layer 114. The first semiconductor layer 112 includes a source region 116 and a drain region 118 formed in a predetermined region of the semiconductor layer 110 in which the source region 116 is not formed. As shown in FIG. 1, the second semiconductor layer 114 may include a left region and a right region of the first semiconductor layer 112, a source region 116, and a drain region 118 in the center region of the second semiconductor layer 114. First, second, third, and fourth bridges 114a, 114b, 114c, and 114d for respectively connecting the first and second bridges.

The semiconductor layer 110 also includes a channel 120 having multiple current movement paths, and a source region 116 and a drain region 118 connected to opposite ends of the channel 120. The channel 120 is formed in most regions of the window-shaped semiconductor layer 110 except for the source region 116 and the drain region 118. In addition, the channel 120 may include a first current movement path 120a, a second current movement path 120b, a third current movement path 120c, and a fourth current between the source region 116 and the drain region 118. And a current movement path by the movement path 120d, the fifth current movement path 120e, the sixth current movement path 120f, and a combination thereof. The first current movement path 120a represents a current movement path from the source region 116 to the drain region 118 through the left region of the first semiconductor layer 112 as shown in FIG. 1. Reference numeral 120b indicates a current movement path from the source region 116 to the drain region 118 through the right region of the first semiconductor layer 112, and the third current movement path 120c may refer to the source region 116 in the source region 116. The current movement path leading to the center region of the second semiconductor layer 114 is shown, and the fourth current movement path 120d is the second region in the middle region (the left region of the first semiconductor layer) on the first current movement path 120a. The current movement path leading to the center region of the semiconductor layer 114 is shown, and the fifth current movement path 120e is the second semiconductor layer in the middle region (the right region of the first semiconductor layer) on the second current movement path 120b. A sixth movement path leading to the central region of 114; Current movement path (120f) represents the current moving path to the drain region 118 in the central region of the second semiconductor layer 114.

The semiconductor layer 110 described above forms current movement paths 120a, 120b, 120c, 120d, 120e, and 120f between the source 116 and the drain 118 when a voltage is applied to the gate electrode 160. The source 116 is connected to the source electrode 130 through the first contact 132, and the drain 118 is connected to the drain electrode 140 through the second contact 142. In addition, the semiconductor layer 110 is formed through a process of crystallizing amorphous silicon with poly silicon (hereinafter referred to as polycrystalline silicon). The semiconductor layer 110 is one of important factors for determining the electrical characteristics of the transistor.

The source electrode 130 and the drain electrode 140 are connected to the source region 116 and the drain region 118 of the semiconductor layer 110 through the first contact hole 132 and the second contact hole 142, respectively. . The location of the source 116, the source electrode 130, the drain 118, and the drain electrode 140 may be determined according to the type of the transistor.

The gate electrode 160 is formed to face the channel 120 with a predetermined insulating layer interposed therebetween. The gate electrode 160 may be formed in a size and shape similar to a region in which the channel 120 is formed in the semiconductor layer 110 or in a size and shape including a region in which the channel 120 is formed.

Meanwhile, in the above description, the second semiconductor layer 114 of the semiconductor layer 110 has been described to form one cross bridge. However, the second semiconductor layer 114 of the semiconductor layer 110 according to an embodiment of the present invention may be formed in various shapes and shapes. In addition, the second semiconductor layer 114 may be formed to have two or more cross-shaped bridges in a horizontal direction and / or a vertical direction. This configuration can be appropriately selected depending on the size of the transistor.

2 is a plan view illustrating a case where a high density defect is generated in a transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the transistor 100 is formed of a thin film transistor. In addition, the transistor 100 includes a semiconductor layer 110 formed of polycrystalline silicon. This is because transistors are about 100 to 200 times faster because polycrystalline silicon has fewer surface defects than amorphous silicon.

The semiconductor layer 110 described above is crystallized through an excimer laser annealing (ELA) process. In this case, in the ELA process, the advancing direction of the laser beam may be set in the vertical direction toward the vertical direction in addition to the horizontal direction toward the left and right directions of the semiconductor layer.

Meanwhile, the crystallinity of the semiconductor layer 110 is greatly influenced by the pulse to pulse stability of the laser beam of the ELA. In other words, in the process of crystallizing polycrystalline silicon through a laser annealing process, a plurality of layers formed in the panel are basically formed due to the advancing direction (first or second direction) of the laser beam and uneven energy distribution in the laser beam in the form of a line. Non-uniformity occurs in the characteristics of a thin film transistor (poly-TFT) formed of polycrystalline silicon. In addition, in an excimer laser annealing (ELA) process using a multi-mode laser beam, if an unexpected change in beam energy density occurs in the middle of the crystallization process, the transistor 100 may generate a semiconductor at a portion where the change in beam energy density occurs. The crystallinity of layer 110 is damaged. Accordingly, the driving transistor 100 according to the exemplary embodiment of the present invention may include a portion damaged by crystallinity due to a process variation for crystallizing polycrystalline silicon, similar to a general poly-TFT.

For example, as shown in FIG. 2, in the process of crystallizing the semiconductor layer of the transistor 100, high-density defects 220 and 230 may be generated at specific portions in the channel 120, and in this case, high density Defects 220 and 230 interfere with the current flow in channel 120.

However, in the transistor 100 according to the exemplary embodiment of the present invention, as shown in FIG. 2, when the first high density defect portion 220 is formed on the fourth current movement path 120d in the channel 120 and / Alternatively, even when the second high density defect portion 230 is formed on the third current movement path 120C, the first current movement path 120a, the second current movement path 120b, and the fifth current movement path 120e are provided. ) And combinations thereof maintain constant current flow across the transistor.

As described above, the transistor 100 according to an embodiment of the present invention forms a current movement path to another channel region even when a high density of defects are generated at a specific portion within a channel due to non-uniformity of a manufacturing process, and thus the overall current flow of the transistor. Is kept constant, thereby increasing the uniformity of the transistors in the panel. Therefore, when the transistor according to the present invention is employed in the light emitting display device, the image quality of the light emitting display device can be improved.

3 is a cross-sectional view of the transistor taken along the line III-III of FIG. 1. A manufacturing process of the transistor 100 according to an embodiment of the present invention will be described with reference to FIG. 3.

First, the buffer layer 103 is formed on the glass substrate or the insulating transparent substrate 102. For example, the buffer layer 103 is formed of a silicon oxide film with a thickness of about 3000 m 3. Next, amorphous silicon is formed on the buffer layer 103. For example, amorphous silicon is deposited and dehydrogenated by plasma enhanced chemical vapor deposition (PECVD). In addition, amorphous silicon is polycrystalline through a laser scanning process. The laser beam applied in laser scanning has, for example, a rectangular cross section of about 200 to 250 mm in the long direction and about 0.25 to 1.5 mm in the unidirectional direction. In addition, in the case of a large area panel, the laser beam is irradiated superimposed for polycrystallization of amorphous silicon. This is because the energy deviation between the laser beam irradiation areas can be minimized in the process of polycrystallizing large-area amorphous silicon.

Meanwhile, a method of forming polycrystalline silicon using amorphous silicon is implemented by depositing pure amorphous silicon (intrinsic amorphous silicon) in a thickness of about 500 통해 through LPCVD (low pressure chemical vapor deposition) method in addition to PEDVD method and then crystallizing it. Can be.

Next, the semiconductor layer 110 is patterned into a window shape (see FIG. 1) through an etching process using a photoresist mask having a predetermined pattern.

Next, a gate insulating film 104 is formed on the entire upper surface of the patterned semiconductor layer 110. The gate electrode 160 is formed on the gate insulating layer 104. In this case, the gate electrode 160 is formed to face the channel 120 of the semiconductor layer 110. Here, the gate electrode 160 includes a gate of the transistor 100.

Next, impurity ions are implanted into a predetermined region of the patterned semiconductor layer 110 using the gate of the transistor 100 as a mask. Here, the predetermined region into which the impurity ions are implanted is formed of the source region 116 and the drain region 118. The impurity ions to be implanted are determined by the type of transistor. For example, phosphorus (P) is implanted in the case of an n-type thin film transistor, and boron (B) is implanted in the case of a p-type thin film transistor.

On the other hand, the source region 116 and the drain region 118 described above are first implanted with a low concentration of impurity ions using a gate as a mask, thereby forming a low concentration source region and a drain region, and then from the gate and the gate. A lightly doped drain (LDD) structure is formed in which a low concentration of source and drain regions is covered with a photoresist, and secondary impurities are implanted at a high concentration, thereby forming a high concentration of source and drain regions. Can be.

Next, an interlayer insulating layer 105 is formed on the structure including the gate electrode 160. In addition, a first contact hole and a second contact hole are formed in a predetermined region of the interlayer insulating layer 105 facing the source region 116 and the drain region 118 without the gate electrode 160 being formed. The first contact hole and the second contact hole may each be formed in plurality.

Next, a metal layer is formed on the interlayer insulating film 104 so as to form a predetermined gap with the gate electrode 160 without covering the gate electrode 160, and then patterned to form the source electrode 130 and the drain electrode 140. In this case, the source electrode 130 is electrically connected to the source region 116 through the first contact 132 formed by the first contact hole, and the drain electrode 140 is formed by the second contact hole. It is electrically connected to the drain region 118 through two contacts 142.

On the other hand, a passivation film or a protective film 106 for protecting the transistor 100 may be additionally formed on the structure described above.

4A to 4G are plan views illustrating modified examples of the transistor according to the exemplary embodiment of the present invention.

Referring to FIG. 4A, the transistor 100a includes a channel 120 having multiple current movement paths, and a semiconductor layer 112 having a source 116 and a drain 118 connected to both ends of the channel 120. It includes. In addition, the transistor 110a includes a gate electrode 160 facing the channel 120 with an insulating layer (not shown) therebetween.

The semiconductor layer 112 is formed in a window shape having one non-channel region 150. The non-channel region 150 is a region formed inside the channel 120 and does not have a current moving path. Specifically, the semiconductor layer 110 has a closed loop in the shape of a substantially rectangular ring. The semiconductor layer 112 includes a source region 116 and a drain region 118.

The semiconductor layer 112 also includes a channel 120 having multiple current movement paths, and a source region 116 and a drain region 118 connected to opposite ends of the channel 120. The channel 120 is formed in the semiconductor layer 112 in the regions except for the source region 116 and the drain region 118. In addition, the channel 120 forms a first current path 120a and a second current path 120b between the source region 116 and the drain region 118. The first current path 120a represents a current path from the source region 116 to the drain region 118 through the left side of the semiconductor layer 112 in FIG. 4A, and the second current path 120b. Denotes a current movement path from the source region 116 to the drain region 118 through the right region of the semiconductor layer 112.

With the above-described configuration, even when a high density defect portion occurs in one of the first and second current movement paths 120a and 120b, the transistor 110a performs the other current movement path. This allows the current flow to remain substantially constant.

The transistor 110a according to the present exemplary embodiment does not include the second semiconductor layer 114 formed in a bridge shape inside the first semiconductor layer 112 in the transistor 100 described above. However, the transistor 110a according to the present embodiment is according to the basic technical concept of the present invention, and is formed in a closed loop shape and has a channel having multiple current movement paths and a dumbbell facing the channel with an insulating layer interposed therebetween. It characterized in that it comprises a gate electrode of the shape.

Referring to FIG. 4B, the transistor 100b includes a channel 120 having multiple current movement paths, and a semiconductor layer 110 having a source 116 and a drain 118 connected to both ends of the channel 120. It includes. In addition, the transistor 110b includes a gate electrode 160 facing the channel 120 with an insulating layer (not shown) therebetween.

The semiconductor layer 110 is formed in a window shape having two non-channel regions 150. Specifically, the semiconductor layer 110 includes a first semiconductor layer 112 forming a closed loop in a substantially rectangular ring shape, and a second semiconductor layer 114 formed in a bridge shape inside the first semiconductor layer 112. Include. Here, the first semiconductor layer 112 includes a source region 116 and a drain region 118. The second semiconductor layer 114 connects the source region 116 and the drain region 118 in a bridge shape.

The semiconductor layer 110 also includes a channel 120 having multiple current movement paths, and a source region 116 and a drain region 118 connected to opposite ends of the channel 120. The channel 120 is formed in the first semiconductor layer 112 and the second semiconductor layer 114 except for the source region 116 and the drain region 118. The channel 120 also includes a first current movement path 120a, a second current movement path 120b, and a third current movement path 120c between the source region 116 and the drain region 118. The first current movement path 120a represents a current movement path from the source region 116 to the drain region 118 through the left region of the first semiconductor layer 112 in FIG. 4B. 120b represents a current movement path from the source region 116 to the drain region 118 through the right region of the first semiconductor layer 112, and the third current movement path 120c represents the second semiconductor layer 114. In FIG. 2, current flow paths directly connecting the drain region 118 to the source region 116 are illustrated.

 On the other hand, the third current movement path 120c is an intermediate region on the second current movement path 120b in the middle region (left region of the first semiconductor layer) on the first current movement path 120a (of the first semiconductor layer). It can be implemented as a current movement path connecting the right region).

On the other hand, the third current movement path 120c may be implemented to form a plurality of parallel bridges as shown in FIG. 4C. In this case, the semiconductor layer 110 includes a first semiconductor layer 112 having a closed loop shape, and a second semiconductor layer 114 having a first bridge 114a and a second bridge 114b. The first and second current movement paths 120a, 120b, 120c, and 120d are provided by the first and second semiconductor layers 112 and 114.

With the above-described configuration, the transistors 110b and 110c can maintain a substantially constant overall current flow by forming a current movement path through other portions in the channel, even when dense defects occur in specific portions in the channel. have.

Referring to FIG. 4D, the transistor 100d includes a channel 120 having multiple current movement paths, and a semiconductor layer 110 having a source 116 and a drain 118 connected to both ends of the channel 120. It includes. In addition, the transistor 110d includes a gate electrode 160 facing the channel 120 with an insulating layer (not shown) therebetween.

The semiconductor layer 110 is formed in a window shape having three non-channel regions 150. Specifically, the semiconductor layer 110 includes a first semiconductor layer 112 forming a closed loop in a substantially rectangular ring shape, and a T-shaped or Y-shaped bridge formed inside the first semiconductor layer 112. 2 semiconductor layer 114 is included. The first semiconductor layer 112 includes a source region 116 and a drain region 118. The second semiconductor layer 114 is directly connected to the drain region 118.

In addition, the semiconductor layer 110 includes a channel 120 having multiple current movement paths, and a source region 116 and a drain region 118 connected to both ends of the channel 120. The channel 120 is formed in most regions of the window-shaped semiconductor layer 110 except for the source region 116 and the drain region 118. In addition, the channel 120 may include a first current movement path 120a, a second current movement path 120b, a third current movement path 120c, and a fourth current between the source region 116 and the drain region 118. And a current movement path by the movement path 120d, the fifth current movement path 120e, and a combination thereof. The first current movement path 120a represents a current movement path from the source region 116 to the drain region 118 through the left region of the first semiconductor layer 112 in FIG. 4D. Reference numeral 120b represents a current movement path from the source region 116 to the drain region 118 through the right region of the first semiconductor layer 112, and the third current movement path 120c represents the first current movement path ( The current movement path from the middle region on the second semiconductor layer 114 to the center region of the second semiconductor layer 114 on the 120a, and the fourth current movement path 120d is the second semiconductor layer (in the middle region on the second current movement path 120b). The current movement path leading to the center region of the 114 is shown, and the fifth current movement path 120e indicates the current movement path from the center region of the second semiconductor layer 114 to the drain region 118. The fifth current movement path 120e may be implemented as a current movement path from the source region 116 to the center region of the second semiconductor layer 114.

With the above-described configuration, the transistor 110d generates a high density defect portion in any one, two, three or four current movement paths of the first to fifth current movement paths 120a, 120b, 120c, 120d, and 120e. If so, the current flow can be kept constant through the remaining four, three, two or one current path.

Meanwhile, the second semiconductor layer 114 may not only connect the drain region 118 and the first and second current movement paths 120a and 120b, but also the source region 116 and the first and second current movement paths. The gates 120a and 120b may be connected to each other, or the source region 116 and the drain region 118 may be configured to connect any one of the first and second current movement paths 120a and 120b.

Referring to FIG. 4E, the transistor 100e includes a channel 120 having multiple current movement paths, and a semiconductor layer 110 having a source 116 and a drain 118 connected to both ends of the channel 120. It includes. In addition, the transistor 110e includes a gate electrode 160 facing the channel 120 with an insulating layer (not shown) therebetween.

The semiconductor layer 110 is formed in a window shape having five non-channel regions 150. Specifically, the semiconductor layer 110 includes a first semiconductor layer 112 forming a closed loop in a substantially rectangular ring shape, and a second semiconductor layer forming a bridge having a plurality of intersections inside the first semiconductor layer 112. 114. The first semiconductor layer 112 includes a source region 116 and a drain region 118. As shown in FIG. 4E, the second semiconductor layer 114 includes the left and right regions of the first semiconductor layer 112, the source region 116, and the drain region 118 in the center region of the second semiconductor layer 114. First, second, third, fourth, and fifth bridges 114a, 114b, 114c, 114d, and 114e, respectively, respectively.

The semiconductor layer 110 also includes a channel 120 having multiple current movement paths, and a source region 116 and a drain region 118 connected to opposite ends of the channel 120. The channel 120 is formed in the window-shaped semiconductor layer 110 except for the source region 116 and the drain region 118. In addition, the channel 120 may include a first current movement path 120a, a second current movement path 120b, a third current movement path 120c, and a fourth current between the source region 116 and the drain region 118. And a current movement path by the movement path 120d, the fifth current movement path 120e, the sixth current movement path 120f, the seventh current movement path 120g, and a combination thereof. The first current movement path 120a represents a current movement path from the source region 116 to the drain region 118 through the left region of the first semiconductor layer 112 in FIG. 4F. Reference numeral 120b indicates a current movement path from the source region 116 to the drain region 118 through the right region of the first semiconductor layer 112, and the third current movement path 120c may refer to the source region 116 in the source region 116. The current movement path leading to the center region of the second semiconductor layer 114 is shown, and the fourth current movement path 120d is the second region in the middle region (the left region of the first semiconductor layer) on the first current movement path 120a. The current movement path leading to the center region of the semiconductor layer 114 is shown, and the fifth current movement path 120e is the second semiconductor layer in the middle region (the right region of the first semiconductor layer) on the second current movement path 120b. A sixth movement path leading to the central region of 114; And the seventh current movement paths 120f and 120g represent approximately parallel current movement paths extending from the center region of the second semiconductor layer 114 to the drain region 118.

Meanwhile, as shown in FIG. 4F, the third current movement path 120c is an intermediate region between the source region 116 and the second semiconductor layer 114 similarly to the sixth and seventh current movement paths 120f and 120g. It can be formed as a current movement path on the two bridges connecting each. In this case, the transistor 110f includes the first to seventh bridges 114a, 114b, 114c, 114d, 114e, 114f, and 114g in the second semiconductor layer 114, and the first and second semiconductor layers 112. , 114, has multiple current movement paths by first to ninth current movement paths 120a to 120g and combinations thereof.

By the above-described configuration, the transistors 110e and 110f can maintain the current flow substantially constant by forming a current movement path in other portions of the channel even when a high density of defect portions occur in specific portions in the channel. .

Referring to FIG. 4G, a transistor 100g includes a channel 120 having multiple current movement paths, and a semiconductor layer 110 having a source 116 and a drain 118 connected to both ends of the channel 120. It includes. In addition, the transistor 110h includes a gate electrode 160 facing the channel 120 with an insulating layer (not shown) therebetween.

The semiconductor layer 110 is formed in a window shape having four non-channel regions 150. Specifically, the semiconductor layer 110 includes a first semiconductor layer 112 forming a closed loop in a substantially rectangular ring shape, and a cross or X-shaped bridge inclined inside the first semiconductor layer 112. The second semiconductor layer 114 is formed. The first semiconductor layer 112 includes a source region 116 and a drain region 118. As shown in FIG. 4G, the second semiconductor layer 114 includes a source-side first left region and a drain-side second left region of the first semiconductor layer 112 and a first semiconductor in the center region of the second semiconductor layer 114. First, second, third, and fourth bridges 114a, 114b, 114c, 114d connecting the source side first right region and the drain side second right region of the layer 112, respectively.

The semiconductor layer 110 also includes a channel 120 having multiple current movement paths, and a source region 116 and a drain region 118 connected to opposite ends of the channel 120. The channel 120 is formed in the window-shaped semiconductor layer 110 except for the source region 116 and the drain region 118. In addition, the channel 120 may include a first current movement path 120a, a second current movement path 120b, a third current movement path 120c, and a fourth current between the source region 116 and the drain region 118. And a current movement path by the movement path 120d, the fifth current movement path 120e, the sixth current movement path 120f, and a combination thereof. The first current movement path 120a represents a current movement path connecting the drain region 118 through the left region of the source region 116 and the first semiconductor layer 112 in FIG. 4G, and the second current movement path. The path 120b represents a current movement path connecting the drain region 118 through the right region of the source region 116 and the first semiconductor layer 112, and the third current movement path 120c represents the source region 116. ) Represents a current movement path connecting the first left region adjacent to and the center region of the second semiconductor layer 114, and the fourth current movement path 120d represents the center region and the drain region of the second semiconductor layer 114. A current movement path connecting the second left region adjacent to 118 is shown, and the fifth current movement path 120e connects the first right region adjacent to the source region 116 and the center region of the second semiconductor layer 114. Represents the current movement path, and the sixth current movement path 120f is the second Connecting the center region and a second region adjacent the right side to the drain region 118 of the conductive layer 114 represents the current route.

With the above-described configuration, the transistor 110f can maintain the current flow substantially constant by forming a current movement path at another portion in the channel even when a high density defect portion is generated in the specific portion in the channel.

In the above-described embodiment, the transistor having the coplanar structure or the upper gate structure has been described. However, the present invention is not limited to such a configuration and can be applied to other structures such as a staggered structure or a lower gate structure. For example, the present invention includes a ring-shaped first semiconductor layer and / or a second semiconductor layer formed in a bridge shape inside the ring-shaped first semiconductor layer, and the first semiconductor layer and / or the second semiconductor layer. The present invention can be easily applied to thin film transistors having various structures including channels capable of forming multiple current movement paths.

5 is a layout diagram of pixels of a light emitting display device employing a transistor according to an exemplary embodiment of the present invention. FIG. 6 is an equivalent circuit diagram of the pixel of FIG. 5.

5 and 6, the pixel 300 represents a basic component for displaying an image in a light emitting display device, and controls an electroluminescent device (EL) 370 and the light emitting device 370. Pixel circuit 390 is included. In addition, the pixel 300 is connected to a first power line 330 transmitting a first power supply voltage Vdd and a power supply line (not shown) transmitting a second power supply voltage VSS, and scanning lines Sn and 310. Light is emitted in a predetermined color and at a predetermined level according to the scan signal transmitted through the data signal and the data signal transmitted through the data lines Dm and 320. To this end, the pixel 300 includes first transistors M1 and 340, capacitors C and 350, second transistors M2 and 360, and light emitting elements EL and 380.

The first and second transistors 340 and 360 may be implemented as thin film transistors, and have a gate, a source, and a drain, respectively. Capacitor 350 has a first electrode and a second electrode.

The first transistor 340 may include a gate connected to the scan line 310, a source connected to the data line 320 through the first contact hole 342, and a capacitor 350 through the second contact hole 344. A drain connected to the first electrode 352 is provided. The first transistor 340 samples the data signal applied to the data line 320 according to the scan signal applied to the scan line 310.

The capacitor 350 is connected to the drain of the first transistor 340 and is connected to the gate of the second transistor 360 and the first power line 330 through the third contact hole 356. And a second electrode 354 patterned together with a semiconductor layer (not shown) of the second transistor 360.

In addition, the capacitor 350 stores a predetermined voltage corresponding to the data signal transmitted through the data line 320 during the on period of the first transistor 340, and stores the second voltage during the off period of the first transistor 340. The voltage between the gate and source of transistor 360 is maintained at a stored voltage.

The second transistor 360 is implemented with a transistor according to an embodiment of the present invention. Accordingly, the second transistor 360 may maintain a constant current flow by forming a current movement path through another portion of the channel even when a high density of defect portions are generated in a portion of the channel in the crystallization process of the semiconductor layer. . This indicates that the transistors in the pixel according to the invention have high uniformity.

For example, the second transistor 360 includes a semiconductor layer formed in a window shape having four non-channel regions 368 as shown in FIG. 5. The semiconductor layer includes a first semiconductor layer formed in a closed loop shape and a second semiconductor layer formed in a bridge shape inside the first semiconductor layer. The semiconductor layer also includes a source 362 and a drain 364 connected to both ends of the channel 366 in the first semiconductor layer. The source 362 is connected to the source electrode 370 or the first power line 330 through the fourth contact hole 372, and the drain 364 is connected to the drain electrode 374 through the fifth contact hole 376. Is connected to.

In addition, the second transistor 360 includes a gate 378 facing the channel 366 with a predetermined insulating layer interposed therebetween. The gate 378 is connected to the first electrode 352 of the capacitor 350. In this configuration, the second transistor 360 generates a predetermined current by a voltage between the gate 378 and the source 362 connected to the first electrode 352 and the second electrode 354 of the capacitor 350, respectively. It supplies to the light emitting element 380.

The light emitting element 380 includes an organic thin film 386 and a first electrode 382 and a second electrode (not shown) formed on both surfaces of the organic thin film 386. Here, the first electrode 382 represents the anode electrode, and the second electrode represents the cathode electrode. The first electrode 382 is connected to the drain electrode 374 of the second transistor 360 through the sixth contact hole 384. The second electrode may be commonly connected to the cathode electrode of another light emitting device through an electrode made of indium tin oxide (ITO) or the like.

The organic thin film 386 described above includes a hole injecting layer and an electron injection layer on both sides of an emitting layer made of an organic material to improve injection characteristics of electrons and holes from the anode electrode 382 and the cathode electrode. It may be formed in a multilayer structure including an electron injecting layer. In addition, the organic thin film 386 may optionally include an electron transporting layer, a hole transporting layer, a hole blocking layer, or the like, in order to improve light emission characteristics of the light emitting device.

As described above, in the above-described pixel of the light emitting display device, even when a high-density defect portion is formed in a specific portion on the channel of the transistor 360 during the crystallization process, the entire current flows by forming a current movement path to another portion of the channel. Can be kept constant. Therefore, by using the pixel according to the present invention, it is possible to greatly improve the uniformity of characteristics of the driving transistor in the panel.

On the other hand, in the above-described embodiment, the transistor in the pixel is formed as a P-type transistor. However, the present invention is not limited to such a configuration, and the transistor in the pixel can be implemented with an n-type transistor.

In addition, in the above-described embodiment, the case where one switching transistor (first transistor) and one driving transistor (second transistor) is included in the pixel has been described. However, the present invention is not limited to such a configuration. For example, the pixel according to the present invention may include at least two driving transistors and / or at least two switching transistors. In addition, the pixel according to the present invention may be configured to include at least two light emitting elements connected to one driving transistor. In addition, the pixel according to the present invention may be driven in a sequential driving manner in which two light emitting devices are sequentially driven during one horizontal period. In this case, the at least two light emitting devices may display different colors. Furthermore, the pixel according to the present invention may include not only the pixel circuit of the basic voltage programming structure described above but also the pixel circuit of another voltage programming structure or the pixel circuit of the current programming structure. The pixel circuit of the current programming structure will be described later with reference to FIG. 8.

FIG. 7 is a cross-sectional view of the pixel taken along the line VII-VII of FIG. 5. Referring to FIG. 7, a cross-sectional structure of a pixel including a transistor according to an exemplary embodiment of the present invention will be described below.

First, a buffer layer 504 formed of a nitride film or an oxide film is formed on the insulating transparent substrate 502. The buffer layer 504 is for preventing impurities such as metal ions from diffusing into the semiconductor layer, especially the channel. The buffer layer 504 may be formed by a chemical vapor deposition (CVD) method.

Next, an amorphous silicon layer is coated on the substrate 502 on which the buffer layer 504 is formed, and heated at a temperature of about 430 ° C. to perform a dehydrogenation process to remove hydrogen components contained in the amorphous silicon layer. The dehydrogenated amorphous silicon layer is crystallized by a predetermined method to form the semiconductor layer 506. The semiconductor layer 506 includes a first and second semiconductor layers 506a having source and drain regions connected to the channel and both ends of the channel, and a third semiconductor layer 506b formed of one electrode of the capacitor 350. do.

The semiconductor layer 506 may be formed of solid phase crystallization (SPC), excimer laser crystallization (ELC / excimer laser anneal (ELA)), sequential lateral solidification (SLS), metal Crystallization is carried out by any one of crystallization methods such as metal induced crystallization (MIC) and metal induced lateral crystallization (MILC).

In addition, the semiconductor layer 506 is patterned in a predetermined pattern through a photoresist film (not shown) formed on the semiconductor layer 506 using physical and chemical reactions. In this case, the first and second semiconductor layers 506a are patterned in a window shape (see FIG. 1 or FIG. 5), and the third semiconductor layer 506b forming one electrode of the capacitor 350 is also patterned.

Subsequently, a gate insulating film 508 is formed on the substrate 502 on which the semiconductor layer 506 is formed, a gate electrode material 510 such as aluminum is deposited on the gate insulating film 508, and then patterned to form the gate electrode 510a. To form. At this time, the other electrode 510b of the capacitor 350 is also patterned together with the gate electrode 510a. Thereafter, impurity ions are implanted into predetermined regions of the first and second semiconductor layers 506a using the gate electrode 510a as a mask. In this case, predetermined regions of the first and second semiconductor layers 506a are formed of source and drain regions.

Next, an interlayer insulating layer 512 is formed on the structure, and first and second contact holes 512a and 512b are formed in the interlayer insulating layer 512 to expose source and drain regions, respectively. Thereafter, the metal layer 514 is entirely deposited and patterned to form a source / drain electrode 514a and a drain / source electrode 514b. The source / drain electrode 514a and the drain / source electrode 514b are connected to the source and drain regions through the first contact hole 512a and the second contact hole 512b. The source / drain electrodes 514a are connected to a power supply line.

Next, a planarization film 516 made of an organic material such as acrylic, polyimide, and BCB is formed on the structure. The planarization layer 516 includes a third contact hole 518a exposing the drain / source electrode 514b. Meanwhile, the planarization film 516 may be formed after forming a passivation film (not shown) made of SiO ₂ , SiNx, or the like on the structure.

Next, the anode electrode 520 is deposited and patterned on the planarization film 516. The anode electrode 520 is electrically connected to the drain / source electrode 514b through the third contact hole 518a.

Next, a pixel defining layer 522 is formed on the structure. The pixel defining layer 522 includes an opening 522a exposing the anode electrode 520. Thereafter, the organic light emitting material 524 is applied to the opening 522a. The cathode electrode 526 is formed on the structure to which the organic light emitting material 524 is coated.

With the above-described configuration, a transistor having a channel structure having multiple current movement paths, a capacitor electrically connected between the gate and the source of the transistor, and a light emitting element EL controlled by these transistors and the capacitor are formed.

On the other hand, in the above-described embodiment, a pixel including a transistor having a PMOS structure is mentioned. However, the present invention is not limited to such a configuration, and can be easily applied to pixels including transistors of NMOS structure. In the above-described embodiment, the lower electrode and the upper electrode of the capacitor are formed together at the time of forming the semiconductor layer and the gate electrode, but the present invention is not limited to such a configuration. For example, the capacitor may be formed to include a lower electrode formed on the same layer as the gate electrode and an upper electrode formed on the same layer as the source / drain electrode.

8 is a circuit diagram of another pixel that may employ a transistor according to an embodiment of the present invention.

Referring to FIG. 8, the pixel 300a includes a light emitting element EL and a pixel circuit 390a for controlling the light emitting element EL. The pixel circuit 390a includes first to fourth transistors M1, M2, M3, and M4, and first and second capacitors C1 and C2.

The first to fourth transistors M1, M2, M3, and M4 have a source, a drain, and a gate, respectively. Here, the source and the drain may be represented by the first electrode and the second electrode. The first and second capacitors C1 and C2 have a first electrode and a second electrode.

A gate of the first transistor M1 is connected to the first node N1, a source is connected to a power supply line for transmitting a power supply voltage Vdd, and a drain is connected to the second node N2. The first transistor M1 supplies a current corresponding to the voltage applied between the first electrode and the second electrode of the first capacitor C1 to the light emitting device EL during the on period of the fourth transistor M4.

In addition, the first transistor M1 is implemented as a transistor according to an embodiment of the present invention. In other words, the first transistor M1 includes a window-shaped semiconductor layer having multiple current movement paths. Accordingly, the first transistor M1 can maintain substantially the entire current flow by forming a current movement path through other portions of the channel even when a high density of defects generated in the manufacturing process occurs in a specific portion of the channel. .

The gate of the second transistor M2 is connected to the scan line Sn, the source is connected to the data line Dm, and the drain is connected to the first node N1. The second transistor M2 transmits a data signal transmitted through the data line Dm to the first node N1 in response to a scan signal applied to the scan line Sn.

The gate of the third transistor M3 is connected to the scan line Sn, the source is connected to the data line Dm, and the drain is connected to the second node N2. The third transistor M3 diode-connects the first transistor M1 in response to a scan signal applied to the scan line Sn.

The gate of the fourth transistor M4 is connected to the light emission control line En, the source is connected to the second node N2, and the drain is connected to the light emitting element EL. The fourth transistor M4 selectively or limitedly supplies the current from the first transistor M1 to the light emitting element EL in response to the light emission control signal applied to the light emission control line En.

The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to a power supply line that transmits a power supply voltage Vdd. In addition, the first electrode of the first capacitor C1 is connected to the gate of the first transistor M1, and the second electrode is connected to the source of the first transistor M1. The first capacitor C1 may store a voltage corresponding to the threshold voltage of the first transistor M1 in the on periods of the second and third transistors M2 and M3. In addition, the first capacitor C1 stores a voltage corresponding to the data current transmitted through the data line Dm in the on period of the second transistor M2. In addition, the first capacitor C1 maintains the voltage between the gate sources of the first transistor M1 at the stored voltage in the off period of the second and third transistors M2 and M3.

The first electrode of the second capacitor C2 is connected to the first node N1, and the second electrode is connected to a boost line that transmits a boost voltage. The second capacitor C2 boosts the gate voltage of the first transistor M1 to downscale the current. In other words, the second capacitor C2 increases the voltage of the first node N1 with the low voltage formed at the first node N1 due to the writing of a large current as the voltage of the boost line increases.

As described above, when the pixel including the transistor according to the exemplary embodiment of the present invention is used, in the case of an active matrix type light emitting display device, even when a high density defect portion is formed in a specific portion of a channel of the driving transistor, the overall current flow of the transistor It is possible to improve the image quality by increasing the uniformity of the driving transistor in the panel by keeping the constant.

In the above-described embodiment, the pixel of the light emitting display device has been described, but the present invention is not limited to such a configuration. For example, the present invention can be easily applied to pixels of other display devices such as TFT-LCDs using a driving thin film transistor.

9 is a configuration diagram of a light emitting display device employing a transistor according to an embodiment of the present invention.

Referring to FIG. 9, the light emitting display device 500 displays an image by an active matrix driving method. This driving method can easily control each pixel to display natural colors with excellent image quality. To this end, the light emitting display device 500 includes a scan driver 510, a data driver 520, and an image display unit 530. The image display unit 530 includes a plurality of pixels 540. Each pixel 540 includes a light emitting element EL and a pixel circuit 542 for controlling the light emitting element EL. The pixel circuit 542 includes a driving transistor according to an embodiment of the present invention. In Fig. 9, the driving transistor is enlarged and displayed.

Specifically, the light emitting display device 500 includes n scan lines S1, S2,..., Sn extending from the scan driver 510 in the horizontal direction of the image display unit 530, and an image from the data driver 520. An image having m data lines D1, D2, D3, ..., Dm extending in the vertical direction of the display portion 530, and n x m pixels 540 connected to each scan line and each data line. The display unit 530 is included.

The scan driver 510 supplies a scan signal to the scan lines S1, S2, ..., Sn. The scanning signal is at least one of a single scan method, a progressive scan method, a dual scan method, an interlaced scan method, or another scanning method. 540 is passed.

The data driver 520 supplies a data signal to the data lines D1, D2, D3, ..., Dm. The data signal includes a data voltage. The data signal may be implemented as a data current according to the configuration of the pixel circuit.

The image display unit 530 includes a power supply line (not shown) that transmits a power supply voltage Vdd, a plurality of scan lines S1, S2, ..., Sn, and a plurality of data lines D1, D2, D3, ... , Dm) and a plurality of pixels 540. The image display unit 530 is formed on a substrate (not shown) such as an insulating transparent substrate.

The scan driver 510 and / or the data driver 520 may be directly mounted on a substrate on which the image display unit 530 is formed, and the scan driver 510 and / or the data driver 520 may be mounted on the substrate on which the image display unit 530 is formed. It can be replaced by a drive circuit formed of layers. On the other hand, the scan driver 510 and / or the data driver 520 may be formed in a chip on flexible board, or chip on film (COF) structure. In other words, the scan driver 510 and / or the data driver 520 may be mounted in the form of a chip or the like on a flexible printed circuit (FPC) or a film that is bonded to and electrically connected to a substrate. Can be.

The pixel 540 displays a predetermined color and luminance according to a data signal transmitted through the data lines D1, D2, D3,..., And Dm. In addition, the pixel 540 includes at least a switching transistor, a capacitor, a driving transistor, and a light emitting element. Here, the driving transistor 543 is implemented as a transistor according to an embodiment of the present invention, as shown in an enlarged view in FIG. 9. Therefore, when each semiconductor layer 540 is formed through a crystallization process such as ELA, a high density defect portion is formed in a specific channel portion of the semiconductor layer of the driving transistor. The image quality of the light emitting display device 500 may be improved by forming a current movement path to maintain a constant current flow, or by increasing the uniformity of the driving thin film transistor in the image display unit 530.

On the other hand, in the above embodiment, the transistor has been described as having a source, a drain, and a gate. However, the present invention includes a first electrode, a second electrode, and a third electrode, and can control the amount of current flowing from the second electrode to the third electrode by a voltage applied between the first electrode and the second electrode. It can be implemented as an active device.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.

According to the present invention, the uniformity of the driving transistor in the pixel circuit for controlling the light emitting element can be increased. In addition, since the circuit for compensating the threshold voltage of the driving transistor can be omitted, the aperture ratio can be increased. In addition, even in the case where a high density of defects are generated during manufacturing of the driving transistor, the driving transistor keeps the overall current flow substantially constant, thereby reducing the yield reduction due to the failure of the driving transistor. In addition, the image quality of the light emitting display device can be improved by using the above-described driving transistor.

Claims (19)

Board; A first semiconductor layer having a channel having at least two current movement paths, a source and a drain connected to both ends of the channel, and formed in a closed loop shape on the substrate; A gate insulating layer formed in contact with the channel; And And a gate facing the channel with the gate insulating layer interposed therebetween. The method of claim 1, And a second semiconductor layer forming an additional current movement path inside the first semiconductor layer. The method of claim 2, And the second semiconductor layer interconnects the source and the drain. The method of claim 2, And the second semiconductor layer interconnects the current paths. The method of claim 2, And the second semiconductor layer connects at least one of the source and the drain and at least one of the current paths. The method of claim 2, The second semiconductor layer is a transistor formed in a T-shape. The method of claim 2, And the second semiconductor layer interconnects the source and the drain with the current movement path. The method of claim 2, The second semiconductor layer has a cross shape. The method of claim 2, And the first and second semiconductor layers are formed of a polysilicon layer. The method of claim 2, And the first and second semiconductor layers are formed by a crystallization process of crystallizing an amorphous silicon layer. The method of claim 10, Wherein said crystallization process comprises an excimer laser annealing process. A first transistor for transmitting a data signal; A capacitor for storing a voltage corresponding to the data signal; A second transistor supplying a current corresponding to the voltage of the capacitor; And Including a light emitting device for emitting a light corresponding to the current, The second transistor includes a channel having at least two current movement paths, a source and a drain connected to both ends of the channel, and a first semiconductor layer formed in a closed loop shape on a substrate, and formed in contact with the channel. And an insulating layer and a gate facing the channel with the insulating layer interposed therebetween. The method of claim 12, And a second semiconductor layer forming an additional current movement path inside the first semiconductor layer. A plurality of scan lines transferring scan signals; A plurality of data lines for transmitting data signals; And A light emitting display device comprising the transistor according to any one of claims 1 to 11 and comprising a plurality of pixels connected to the plurality of scan lines and the plurality of data lines, respectively. The method of claim 14, And a scan driver configured to supply the scan signals to the plurality of scan lines. The method of claim 14, And a data driver configured to supply the data signals to the plurality of data lines. The method of claim 14, The pixel, A first transistor for transmitting a data signal; A capacitor for storing a voltage corresponding to the data signal; A second transistor supplying a current corresponding to the voltage of the capacitor; And A light emitting display device comprising: a light emitting device that emits light corresponding to the current. The method of claim 14, The pixel, A first transistor having a first electrode, a second electrode, and a gate, wherein the first electrode is connected to the first power line, and the second electrode is connected to a second node; A second transistor having a first electrode, a second electrode, and a gate, wherein the first electrode is connected to the data line, the second electrode is connected to a first node, and the gate is connected to the scan line; A third transistor having a first electrode, a second electrode, and a gate, wherein the first electrode is connected to the data line, the second electrode is connected to a second node, and the gate is connected to the scan line; A fourth transistor having a first electrode, a second electrode, and a gate, wherein the first electrode is connected to the second node, and the gate is connected to an emission control line; A first capacitor having a first electrode and a second electrode, the first electrode connected to the first node, and the second electrode connected to a first power line; A second capacitor having a first electrode and a second electrode, wherein the first electrode is connected to the first node, and the second electrode is connected to a boost line; And And a light emitting device having a first electrode and a second electrode, wherein the first electrode is connected to the second electrode of the fourth transistor, and the second electrode is connected to a second power line. The method of claim 18, The light emitting device includes an organic light emitting device having an organic material as a light emitting layer.

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