KR100617083B1 - apparatus for controlling system clock in digital broadcasting receiver - Google Patents

Abstract

The present invention provides a system clock control apparatus of a digital broadcast receiver that can stabilize the operation of the STC counter without restoring the system clock when demultiplexing programs having different time references in a multi-channel system. A reference counter for counting a reference system clock between the PCR input intervals in the restored system clock, a storage for temporarily storing PCR of a program to be controlled among the input PCRs, and a current PCR input time and a previous time stored in the storage A second subtractor for calculating a system clock count by calculating a PCR difference between PCR input time points, and a system clock speed counted at the reference counter and a system clock speed counted at the second subtractor, and calculating a difference between two clock speeds; A first subtractor for calculating an error, and the first subtractor A divider for obtaining the required distortion cycles for the error magnitudes of the PCR and the system clock through the difference, a mux for outputting a value defined according to the error calculated by the first subtractor for each distortion cycle obtained from the divider, and the mux And an adder for outputting the corrected STC counter value by adding the outputted value from the restored system clock inputted from the outside.

STC counter, PCR, system clock

Description

Apparatus for controlling system clock in digital broadcasting receiver

1 is a diagram illustrating a structure of a decoder for processing a conventional program.

2 is a graph showing the error of the STC and PCR generated when processing a conventional multi-program

3 is a block diagram showing a system clock control apparatus for a digital broadcast receiver according to the present invention.

* Explanation of symbols for main parts of the drawings

100: reference counter 200: storage

310, 320: Subtractor 400: Divider

500: mux control unit 600: mux

700: adder

The present invention relates to a digital broadcast receiver, and more particularly, to an apparatus for controlling a system clock of an STC counter used in a digital broadcast receiver.

In a digital broadcast receiver, a system decoder demultiplexes one program from an input stream and sends audio and video data of the program to each decoder, and a demultiplexer of audio and video. It consists of a system time clock (STC) counter that generates system clock information for lip synchronization.

At this time, the STC counter operates with a system clock that matches the encoder restored using the transmitted PCR. In this case, the PCR is information for setting the STC value of the system decoder to the value intended by the encoder.

FIG. 1 is a diagram illustrating a structure of a decoder for processing a program. An STC is processed using a channel processor 10 for processing input channel data and a system clock restored from data processed by the channel processor 10. A system decoder 20 for performing synchronization at the counter 22 and restoring a system clock in the TS stream demultiplexer 21, and an audio decoder 30 for decoding audio and video using the recovered data of the system clock. And video decoder 40.

As shown in Fig. 1, the structure of the decoder is composed of one TS stream demultiplexer 21 and an STC counter 22 to process one program.

Therefore, when decoding a program input through two or more channels, such as a multichannel system, since each program has a different PCR, a decoder having the above structure must be operated for each program. At this time, the system clocks recovered from the PCR of each program are not equal to each other.

In other words, the system clock frequency recovered from the PCR of the program and the value of the STC counter running on the recovered system clock prevent the overflow or underflow of each audio / video decoder buffer and Since it is used for lip synchronization, it is closely related to the display clock of the decoders.

In this case, when each program is displayed on a separate display unit, a separate system clock recovery circuit may be provided for each program according to each display unit. However, when only one display unit is used, only one system clock may be used.

That is, programs to be demultiplexed through multiple channels have different time bases, and the system clocks of the encoders encoding the time bases are all different.

Therefore, the decoder must recover all system clocks for each program, but if only one display unit is used, it is inevitable to recover only one system clock and use it in multiple programs. At this time, the increase and decrease of the STC counter of another program using the reference system clock is shown in FIG.

As shown in FIG. 2, the PCR of the first program having the encoder clock having 27 MHz + α is set as the reference encoder clock. When the system clock having the encoder clock of another second program of 27 MHz −β is present, the second Since the system clock of the program operates the STC counter by using the PCR of the reference encoder clock of the first program, an error occurs for each program, thereby causing repetition or skipping.

Accordingly, the present invention has been made to solve the above problems, a system of a digital broadcast receiver that can stabilize the operation of the STC counter without restoring the system clock when demultiplexing programs having different time references in a multi-channel system Its purpose is to provide a clock control device.

Features of the system clock control apparatus of the digital broadcast receiver according to the present invention for achieving the above object is a reference counter for counting the reference system clock between the PCR input interval from the restored system clock input from the outside, and the input A storage unit for temporarily storing PCR of a program to be controlled during PCR, a second subtractor for calculating a count of a system clock by calculating a PCR difference between a current PCR input time point and a previous PCR input time point stored in the storage unit, and the reference A first subtractor that calculates an error between two clock speeds by calculating a reference system clock speed counted by a counter and a system clock speed counted by the second subtractor, and a PCR and system through the error calculated by the first subtractor. A divider for calculating the required distortion cycle for the error magnitude of the clock; A mux for outputting a value defined according to the error calculated by the first subtractor for each true distortion cycle, and a STC counter value corrected by adding a value output from the mux to a restored system clock input from an external source; It is configured to include an adder.

Preferably, the mux control unit further comprises a mux control unit configured to control the mux through the sign of the error value calculated by the first subtractor.

Preferably, the divider calculates a distortion cycle Z by dividing a reference system clock output from the reference counter by an error value Y calculated by the second subtractor.

Preferably, the storage unit stores a first storage unit for storing the first PCR currently input, and a first storage unit stored in the first storage unit before storing the second PCR in the first storage unit when the next second PCR is input. It characterized in that it comprises a second storage unit for storing one PCR.

Preferably, the mux outputs +2 if the sign of the error value calculated by the first subtractor for each distortion cycle is positive (+), +0 if negative (-), and + if zero (0) It is characterized by outputting 1.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

A preferred embodiment of a system clock control apparatus of a digital broadcasting receiver according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating an apparatus for controlling a system clock of a digital broadcast receiver according to the present invention.

As shown in FIG. 3, when a system clock restored to 27 MHz from an external source is input, a reference counter 100 for counting a reference system clock between PCR input sections and a PCR of a program to be controlled among PCR inputted from a channel are temporarily And a second subtractor 320 that calculates a count of a system clock by calculating a PCR difference between a current PCR input time point and a previous PCR input time point stored in the storage unit 200. A first subtractor 310 calculating an error between the two clock speeds by calculating the reference system clock speed counted by the reference counter 100 and the system clock speed counted by the second subtractor 320, and The divider 400 obtains a distortion cycle necessary for the error magnitude of the PCR and the system clock through the error calculated by the first subtracter 310. Subsequently, the mux 600 outputs a value defined according to the error calculated by the first subtractor 310 for each distortion cycle obtained by the divider 400, and the mux 600 is the first subtractor. The MUX control unit 500 is controlled through the sign of the error value calculated in step 310, and the STC counter value corrected by adding the value output from the MUX 600 with the restored system clock input from the outside. It is composed of an adder 700.

At this time, the storage unit 200 is composed of two registers, and stores only the first PCR currently input (CP) (210), and when the next second PCR is input to the CP (210) It consists of a PP (previous PCR) 220 for storing the first PCR input before storing the 2 PCR.

The mux 600 adds +2 to the adder 700 when the sign of the error value calculated by the first subtractor 310 is positive (+) under control of each distortion cycle of the mux controller 500. Output, and if it is negative, it outputs +0, and if it is zero, it outputs +1.

The operation of the system clock control apparatus of the digital broadcasting receiver according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the reference counter 100 for counting the reference system clock between the PCR input sections is configured. The reference counter 100 is initialized when the PCR is input, counted by the reference system clock to count the reference system clock until the next PCR input, and is initialized again.

Then, the storage unit 200 is composed of two registers for storing the PCR of the program to be controlled among the PCR input from the channel. Thus, the current input PCR is stored in the C.P (current PCR) 210. Then, when the next PCR is input, the value of C.P is transferred to P.P (previous PCR) 220, and the current PCR is stored in C.P 210 again.

Next, the PCR difference between the current PCR input point and the previous PCR input point is calculated using the second subtractor 320 to calculate a count of the system clock.

That is, the difference X (between T1 and T0) of the PCR in the section T1 (current PCR input point) and T0 (previous PCR input point) in which the PCR is input may be expressed by Equation 1 below.

X = C.P-P.P

As shown in Equation 1, X is a count of a system clock that encodes a corresponding program in a period between T1 and T0. At this time, the reference counter 100 is referred to as the reference system clock count between T1 and T0.

Accordingly, an error between the system clock size and the reference system clock size of the corresponding program can be found using the clock size stored in the reference counter 100 between T1 and T0 and the X value calculated by the second subtracter 320. Can be.

The method for obtaining the error between the PCR and the system clock speed is described in more detail as follows.

First, as shown in Equation 2, the first subtractor 310 obtains a difference between the reference system clock size ref_counter stored in the reference counter 100 and the system clock size X calculated by the second subtractor 320. In this case, define the obtained value as Y.

Y = ref_counter-X.

The sign of the value Y calculated by the first subtractor through Equation 2 indicates a relative speed between the system clock and the reference system clock of the corresponding program. In other words, if the sign of Y is positive, the reference system clock is faster, and if it is negative, it can be determined that it is slower.

The absolute value of Y is the difference between the increment of PCR and the system clock counter between T1 and T0.

Next, the divider 400 calculates a value Z of how many cycles it takes when the PCR and the system clock counter differ by one. This is calculated through the following equation (3).

Z = ref_counter / Y

That is, the divider 400 can obtain a distortion cycle that requires control of the PCR of the program and the error of the system clock.

The STC counter can be controlled according to the number of distortion cycles calculated by the divider 400 and the sign of Y calculated by the first subtractor.

That is, since the operation of the basic STC counter is an incremental adder based on the reference system clock, the values of +0, +1, and +2 are set in the mux 600, and the mux controller 500 determines that the divider ( When the sign of Y output from the first subtractor 310 is positive (+) for each distortion cycle output from 400, the MUX 600 is controlled to input (+2) to the adder 700.

In addition, the mux controller 500 controls the adder by controlling the mux 600 when the sign of Y output from the first subtractor 310 is negative for each distortion cycle output from the divider 400. Enter (+0) for (700).

In other cases, the mux control unit 500 controls the mux 600 to input +1.

At this time, the +0, +1, +2 defined in the mux 600 is a value set by the system user randomly, and is not limited thereto. Therefore, it can be changed according to the state of the system and the degree of error.

As such, when the defined value is input to the adder, the adder 700 adds the value output from the mux 600 to the restored system clock input from the outside to output the corrected STC counter value.

As a result, the same effect as controlling the system clock is achieved.

The proposed method calculates the error using the PCR value of the input program and the reference system clock value, and controls the operation of the STC counter of the corresponding program based on the PCR value of the input program. Try to achieve the same effect as adjusting the clock.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

The apparatus for controlling a system clock of a digital broadcast receiver according to the present invention as described above has the following effects.

First, the stability of audio and video lip-synchorinization can be improved by operating the STC counter to match the system clock size of the program without recovering the system clock.

Second, it operates without a separate S / W and can be adopted in a multi-channel system.

Claims (6)

A reference counter for counting the reference system clock between the PCR input intervals from the restored system clock inputted from the outside; A storage unit for temporarily storing PCR of a program to be controlled among the input PCRs; A second subtractor for calculating a count of a system clock by calculating a PCR difference between a current PCR input time point and a previous PCR input time point stored in the storage unit; A first subtractor for calculating an error between two clock speeds by calculating a reference system clock speed counted by the reference counter and a system clock speed counted by the second subtractor; A divider for obtaining a necessary distortion cycle for the error magnitude of the PCR and the system clock through the error calculated by the first subtractor; A mux for outputting a value defined according to an error calculated by the first subtractor for each distortion cycle obtained by the divider; And an adder configured to add a value output from the mux to a restored system clock input from an external device and output a corrected STC counter value. The method of claim 1, And a mux control unit configured to control the mux through a sign of an error value calculated by the first subtractor. The method of claim 1, And the divider calculates a distortion cycle (Z) by dividing a reference system clock magnitude output from the reference counter by an error value (Y) calculated by the second subtractor. The method of claim 1, The storage unit and the first storage unit for storing the first PCR currently input; And a second storage unit for storing the first PCR stored in the first storage unit before storing the second PCR in the first storage unit when the second PCR is input. System clock control device. The method of claim 4, wherein And the first storage unit and the second storage unit comprise registers. The method of claim 1 The mux outputs +2 if the sign of the error value calculated by the first subtractor for each distortion cycle is positive (+), +0 if negative (-), and +1 if zero (0) And a system clock control device for a digital broadcast receiver.

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