KR100616230B1 - Three-Dimensional All-Around Gate Field Effect Transistor Structures and Method for Manufacturing - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a field effect transistor and its structure, and more particularly, to a method for fabricating a three-dimensional field effect transistor having a gate formed over a silicon channel, and a field effect transistor fabricated by the fabrication method.

In accordance with an embodiment of the present invention, a method of fabricating a 3D field effect transistor having a gate formed on a front surface of a silicon channel includes: (a) sequentially forming a silicon substrate, a lower insulating layer, silicon, and a hard mask; (b) anisotropically etching silicon using the mask pattern as a mask to form a pattern of a silicon channel in which a channel is to be formed and a silicon region in which a source / drain is to be formed; (c) forming an additional mask that may serve as an etch stop layer when etching the lower portion of the lower insulating layer or the silicon channel; (d) forming an entire surface of the silicon channel through the lower insulating layer under the silicon channel stop layer or the lower portion of the silicon channel; (E) growing a gate dielectric layer around the exposed silicon channel and depositing a gate material, and then forming a gate region to fabricate a field effect transistor having a gate formed on the entire surface of the silicon channel; It is made, including.

Field effect transistor, front gate, three-dimensional structure, thin film channel, short channel effect

Description

Three-Dimensional All-Around Gate Field Effect Transistor Structures and Method for Manufacturing

FIG. 1 is a process perspective view showing a method for manufacturing a fin field effect transistor by a method of forming a gate according to the prior art on both sides of a fin.

2 is a gate region electron micrograph of a tri-gate transistor in which a gate according to the prior art surrounds three surfaces of a silicon channel.

3A is a process perspective view illustrating a method of fabricating a field effect transistor in which a gate according to the prior art surrounds a silicon channel in an omega form.

3B is an electron micrograph of the device fabricated by the fabrication method shown in FIG. 3A.

4 is a cross-sectional view illustrating a method of fabricating a fin field effect transistor using a bulk substrate according to the prior art.

5 is a cross-sectional view illustrating a method of fabricating a body-tied omega FinFET using a bulk substrate according to the prior art.

6A is a perspective view of a nanowire field effect transistor (nanowire FinFET) in which a silicon channel is rounded according to the prior art.

FIG. 6B is a gate region electron micrograph of the field effect transistor manufactured by the fabrication method shown in FIG. 6A.

7A is a process perspective view and a cross-sectional view sequentially illustrating a method of forming a gated field effect transistor on a silicon channel all-around according to an embodiment of the present invention.

FIG. 7B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 7A.

8A is an electron micrograph of a gate area according to an embodiment of the present invention.

8B is a cross-sectional view of the gate area illustrated to explain technical features according to an embodiment of the present invention.

FIG. 9A is a process perspective view sequentially illustrating a method of forming a field effect transistor having a gate formed on an entire surface of a silicon channel according to another exemplary embodiment of the present invention.

FIG. 9B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 9A.

10A is an electron micrograph of a gate region formed according to the method shown in FIG. 9.

FIG. 10B is a cross-sectional view of a gate area illustrated to explain technical features in accordance with another embodiment of the present invention.

FIG. 11A is a process perspective view sequentially illustrating a method of forming a field effect transistor having a gate formed on an entire surface of a silicon channel according to another exemplary embodiment of the present invention.

FIG. 11B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 11A.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for fabricating a field effect transistor and a structure thereof, and more particularly, to a method for fabricating a three-dimensional field effect transistor having a gate formed on a silicon channel all-around, and a field effect transistor fabricated by the method. will be.

At present, in order to lower the price and increase the performance of semiconductor devices, semiconductor device sizes have been continuously reduced in accordance with Moore's Law to enable high integration of semiconductor ICs.

However, as the channel length of the device is reduced to 100 nm or less, in the conventional field effect transistor, the potential of the channel is controlled not only by the gate but also by the drain, so that a leakage current flows between the source and the drain even when the device is turned off. .

In order to reduce this short channel effect (to increase the channel potential control of the gate voltage to reduce the leakage current), a double gate structure in which gates are formed on both sides of a silicon channel formed perpendicular to the substrate to form a channel, is a conventional SOI (silicon- A silicon thin film field effect transistor structure using an on-insulator) CMOS (Complementary Metal Oxide Semiconductor) process method has been proposed.

Afterwards, a tri-gate transistor structure is used as a channel by forming a gate on the silicon channel face, an omega FinFET structure in which the gate surrounds the silicon channel in an omega form, and a variation in device characteristics between wafers is reduced. Structure and Formation of Fin Field Effect Transistor with Effective Inter-Device Isolation, Structure and Formation of Body-Tied Omega FinFET Using Bulk Substrate, Not SOI Substrate for Solving Heat Transfer Problem of Fin Field Effect Transistor, Various methods have been developed, such as the structure and formation method of a nanowire field effect transistor (nanowire FinFET) in which a silicon channel is rounded.

Thus, in order to improve the short channel effect and to manufacture smaller field transistors, gates are placed on the top / bottom or both sides of the channel instead of the two-dimensional structure in which the potential of the silicon channel is controlled by one gate electrode on the channel. Transistors with a double gate or multi-gate structure having a three-dimensional structure for maximizing the potential control capability of the channel by voltage have been proposed, but the manufacturing process is too complicated, and it is difficult to control the device and process variables.

To solve this problem, a FinFET using a silicon fin, which is very similar to the existing SOI transistor fabrication process and has a simple fabrication process, has been proposed.

In FinFET structures, the fin width must be 30% to 50% thinner than the gate line width to improve short channel effects.

In most semiconductor mass production processes, since the limit resolution for the minimum line width of the exposure technique is applied when forming the gate line width, it is impossible to form a fine pattern smaller than the gate line width.

Hereinafter, a method of forming a silicon thin film field effect transistor according to the related art will be schematically described with reference to the accompanying drawings and a problem thereof will be described.

1 is a process perspective view sequentially illustrating a method for fabricating a fin field effect transistor by a method of forming gates on both sides of a fin according to the prior art.

As shown, a hard mask 104a is formed on the SOI substrate 101 made of silicon, the lower insulating film 102, the silicon 103a on the lower insulating foil, and the silicon 103a (100A).

Lithography is used to form a silicon channel pattern (100B).

Oxidation and etching are used to reduce the fin width below the previously obtained width (100C).

After the gate 107 dielectric layer and the gate 107 material are grown or deposited, the gate 107 region is patterned, and a source / drain extension region is formed through ion implantation (100D).

A spacer 108 is formed on the side of the gate 107 and then a source / drain region is formed through ion implantation (100E).

An electrode 109 is formed by self-aligned silicide to fabricate a fin field effect transistor (100F).

The method of forming the gates 107 on both sides of the silicon channel by this method has a disadvantage in that the width of the silicon channel must be smaller than the gate 107 line width in order to obtain the potential control force of the gate voltage.

2 is a gate region electron micrograph of a transistor in which a gate according to the prior art surrounds three surfaces of a silicon channel.

The structure forms three gates surrounding the silicon channel, thereby depleting the entire silicon channel to mitigate the silicon channel dimensional condition.

However, there is a drawback that the edge characteristics of the silicon channel in operation below the threshold voltage influence device characteristics such as threshold voltage and drain induced barrier lowering (DIBL).

3A is a process perspective view illustrating a method of manufacturing a field effect transistor in which a gate surrounds a silicon channel in an omega form according to the prior art.

It is a silicon channel fabrication process of a conventional fin field effect transistor (300A).

A lower insulating layer 302 is etched under the silicon 301 channel (300B).

An omega field effect transistor is fabricated using a method of growing a gate 303 dielectric film (300C).

3B is an electron micrograph of the device fabricated by the fabrication method shown in FIG. 3A.

The electron micrograph shown is a cross-sectional photograph of a transmission electron microscope (TEM) of the gate surrounding the silicon channel in omega form.

The structure deposits a gate material after etching the oxide layer and forms a gate region through gate patterning, wherein the oxide layer below the source / drain region as well as the silicon channel where the channel is to be formed is etched to form an undercut shape.
The gate material is deposited therebetween, so that after the gate etching process, the remaining gate material remains at the bottom of the source / drain region and thus has a high overlap capacitance.

FIG. 4 is a cross-sectional view illustrating a method of fabricating a fin field effect transistor which reduces variation in device characteristics between wafers and is effective in device isolation using a bulk substrate according to the prior art.

A hard mask blocking layer 402a and a hard mask cap layer 401a are deposited on the bulk wafer 403a (400A).

After deposition, the fin pattern is patterned using optical lithography to form the hard mask blocking layer 402b and the hard mask cap layer 401b into a fin pattern (400B).

Using the patterned hard mask cap layer 401b and the pin height control layer, the bulk wafer 403c, which is a silicon substrate, is vertically anisotropically etched to a desired depth to adjust the height of the fin (400C).

In order to control the growth rate of the substrate between the silicon channel and the fin during oxidation, the silicon channel is protected with a hard mask blocking layer and ion implanted to form a damage layer 404 between the fins (400D).

An oxide film 405 having a different thickness is formed through oxidation, and the silicon channel 406 is formed by removing the oxide film grown on the side of the silicon channel through etching (400E).

A fin field effect transistor is manufactured in bulk by growing or depositing the gate dielectric layer 407 and the gate material (400F).

This structure uses a height control layer that uses damage caused by heavy ion implantation to adjust the height of the fin, and thus has a disadvantage in that it is difficult to control the exact silicon channel height as compared with the conventional SOI substrate.

5 is a cross-sectional view illustrating a method of fabricating an omega fin field effect transistor using a bulk substrate to solve a heat transfer problem of the fin field effect transistor according to the related art.

After forming a silicon channel using a silicon substrate using a trench process, the width of the fin on which the channel and the source / drain are to be formed is controlled by oxidation and etching (500A).

An oxide film is grown and a nitride film is deposited (500B).

An oxide film is deposited using chemical vapor deposition (500C).

Chemical-mechanical polishing (CMP) is performed using the nitride film as an etch stop layer (500D).

After wet etching the nitride film, ion implantation is performed to control the threshold voltage (500E).

By growing or depositing a gate dielectric layer and a gate material, an omega fin field effect transistor is fabricated in bulk (500F).

This structure uses a trench process to adjust the height of the fin, and has a disadvantage in that it is difficult to control the exact silicon channel height compared to the case of using a conventional SOI substrate.

6A is a perspective view of a nanowire field effect transistor with rounded silicon channels according to the prior art.

FIG. 6B is a gate region electron micrograph of the field effect transistor manufactured by the fabrication method shown in FIG. 6A.

A silicon channel is formed using a method of fabricating an omega fin field effect transistor on an SOI substrate, followed by hydrogen annealing to form a cylindrical nanowire silicon channel.

This structure has the advantage of reducing the corner effect of the body by using a cylindrical silicon channel, but not only the silicon channel on which the channel is to be formed but also the oxide layer under the source / drain region is etched and the gate material remains there. The disadvantage is that it has a high overlap capacitance.

An object of the present invention for solving the above problems is, by using an additional mask, a lower insulating layer or a partial etching of the silicon channel at the bottom of the silicon channel by using a partial capacitance of the silicon channel, the gate capacitance is formed on the front surface of the silicon channel smaller than the conventional structure The present invention provides a method for manufacturing an effect transistor.

In addition, another object of the present invention is to fabricate a field effect transistor having a gate formed on the front of the silicon channel with the overlap capacitance is a selective partial isotropic plasma dry etching that can form an undercut when etching the gate without the additional mask. To provide a way.

In the method for manufacturing a three-dimensional field effect transistor having a gate formed on a silicon channel all-around according to the present invention, the method for manufacturing a field effect transistor includes: (a) a silicon substrate, a lower insulating film, silicon, and a hard mask; Sequentially forming; (b) anisotropically etching silicon using the mask pattern as a mask to form a pattern of a silicon channel in which a channel is to be formed and a silicon region in which a source / drain is to be formed; (c) forming an additional mask that may serve as an etch stop layer when etching the lower insulating layer; (d) forming an entire surface of the silicon channel through etching of a lower insulating layer under the silicon channel stop layer; And (e) growing a gate dielectric layer around the exposed silicon channel, depositing a gate material, and forming a gate region to fabricate a field effect transistor having a gate formed on the entire surface of the silicon channel. It is characterized by.

According to the configuration according to the present invention, a three-dimensional transistor structure and manufacturing method of an all-around gate that can significantly improve the short channel effect than the double gate transistor while the channel width is larger than the gate line width.

In addition, it is possible to implement ultra-high-speed integrated circuits by minimizing overlap capacitance and to allow extreme scaling of silicon devices.

In addition, by forming a gate on the entire surface of the silicon channel of the three-dimensional structure to be used for the ultra-fast / ultra-high density semiconductor chip, it is possible to fabricate an ultra-fast field effect transistor of sub-10nm or less.

In addition, the method of manufacturing a field effect transistor according to the present invention comprises the steps of: (a) sequentially forming a silicon substrate, a lower insulating film, silicon and a hard mask; (b) anisotropically etching silicon using the mask pattern as a mask to form a pattern of a silicon channel in which a channel is to be formed and a silicon region in which a source / drain is to be formed; (c) forming an additional mask that may serve as an etch stop layer when etching the lower end of the silicon channel formed on the lower insulating layer; (d) forming a front surface of the silicon channel through isotropic plasma etching of a lower end of the silicon channel below the silicon channel stop layer; And (e) growing a gate dielectric layer around the exposed silicon channel, depositing a gate material, and forming a gate region to fabricate a field effect transistor having a gate formed on the entire surface of the silicon channel. It is characterized by.

In addition, the method of manufacturing a field effect transistor according to the present invention comprises the steps of: (a) sequentially forming a silicon substrate, a lower insulating film, silicon and a hard mask; (b) isotropic plasma etching silicon using the mask pattern as a mask to form an undercut under the entire silicon structure including channel, source, and drain predetermined regions; (c) growing a gate dielectric film around the silicon channel and depositing a gate material, and then forming a gate region; and (d) fabricating a field effect transistor having a gate formed on the front surface of the silicon channel by isotropic plasma etching to etch the remaining gate material in the gate region.

Hereinafter, a preferred embodiment of a method of manufacturing a field effect transistor having a gate formed on a silicon channel all-around according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 7A is a process perspective view sequentially illustrating a method of fabricating a field effect transistor having a gate formed on a front surface of a silicon channel according to an exemplary embodiment of the present invention.

The SOI substrate forms a silicon substrate 701, a lower insulating film 702, and a silicon 703a and a hard mask 704a over the lower insulating film 702, which are not etched in future silicon anisotropic or isotropic etching. It is composed of a material (700A).

Anisotropically etching the silicon 703b using the mask pattern as the mask 704b to form a pattern of a silicon channel where a channel is to be formed and a silicon region where a source / drain is to be formed (700B).

The photoresist pattern 705 is added, and the lower insulating layer is etched using the added photoresist pattern 705 as a mask (700C).

After growing the gate dielectric layer 707a and depositing the gate material 706a, a gate region is formed to fabricate a field effect transistor having a gate formed over the silicon channel (700D).
By this process, it is possible to fabricate a field effect transistor having a gate formed on the entire silicon channel according to an embodiment of the present invention.

FIG. 7B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 7A.

As shown in 7A of FIG. 7B, a method of etching the lower insulating layer 702 at the bottom of the silicon channel using only isotropic etching through wet etching, first anisotropic etching using dry etching, and then using silicon etching using wet etching It is possible to use a method of etching the lower insulating film at the bottom.

As shown in 7B of FIG. 7B, a cross-sectional view of a-a 'which has been etched by the added mask pattern 705e and b-b' which has not been etched is shown.
The cross-sectional view of a-a 'shows that the entire surface of the silicon 705f channel is exposed by etching the lower insulating layer, and the cross-sectional view of b-b' shows that the gate where no gate is to be formed is not formed. The silicon channel is formed on the lower insulating layer.

7C of FIG. 7B is a cross-sectional view of a-a 'which is etched by the added mask pattern and b-b' which is not etched.

The cross sectional view of a-a 'shows that the gate 706a surrounds the front surface of the silicon 707a channel, and the cross-sectional view of b-b' shows overlap capacitance because no gate material remains outside the gate region. It can be shown that it can be minimized (700G).

8A is an electron micrograph of a gate area according to an embodiment of the present invention.

Referring to FIG. 8A, an electron micrograph of a silicon channel formed when a silicon channel is formed on a lower insulating layer and a lower insulating layer is etched by wet etching using HF and a gate surrounding the front surface thereof.

8B is a cross-sectional view of the gate area illustrated to describe technical features according to an embodiment of the present invention.

The 800A is a field effect transistor having a gate formed on the entire surface of the silicon channel using the added mask pattern according to the exemplary embodiment of the present invention.

The 800B is a field effect transistor having a gate formed on an entire surface of a silicon channel formed by etching a lower insulating layer without using a mask added by a conventional method.

Drain area in case of etching through gate region cross-sectional view c-c '(800C) of each structure and added mask pattern Drain region in case of etching process without d-d'800D and additional mask pattern Sectional view e-e'800E.

The cross-sectional view of c-c 'shows that a gate is formed in front of the silicon channel in both cases.

Unlike the cross-sectional view of d-d 'in which the gate material does not remain in the drain region other than the gate region, the cross-sectional view of ee' when the additional mask pattern is not used is obtained by etching the lower insulating layer at the bottom of the drain region. The overlap capacitance is shown to increase significantly.

9A is a process perspective view sequentially illustrating a method of fabricating a field effect transistor having a gate formed on an entire surface of a silicon channel according to another exemplary embodiment of the present invention.

The SOI substrate forms the silicon substrate 901, the lower insulating film 902, and the silicon 903 and the added hard mask 904 on the lower insulating film, and the silicon patterned using the added mask pattern 904 as a mask. The channel is isotropic plasma etched for a sufficient time (900A).

Here, the added pattern mask 904 is preferably made of a material that is not affected when etching the silicon layer, that is, a material such as a photoresist film.

After the gate dielectric layer 905 is grown and the gate material 904 is deposited, the gate region is patterned to fabricate a field effect transistor having a gate formed over the silicon channel (900B).

FIG. 9B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 9A.

A cross-sectional view of a-a '9A which has been etched by the added pattern mask 904a of the structure and b-b' 9B which is not etched is shown.

A cross-sectional view 9A of a-a 'shows that the entire surface of the silicon channel is exposed by etching the silicon channel in the region where the gate is to be formed, while cross-sectional view 9B of b-b' shows that no gate is formed. The regions not to be formed show that the silicon 903a region is formed on the lower insulating layer.

A cross-sectional view at a-a '(9C) etched by the added mask pattern 904b of the structure and b-b' (9D) not etched is shown.

A cross-sectional view 9C of a-a 'shows that the gate dielectric film 905b surrounds the entire surface of the silicon channel, and a cross-sectional view 9D of b-b' shows that no gate material remains in portions other than the gate region.

10A is an electron micrograph of a gate region formed according to the method shown in FIG. 9.

After the silicon channel is formed on the lower insulating layer, plasma etching is performed using HBr and O ₂ gas which shows high selectivity between silicon and oxide film.

In this case, the excitation (excited) ions to etch silicon collide with the lower insulating layer and then bounce off to form an undercut shape by etching the lower portion of the silicon channel.

By controlling the etching time, all the lower ends of the silicon channels are etched, that is, the undercut profiles meet each other to completely separate the silicon channels from the lower insulating layer.

FIG. 10B is a cross-sectional view of a gate area illustrated to explain technical features in accordance with another embodiment of the present invention. FIG.

200A is a field effect transistor in which a gate is formed over a silicon channel using an added mask pattern according to another exemplary embodiment of the present invention.

The 200B is a field effect transistor having a gate formed on the entire silicon channel formed by etching a silicon pattern without using an added mask.

Drain region cross section d-d '(200D) and drain region cross section in the case of etching without additional mask -e '200E is shown.

Cross-sectional view 200C of c-c 'shows that a gate is formed in front of the silicon channel in both cases.

Unlike the cross-sectional view 200D of d-d 'in which the gate material does not remain in the drain region other than the gate region, the cross-sectional view e-e'200E in the case where the additional mask pattern is not used is the lower portion of the silicon where the drain region is formed. This etch shows that the gate material remains, resulting in a significant increase in overlap capacitance.

FIG. 11A is a process perspective view sequentially illustrating a method of fabricating a field effect transistor having a gate formed on an entire surface of a silicon channel according to another exemplary embodiment of the present invention.

The SOI substrate forms a silicon substrate 601, a lower insulating film 602, and a silicon 603 and a hard mask 604 on the lower insulating film, and the silicon channel is used for a sufficient time using the hard mask pattern 604 as a mask. Isotropic plasma etching is performed (600A).

Here, the hard mask 604 is preferably made of a material that is not etched in the future silicon anisotropic or isotropic etching.

Here, the hard mask uses a material that is not affected by the etching of the silicon layer, that is, a material such as a photoresist film.

Thereafter, compared to the process illustrated in FIGS. 7 to 10, the process of wet or dry removal of the silicon channel underlayer is the same, but the entire silicon structure (including channels, source / drain regions to be included) without additional masks to simplify the process; The difference is that it creates an undercut below.

After the gate dielectric layer 607 is grown and the gate material 606 is deposited, a gate region is formed, and then an isotropic plasma etching is performed for a sufficient time to etch the remaining gate material, thereby forming a field effect transistor having a gate formed on the entire surface of the silicon channel. (600B).

FIG. 11B is a cross-sectional view of the device fabricated by the fabrication method shown in FIG. 11A.

11B shows a cross-sectional view of the silicon channel a-a '6A, the gate region, the non-gate silicon channel b-b' 6B, and the c / c '6C, the source / drain region.

As shown, the cross-sectional views of a-a '(6A), b-b' (6B) and c-c '(6C) show the gate region and the remaining gate after silicon isotropic etching and gate region patterning.

The a-a '(6D), b-b' (6E) and c-c '(6F) shows the remaining gate material is etched after the selective isotropic dry etching (plasma etching) of the gate material.

Plasma etching using a gas having high selectivity to the gate material and the oxide film selectively isotropics the recoiled gate material after the excitation (excited) ions to etch the gate material collide with the underlying insulating film. Etched.

In this case, the silicon channel and the source / drain region may be prevented from being etched because the oxide layer is wrapped.

By controlling the time of etching, the gate region becomes a notched gate and covers the entire surface of the silicon channel, and the other region can completely etch the remaining gate material.

A gated field effect transistor can be fabricated in front of the silicon channel with minimal overlap capacitance without the added mask.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

The above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing description, and the meaning and scope of the claims and their All changes or modifications derived from equivalent concepts should be construed as being included in the scope of the present invention.

The method of manufacturing a field effect transistor in which a gate is formed on the entire surface of a silicon channel according to the present invention can manufacture a device having simple and reproducible improved characteristics, thereby making a significant contribution to continuously reducing the size of a semiconductor device.

In addition, it is possible to solve the high overlap capacitance which is a very practical technique using the current semiconductor process, which is pointed out as a problem in the performance of the conventional pin field effect transistor, and the channel formation problem of the fine line width which is pointed out as a difficulty in fabricating the device.

In addition, it is possible to contribute to the future development of the semiconductor industry by continually reducing the size of the semiconductor device, solving the problem of channel formation of fine line width.

Claims (12)

(a) sequentially forming a silicon substrate, a lower insulating film, silicon, and a hard mask; (b) anisotropically etching silicon using the mask pattern as a mask to form a pattern of a silicon channel in which a channel is to be formed and a silicon region in which a source / drain is to be formed; (c) forming an additional mask that may serve as an etch stop layer when etching the lower insulating layer; (d) forming an all-around surface of the silicon channel through etching of a lower insulating layer under the silicon channel stop layer; And (e) growing a gate dielectric layer around the exposed silicon channel and depositing a gate material, and then forming a gate region to fabricate a field effect transistor having a gate formed on the entire surface of the silicon channel; The field effect transistor manufacturing method having a gate formed on the front surface of the silicon channel comprising a. The method of claim 1, The etching in the step (d) is a method for manufacturing a field effect transistor having a gate formed on the front surface of the silicon channel, characterized in that to perform isotropic etching of the lower insulating film of the lower portion of the silicon channel using only wet etching. The method of claim 1, The etching in the step (d) is a first anisotropic etching of the lower insulating film by dry etching, and a second isotropic etching of the lower insulating film by wet etching to minimize the width of the undercut shape of the lower insulating film of the lower silicon channel A method for manufacturing a field effect transistor having a gate formed on a front surface of a silicon channel, wherein the etching is performed. delete (a) sequentially forming a silicon substrate, a lower insulating film, silicon, and a hard mask; (b) anisotropically etching silicon using the mask pattern as a mask to form a pattern of a silicon channel in which a channel is to be formed and a silicon region in which a source / drain is to be formed; (c) forming an additional mask that may serve as an etch stop layer when etching a lower portion of the silicon channel on the lower insulating layer; (d) forming an entire surface of the silicon channel through isotropic plasma etching of a lower end of the silicon channel on the lower insulating layer under the silicon channel stop layer; And (e) growing a gate dielectric layer around the exposed silicon channel and depositing a gate material, and then forming a gate region to fabricate a field effect transistor having a gate formed on the entire surface of the silicon channel; The field effect transistor manufacturing method having a gate formed on the front surface of the silicon channel comprising a. The method of claim 5, In the isotropic plasma etching in step (d), the isotropic etching of the lower end of the silicon channel on the lower insulating foil is performed by using excitation ions recoiled using a gas including HBr and O ₂ . The field effect transistor manufacturing method in which the gate was formed in the silicon channel whole surface. The method of claim 5, In the step (d), the isotropic plasma etching is performed by performing a first etching of the lower end of the silicon channel on the lower insulating layer by plasma etching using a gas including HBr and O ₂ , followed by wet etching to form the lower part of the silicon channel. A method of manufacturing a field effect transistor having a gate formed on a front surface of a silicon channel, wherein the second etching is performed. The method of claim 6, In the isotropic plasma etching in step (d), the gate is formed on the front surface of the silicon channel, wherein etching is performed using an etching gas having a high selectivity for silicon and oxide other than HBr and O _2. Method for manufacturing field effect transistors. delete (a) sequentially forming a silicon substrate, a lower insulating film, silicon, and a hard mask; (b) isotropic plasma etching silicon using the mask pattern as a mask to form an undercut under the entire silicon structure including channel, source and drain predetermined regions; (c) growing a gate dielectric film around the silicon channel and depositing a gate material, and then forming a gate region; And (d) fabricating a field effect transistor having a gate formed in front of the silicon channel by isotropic plasma etching to etch the remaining gate material in the gate region; The field effect transistor manufacturing method having a gate formed on the front surface of the silicon channel comprising a. The method of claim 10, In the etching of the step (d), after isotropic plasma etching with recoiled excitation ions using a gas including HBr and O ₂ , silicon is characterized in that residual gate material is removed by selective isotropic dry etching. A method of manufacturing a field effect transistor in which a gate is formed in front of a channel. delete

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