KR100614929B1 - Method for 3 dimension integrating wafers - Google Patents

Method for 3 dimension integrating wafers Download PDF

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KR100614929B1
KR100614929B1 KR1020050058234A KR20050058234A KR100614929B1 KR 100614929 B1 KR100614929 B1 KR 100614929B1 KR 1020050058234 A KR1020050058234 A KR 1020050058234A KR 20050058234 A KR20050058234 A KR 20050058234A KR 100614929 B1 KR100614929 B1 KR 100614929B1
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semiconductor substrate
back surface
wafers
defects
dimensional integration
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박상균
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매그나칩 반도체 유한회사
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Abstract

본 발명은 웨이퍼 간의 3차원 집적 방법으로, 서로 집적된 두 웨이퍼에서 제 2 반도체 기판을 연마하면서 발생하는 표면 결함 및 내부에 잔류하는 결함들을 용이하게 제거하기 위하여, 제 2 반도체 기판 내에 상기 결함들을 포함하는 인위적인 손상층을 형성함으로써, 집적 공정을 안정적이고 신뢰성 있게 진행할 수 있는 웨이퍼 간의 3차원 집적 방법에 관한 것이다.The present invention is a three-dimensional integration method between wafers, which includes the defects in the second semiconductor substrate in order to easily remove surface defects and residual defects generated while polishing the second semiconductor substrate in the two wafers integrated with each other. The present invention relates to a three-dimensional integration method between wafers capable of stably and reliably proceeding an integration process by forming an artificial damage layer.

Description

웨이퍼 간의 ３차원 집적 방법{METHOD FOR 3 DIMENSION INTEGRATING WAFERS}3D integration method between wafers {METHOD FOR 3 DIMENSION INTEGRATING WAFERS}

도 1은 종래 기술에 따른 웨이퍼 간의 3차원 집적 공정을 완료한 표면 사진.1 is a surface photograph of a three-dimensional integration process between wafers according to the prior art.

도 2는 종래 기술에 따른 웨이퍼 간의 3차원 집적 방법을 도시한 단면도.2 is a cross-sectional view showing a three-dimensional integration method between wafers according to the prior art.

도 3은 본 발명에 따른 웨이퍼 간의 3차원 집적 방법을 도시한 단면도.3 is a cross-sectional view illustrating a three-dimensional integration method between wafers according to the present invention.

본 발명은 웨이퍼 간의 3차원 집적 방법으로, 제 2 반도체 기판 배면의 결함들을 포함하는 인위적인 손상층을 형성한 후 제거함으로써, 집적된 두 웨이퍼에서 제거 대상이 되는 제 2 반도체 기판의 표면 결함 및 내부에 잔류하는 결함들을 용이하게 제거할 수 있는 웨이퍼 간의 3차원 집적 방법에 관한 것이다.The present invention is a three-dimensional integration method between wafers, by forming and removing an artificial damage layer including defects on the back surface of the second semiconductor substrate, thereby removing the surface defects and the interior defects of the second semiconductor substrate to be removed from the two integrated wafers. A three-dimensional integration method between wafers that can easily remove residual defects.

전자 기기들의 소형화 및 경량화가 진행되면서 반도체 소자의 칩 크기도 감소하게 되었다. 그러나, 칩 크기의 감소에는 한계가 있으므로 복수의 반도체 칩을 하나의 패키지로 구성하는 웨이퍼 간의 3차원 집적 방법이 이용되고 있다.As miniaturization and light weight of electronic devices have progressed, the chip size of semiconductor devices has also decreased. However, since there is a limit to the reduction in chip size, a three-dimensional integration method between wafers constituting a plurality of semiconductor chips in one package is used.

웨이퍼 간의 3차원 집적 방법은, 다른 기판과 연결될 W 또는 Cu 수직 배선을 포함하는 기판 전면에 수직 배선 및 다른 인터커넥트(Interconnect)들과 연결된 Cu 본딩 패드를 형성하여 웨이퍼 간의 집적을 실시한다. 다음에는, 집적된 한쪽 기판 의 뒷면을 연마하여 제거하는 공정을 수행한다. 그러나, 연마 공정이 진행 되면서 기판에 결함들이 발생하여 후속의 공정을 진행하는데 불량 발생의 원인이 되거나 웨이퍼가 깨지는 문제가 된다.The three-dimensional integration method between wafers performs integration between wafers by forming Cu bonding pads connected with vertical interconnects and other interconnects in front of a substrate including W or Cu vertical interconnects to be connected to other substrates. Next, a process of polishing and removing the back side of the integrated one substrate is performed. However, as the polishing process proceeds, defects are generated in the substrate, which causes the defect or the wafer to be broken in the subsequent process.

도 1은 종래 기술에 따른 웨이퍼 간의 3차원 집적 공정을 완료한 표면 사진이다.1 is a surface photograph of a three-dimensional integration process between wafers according to the prior art.

도 1을 참조하면, 웨이퍼 간에 집적 공정이 완료 되었을 때, 수직 배선이 노출된 상태를 나타낸 표면 사진이다. 이때, 표면에는 반도체 기판을 연마하면서 발생한 V 형 라인 결함들을 볼 수 있다. Referring to FIG. 1, when the integration process is completed between wafers, a surface photograph showing a state in which vertical wiring is exposed. At this time, the V-type line defects generated while polishing the semiconductor substrate can be seen on the surface.

도 2는 종래 기술에 따른 웨이퍼 간의 3차원 집적 방법을 도시한 단면도이다.2 is a cross-sectional view showing a three-dimensional integration method between wafers according to the prior art.

도 2를 참조하면, 제 1 반도체 기판(10)에 제 1 반도체 소자 형성층(20)이 형성되어 있고 제 1 반도체 소자 형성층(20) 상부에는 웨이퍼간 집적을 위한 제 1 금속 패드(25)가 구비되어 있다. 이와 동일하게 제 2 반도체 기판(50)에도 제 2 반도체 소자 형성층(30) 및 제 2 금속 패드(35)가 구비된다. 또한, 제 2 반도체 기판(50)에는 제 1 반도체 소자층(20)과 전기적으로 접속이 되도록 하는 인터 웨이퍼(Inter-wafer) 수직 배선(40)이 구비된다.Referring to FIG. 2, a first semiconductor element formation layer 20 is formed on a first semiconductor substrate 10, and a first metal pad 25 for inter-wafer integration is provided on the first semiconductor element formation layer 20. It is. Similarly, the second semiconductor substrate 50 also includes the second semiconductor element formation layer 30 and the second metal pad 35. In addition, the second semiconductor substrate 50 is provided with an inter-wafer vertical wiring 40 to be electrically connected to the first semiconductor element layer 20.

다음에는, 제 1 금속 패드(25)와 제 2 금속 패드(35)가 서로 접속되도록 제 1 반도체 기판(10) 및 제 2 반도체 기판(50)을 집적하고, 제 2 반도체 기판(50)의 뒷면을 기계적 연마 공정을 이용하여 소정 두께 제거한다. 이때, 제거되는 기계적 연마층(60)의 두께는 500 ~ 660㎛ 로 실제 제 2 반도체 기판의 대부분이 연마되는 데, 이 과정에서 반도체 기판의 표면에 결함(90)이 발생하게 된다. 이러한 결함(90)들을 제거하기 위하여 CMP층(70) 및 건식 식각층(80)을 설정하여 공정을 진행하지만 결함(90)들이 제거되지 않고 기판 내부로 전파되는 문제가 있다. Next, the first semiconductor substrate 10 and the second semiconductor substrate 50 are integrated so that the first metal pad 25 and the second metal pad 35 are connected to each other, and the back surface of the second semiconductor substrate 50 is formed. The predetermined thickness is removed using a mechanical polishing process. At this time, the thickness of the mechanical polishing layer 60 to be removed is 500 ~ 660㎛ the majority of the actual second semiconductor substrate is polished, in this process the defect 90 is generated on the surface of the semiconductor substrate. In order to remove the defects 90, the process is performed by setting the CMP layer 70 and the dry etching layer 80, but there is a problem that the defects 90 are not removed and propagate into the substrate.

이러한 결함들은 후속의 공정인 Al I/O(Input/Output) 패드를 형성하거나 금속 배선들을 연결하는 과정에서 웨이퍼 깨짐등 다른 종류의 불량을 발생시키는 원인을 제공한다. 또한, 이러한 기계적 결함들은 전위(Dislocation) 형태의 결함으로 두 기판 집적면 안쪽 반도체 소자 형성층으로 전파되어 소자의 특성을 저하시키는 문제를 유발한다. These defects provide other types of defects such as wafer breakage during the subsequent process of forming Al I / O (Input / Output) pads or connecting metal wires. In addition, these mechanical defects are dislocation-type defects, which propagate to the semiconductor element formation layers inside the two substrate integrated surfaces, causing problems of deterioration of device characteristics.

본 발명은 상기한 바와 같은 문제를 해결하기 위하여, 제 2 반도체 기판을 연마하면서 발생할 수 있는 결함들을 포함하는 인위적인 손상층을 형성함으로써, 제 2 반도체 기판에 존재하는 결함들을 용이하게 제거할 수 있는 웨이퍼 간의 3차원 집적 방법을 제공하는 것을 그 목적으로 한다.In order to solve the problems as described above, the present invention provides a wafer capable of easily removing defects present in the second semiconductor substrate by forming an artificial damage layer including defects that may occur while polishing the second semiconductor substrate. It is an object to provide a three-dimensional integration method of the liver.

본 발명은 상기와 같은 목적을 달성하기 위한 것으로, 본 발명에 따른 웨이퍼 간의 3차원 집적 방법은,The present invention is to achieve the above object, the three-dimensional integration method between wafers according to the present invention,

(a) 제 1 반도체 기판과 수직 배선을 포함하는 제 2 반도체 기판을 집적하는 단계와,(a) integrating a second semiconductor substrate comprising a first semiconductor substrate and a vertical wiring;

(b) 상기 제 2 반도체 기판 배면을 기계적 연마 공정을 이용하여 소정 두께 제거하는 단계와,(b) removing the back surface of the second semiconductor substrate by a predetermined thickness using a mechanical polishing process;

(c) 상기 제 2 반도체 기판의 배면 전체에 손상층을 형성하는 단계와,(c) forming a damage layer on the entire back surface of the second semiconductor substrate,

(d) 상기 손상층을 제거하는 단계와,(d) removing the damage layer;

(e) CMP 공정을 수행하여 상기 제 2 반도체 기판의 배면을 평탄화식각하는 단계 및(e) performing a CMP process to planarize and etch the back surface of the second semiconductor substrate;

(f) 상기 제 2 반도체 기판 배면을 식각하여 상기 수직 배선을 노출시키는 단계를 포함하는 것을 특징으로 한다.(f) etching the back surface of the second semiconductor substrate to expose the vertical lines.

아울러, 본 발명에서는 상기 인위적인 손상층을 형성하는 방법으로,In addition, in the present invention, a method of forming the artificial damage layer,

Ge, P, O, Si 및 이들의 혼합 가스 중 선택된 어느 하나를 이용한 임플란테이션 방법으로 형성하는 제 1 실시예와,A first embodiment formed by an implantation method using any one selected from Ge, P, O, Si, and a mixed gas thereof;

H, O, H2O 및 이들의 혼합 중 어느 하나를 이용한 열처리 방법으로 형성하는 제 2 실시예를 제공한다.A second embodiment is provided by a heat treatment method using any one of H, O, H 2 O, and a mixture thereof.

이하 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 멀티 칩 패키지 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a multi-chip package method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 웨이퍼 간의 3차원 집적 방법을 도시한 단면도이다.3 is a cross-sectional view illustrating a three-dimensional integration method between wafers according to the present invention.

도 3을 참조하면, 제 1 반도체 기판(100)에 제 1 반도체 소자 형성층(120)이 형성되어 있고 제 1 반도체 소자 형성층 상부에는 웨이퍼간 집적을 위한 제 1 금속 패드(125)가 구비되어 있다. 이와 동일하게 제 2 반도체 기판(150)에도 제 2 반도체 소자 형성층(130) 및 제 2 금속 패드(135)가 구비된다. 또한, 제 2 반도체 기판(150)에는 제 1 반도체 소자층(120)과 전기적으로 접속이 되도록 하는 인터 웨이퍼 (Inter-wafer) 수직 배선(140)이 구비된다. 이때, 수직 배선(140) 제 2 금속 패드와 연결되며, 제 2 반도체 기판(150)의 표면에서부터 5 ~ 30㎛의 깊이 까지 형성되는 것이 바람직하다.Referring to FIG. 3, a first semiconductor element formation layer 120 is formed on a first semiconductor substrate 100, and a first metal pad 125 for inter-wafer integration is provided on the first semiconductor element formation layer. In the same manner, the second semiconductor substrate 150 also includes the second semiconductor element formation layer 130 and the second metal pad 135. In addition, the second semiconductor substrate 150 is provided with an inter-wafer vertical interconnection 140 to be electrically connected to the first semiconductor element layer 120. In this case, the vertical wiring 140 is connected to the second metal pad, and is preferably formed to a depth of 5 to 30 μm from the surface of the second semiconductor substrate 150.

다음에는, 제 1 금속 패드(125)와 제 2 금속 패드(135)가 서로 접속되도록 제 1 반도체 기판(100) 및 제 2 반도체 기판(150)을 집적시킨다. 여기서, 제 2 반도체 기판(150)의 실제 두께는 670 ~ 700㎛로 제 1 반도체 기판(100)과 동일하지만 본 발명의 구성을 상술하기 위하여 편의상 두껍게 도시하기로 한다.Next, the first semiconductor substrate 100 and the second semiconductor substrate 150 are integrated so that the first metal pad 125 and the second metal pad 135 are connected to each other. Here, the actual thickness of the second semiconductor substrate 150 is 670 ~ 700㎛ is the same as the first semiconductor substrate 100 but will be shown thick for convenience in order to describe the configuration of the present invention.

도 1의 제 2 반도체 기판(150)은 기계적 연마층(160), 인위적인 손상층(165), CMP층(170) 및 건식 식각층(180)으로 구분된다.The second semiconductor substrate 150 of FIG. 1 is divided into a mechanical polishing layer 160, an artificial damage layer 165, a CMP layer 170, and a dry etching layer 180.

본 발명의 제 1 실시예에 따른 웨이퍼 간의 3차원 결합 방법에 관하여 설명하면 다음과 같다.Referring to the three-dimensional bonding method between the wafers according to the first embodiment of the present invention will be described.

먼저, 제 2 반도체 기판(150)의 뒷면을 기계적 연마 공정을 이용하여 소정 두께 제거한다. 이때, 제거되는 기계적 연마층(160)의 두께는 400 ~ 600㎛ 인 것이 바람직하다.First, the back surface of the second semiconductor substrate 150 is removed by a predetermined thickness using a mechanical polishing process. At this time, the thickness of the mechanical polishing layer 160 to be removed is preferably 400 ~ 600㎛.

다음에는, 상기 연마 공정에 의해서 발생하는 반도체 기판의 결함들을 제거하기 위하여 Ge, P, O, Si 및 이들의 혼합 가스 중 선택된 어느 하나를 이용한 임플란테이션 방법으로 인위적인 손상층(165)을 제 2 반도체 기판(150) 내부에 형성한다. 여기서, 인위적인 손상층(165)은 제 2 반도체 기판(150)내에 잔류하는 결함(190)을 모두 하나의 층에 포함시킬 수 있어야 한다. 이 과정에서도 제거가 안되고 잔류하는 결함들은 O2, H2, Ar 및 이들의 혼합 가스 중 선택된 어느 하나를 이용한 열처리 공정을 300 ~ 500℃의 온도에서 수행하여 인위적인 손상층(165)에 포함되도록 하거나 어닐 아웃(Anneal Out) 시키는 것이 바람직하다.Next, in order to remove defects in the semiconductor substrate generated by the polishing process, the artificial damage layer 165 may be secondly implanted using an implantation method using any one selected from Ge, P, O, Si, and a mixture thereof. It is formed in the semiconductor substrate 150. Here, the artificial damage layer 165 should be able to include all the defects 190 remaining in the second semiconductor substrate 150 in one layer. In this process, the defects that cannot be removed and remain are included in the artificial damage layer 165 by performing a heat treatment process using any one selected from O 2 , H 2 , Ar, and a mixture thereof at a temperature of 300 to 500 ° C. It is preferable to anneal out.

그 다음에는, 제 2 반도체 기판(150)에 기계적 연마 공정 및 습식 식각 공정을 수행하여 상기 손상층을 제거한다. 이때, 인위적인 손상층(165)을 제거하는 공정은 HF 계열 및 Si 계열의 습식 식각 용액 중 선택된 어느 하나를 이용하는 것이 바람직하다. Next, the damage layer is removed by performing a mechanical polishing process and a wet etching process on the second semiconductor substrate 150. In this case, it is preferable to use any one selected from the HF-based and Si-based wet etching solutions for removing the artificial damage layer 165.

이와 같이 습식 식각에 의해 형성된 제 2 반도체 기판(150)의 표면은 균일하게 형성되지 못하기 때문에 후속의 공정에서 또 다시 결함을 발생시킬 위험이 있다. 따라서, 결함 발생을 억제하기 위하여 CMP 공정을 수행한다. 이때, CMP층(170)이 제거된 제 2 반도체 기판(150)의 표면은 두께 균일도가 -1 ~ +1㎛가 되도록 평탄화하는 것이 바람직하다. As such, since the surface of the second semiconductor substrate 150 formed by wet etching may not be uniformly formed, there is a risk of causing defects in subsequent processes. Therefore, the CMP process is performed to suppress the occurrence of defects. At this time, it is preferable that the surface of the second semiconductor substrate 150 from which the CMP layer 170 is removed is planarized so that the thickness uniformity becomes −1 to +1 μm.

마지막으로, 잔류하는 제 2 반도체 기판(150) 전면에 건식 식각 공정을 수행하여 수직 배선(140)을 노출시킨다. 이때, 건식식각 공정은 수직 배선(140)이 0.1 ~ 0.2㎛ 높이로 노출 될 때까지 수행하는 것이 바람직하다.Finally, a dry etching process is performed on the remaining second semiconductor substrate 150 to expose the vertical wiring 140. At this time, the dry etching process is preferably performed until the vertical wiring 140 is exposed to 0.1 ~ 0.2㎛ height.

아울러, 본 발명의 다른 실시예에 따른 웨이퍼 간의 3차원 집적 방법에 있어서, 제 2 반도체 기판(150)의 결함들을 제거하는 방법으로,In addition, in the three-dimensional integration method between wafers according to another embodiment of the present invention, a method for removing defects of the second semiconductor substrate 150,

H, O, H2O 및 이들의 혼합 중 어느 하나를 이용한 열처리 방법을 이용하는 것이 있다. 상기 가스들은 반도체 기판을 산화시킨다. 여기서 상기 열처리 공정에 의해서 제 2 반도체 기판(150)에 발생하는 결함들은 실리콘 산화막에 포함되거나 어닐 아웃되어 제거 된다.There is a method of using a heat treatment method using any one of H, O, H 2 O and a mixture thereof. The gases oxidize the semiconductor substrate. In this case, defects occurring in the second semiconductor substrate 150 by the heat treatment process are included in the silicon oxide film or are annealed out and removed.

이 상에서 설명한 웨이퍼 간의 3차원 집적 방법은 칩투칩 멀티 스택(Chip to Chip multi stacking)과, 칩투웨이퍼 멀티 스택 (Chip to Wafer multi stacking) 및 SIP(System in Package) 공정에서 모두 사용가능 하다.The above-described three-dimensional integration method between wafers can be used in both chip to chip multi stacking, chip to wafer multi stacking, and SIP in system.

이상에서 설명한 바와 같이 본 발명에 따른 웨이퍼 간의 3차원 집적 방법은 제 2 반도체 기판을 연마하면서 발생할 수 있는 결함들을 포함하는 인위적인 손상층을 형성함으로써, 제 2 반도체 기판에 존재하는 결함들을 용이하게 제거할 수 있다. 따라서, 두 반도체 기판 간에 3차원 집적 공정을 안정적으로 형성할 수 있고, 공정 상의 신뢰성을 확보할 수 있는 효과를 제공한다.As described above, the three-dimensional integration method between wafers according to the present invention forms an artificial damage layer including defects that may occur while polishing the second semiconductor substrate, thereby easily removing defects present in the second semiconductor substrate. Can be. Therefore, it is possible to stably form a three-dimensional integration process between the two semiconductor substrates, and provides an effect of ensuring the reliability of the process.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

(a) 제 1 반도체 기판과 수직 배선을 포함하는 제 2 반도체 기판을 집적하는 단계;(a) integrating a second semiconductor substrate comprising a first semiconductor substrate and a vertical wiring; (b) 상기 제 2 반도체 기판 배면을 기계적 연마 공정을 이용하여 소정 두께 제거하는 단계;(b) removing a predetermined thickness from the back surface of the second semiconductor substrate using a mechanical polishing process; (c) 상기 제 2 반도체 기판의 배면 전체에 손상층을 형성하는 단계;(c) forming a damage layer on the entire back surface of the second semiconductor substrate; (d) 상기 손상층을 제거하는 단계;(d) removing the damage layer; (e) CMP 공정을 수행하여 상기 제 2 반도체 기판의 배면을 평탄화식각하는 단계; 및(e) performing a CMP process to planarize and etch the back surface of the second semiconductor substrate; And (f) 상기 제 2 반도체 기판 배면을 식각하여 상기 수직 배선을 노출시키는 단계를 포함하는 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.(f) etching the back surface of the second semiconductor substrate to expose the vertical interconnection. 제 1 항에 있어서,The method of claim 1, 상기 (b) 단계에서 제 2 반도체 기판이 제거 되는 두께는 400 ~ 600㎛ 인 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.The thickness of the second semiconductor substrate is removed in the step (b) is 400 ~ 600㎛ three-dimensional integration method between the wafers. 제 1 항에 있어서,The method of claim 1, 상기 (c) 단계는 Ge, P, O, Si 및 이들의 조합 중 선택된 어느 하나를 이용한 임플란테이션 방법으로 수행하는 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.Step (c) is a three-dimensional integration method between the wafer, characterized in that performed by the implantation method using any one selected from Ge, P, O, Si and combinations thereof. 제 3 항에 있어서,The method of claim 3, wherein 상기 (c) 단계를 수행한 후 O2, H2, Ar 및 이들의 혼합 가스 중 선택된 어느 하나의 분위기 및 300 ~ 500℃의 온도에서 열처리 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.After performing the step (c) further comprises the step of performing a heat treatment process in the atmosphere of any one selected from O 2 , H 2 , Ar and mixed gas and a temperature of 300 ~ 500 ℃ 3D integration method of liver. 제 1 항에 있어서,The method of claim 1, 상기 (d) 단계는 HF 계열 및 Si 계열의 습식 식각 용액 중 선택된 어느 하나를 이용하여 수행하는 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.The step (d) is a three-dimensional integration method between the wafer, characterized in that performed using any one selected from the HF-based and Si-based wet etching solution. 제 1 항에 있어서,The method of claim 1, 상기 (e) 단계의 CMP 공정은 상기 제 2 반도체 기판의 두께 균일도가 -1 ~ +1㎛가 되도록 수행하는 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.The CMP process of step (e) is carried out so that the thickness uniformity of the second semiconductor substrate is -1 ~ + 1㎛. 제 1 항에 있어서,The method of claim 1, 상기 (f) 단계는 건식 식각 공정은 상기 수직 배선이 0.1 ~ 0.2㎛ 높이로 노출 될 때까지 수행하는 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.In the step (f), the dry etching process is performed until the vertical interconnection is exposed at a height of 0.1 to 0.2 μm. (a) 제 1 반도체 기판과 수직 배선을 포함하는 제 2 반도체 기판을 집적하는 단계;(a) integrating a second semiconductor substrate comprising a first semiconductor substrate and a vertical wiring; (b) 상기 제 2 반도체 기판 배면을 기계적 연마 공정을 이용하여 소정 두께 제거하는 단계;(b) removing a predetermined thickness from the back surface of the second semiconductor substrate using a mechanical polishing process; (c) 상기 제 2 반도체 기판의 결함들을 H, O, H2O 및 이들의 조합 중 어느 하나의 분위기에서 수행하는 열처리 방법을 이용하여 제거하는 단계;(c) removing defects of the second semiconductor substrate using a heat treatment method performed in an atmosphere of any one of H, O, H 2 O, and a combination thereof; (d) CMP 공정을 수행하여 상기 제 2 반도체 기판의 배면을 평탄화식각하는 단계; 및(d) performing a CMP process to planarize and etch the back surface of the second semiconductor substrate; And (e) 상기 제 2 반도체 기판 배면을 식각하여 상기 수직 배선을 노출시키는 단계를 포함하는 것을 특징으로 하는 웨이퍼 간의 3차원 집적 방법.(e) etching the back surface of the second semiconductor substrate to expose the vertical interconnections.
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JPS6482685A (en) * 1987-09-25 1989-03-28 Nec Corp Semiconductor laser element
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US20040212076A1 (en) 2002-09-27 2004-10-28 Medtronic Minimed, Inc. Multilayer substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482685A (en) * 1987-09-25 1989-03-28 Nec Corp Semiconductor laser element
KR20000003356A (en) * 1998-06-27 2000-01-15 김영환 Method for forming contact hole of semiconductor memory apparatus
KR20000026686A (en) * 1998-10-22 2000-05-15 윤종용 Method of forming pattern of semiconductor device
US20040212076A1 (en) 2002-09-27 2004-10-28 Medtronic Minimed, Inc. Multilayer substrate

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