KR100614272B1 - Fringe field switching mode liquid crystal display device - Google Patents

Abstract

The present invention discloses an FFS mode liquid crystal display device suitable for improving screen quality by preventing the screen from becoming greenish due to distortion of the common voltage. According to the present invention, in a FFS mode liquid crystal display in which a transparent counter electrode is formed on a lower substrate and a common electrode line is connected to the counter electrode, a plurality of common electrode lines are formed in a unit pixel region defined by gate bus lines and data bus lines. It is characterized by the separation of the storage capacitance by forming.

Common Electrode Line, Greenish, Crosstalk

Description

FRENCH FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE}

1 is a cross-sectional view for explaining a FFS-LCD to which a HAN mode according to the prior art is applied.

2 is a layout showing unit pixels of a conventional FFS-LCD.

3 is a diagram showing polarity of gate lines in a specific pattern (one skip line and two skip dot patterns) when the FFS mode is driven in dot inversion.

Figure 4 is an equivalent circuit diagram for explaining the RC delay of the common electrode line according to the prior art.

5 is a layout diagram illustrating unit pixels of a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.

6 is an equivalent circuit diagram illustrating an RC delay of a common electrode line of a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: gate bus line 200: data bus line

300: pixel electrodes 400a and 400b: first and second common electrode lines

500a, 500b: first and second counter electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a FFS (Fringe Field Switching) mode liquid crystal display suitable for improving screen quality by improving Greenish, Crosstalk, and the like.

In general, the FFS mode liquid crystal display is proposed to improve the low aperture ratio and transmittance of the IPS mode liquid crystal display, and the counter electrode and the pixel electrode are formed of a transparent conductor for the high aperture ratio and the high transmittance, while the counter electrode and the pixel are formed. The gap between the electrodes is formed to be narrower than the gap between the upper and lower substrates so that a fringe field is formed on the counter electrode and the pixel electrode, so that all of the liquid crystal molecules on the electrodes are operated.

1 is a cross-sectional view for explaining a FFS-LCD applying a HAN mode according to the prior art, the lower substrate 10 and the upper substrate 30 are opposed to each other at a predetermined distance (d). The liquid crystal layer 20 having the predetermined liquid crystal molecules 20a is interposed between the lower substrate 10 and the upper substrate 30. In this case, the liquid crystal molecule 20a may be selectively used as a material having a positive or negative dielectric anisotropy.

A counter electrode 15 is plated for each unit pixel on the lower substrate 10 on which the gate bus line (not shown), the data bus line (not shown), and the thin film transistor (not shown), which are active matrix basic elements, are formed. Formed in the form; At this time, the counter electrode 15 is formed of a transparent conductive material, as is known. The gate insulating layer 16 is formed on the counter electrode 15, and the pixel electrode 17 has a comb shape including several combs to form a counter electrode and a fringe field on the gate insulating layer 16. Is formed. In this case, the pixel electrode 17 is also preferably formed of a transparent conductor. A horizontal alignment layer 18 is formed on the lower substrate resultant, and the horizontal alignment layer 18 has a rubbing axis facing a predetermined direction.

When the direction of the rubbing axis is positive in order that the dielectric anisotropy of the liquid crystal molecules 20a is positive to satisfy the maximum transmittance, the fringe field is determined to form 45 ° to 90 ° with the direction projected onto the substrate, and the dielectric anisotropy of the liquid crystal molecules 20a is determined. If it is negative, it is determined to make 0 ° to 45 ° with the substrate projection surface of the fringe field.

On the other hand, although not shown in the figure, the color filter is disposed on the inner surface of the upper substrate 30, and the vertical alignment layer 28 is disposed on the surface of the color filter. At this time, the vertical alignment layer 28 does not have a rubbing axis as is known. Here, the liquid crystal molecules 20a in the liquid crystal layer 20 are formed by the horizontal alignment layer 18 of the lower substrate 10 and the vertical alignment layer 28 of the upper substrate 30. It is arranged in a horizontal plane and in the upper substrate 30 toward the long axis is arranged in a hybrid form perpendicular to the substrate surface.

The first polarizing plate 5 having a predetermined polarization axis is disposed outside the lower substrate 10, and the second polarizing plate 35 having an absorption axis perpendicular to the polarization axis is disposed outside the upper substrate 30. In this case, the polarization axis of the first polarizing plate 5 may use an E-mode orthogonal to the absorption axis while being perpendicular to the absorption axis to realize a normally black mode, or may be perpendicular to the rubbing axis. You can also use -mode.

The FFS-LCD configured as described above operates as follows.

First, if a voltage difference, i.e., no field is formed between the counter electrode 15 and the pixel electrode 17, the liquid crystal molecules 20a are affected by the rubbing axis and the substrate surface under the influence of the horizontal alignment layer 18 on the lower substrate 10 side. It is arranged so as to be parallel to the upper substrate 30, the long axis is arranged perpendicular to the substrate surface under the influence of the vertical alignment film 28 toward the upper substrate 30 side. Accordingly, the light passing through the first polarizing plate 5 does not change the polarization direction while passing through the liquid crystal layer 20, and thus cannot pass through the second polarizing plate 35 having an absorption axis perpendicular to the polarization axis. Thus, the screen is dark.

On the other hand, when a fringe field is applied between the counter electrode 15 and the pixel electrode 17, all of the liquid crystal molecules 20a between and above the counter electrode 15 and the pixel electrode 17 are all caused by the fringe field. Is twisted. As a result, the light passing through the first polarizing plate 5 passes through the liquid crystal layer 20 and passes through the second polarizing plate 35 having an absorption axis orthogonal to the polarization axis by changing its polarization state. Thus, the screen is in a white state.

In the conventional fringe field switching (FFS) mode liquid crystal display device, a plurality of gate bus lines are disposed in parallel with each other in a first direction, that is, in the X direction, on the lower substrate 10, and a plurality of data bus lines are provided. The second direction, that is, the Y-direction is arranged parallel to each other to form a matrix arrangement, and each of the opposite common electrode line is formed between each gate bus line running in parallel with each other in parallel with the gate bus line.

For reference, the matrix arrays each define a unit pixel area.

FIG. 2 illustrates a unit cell of a conventional FFS mode liquid crystal display, in which one gate bus line 51, one common electrode line 53, and one data bus line 55 are disposed.

Here, the gate bus line 51 and the common electrode line 53 are formed in the same stacked structure, and the data bus line 55 is insulated from the gate common electrode with a gate insulating film (not shown) interposed therebetween.

In the drawing, the counter electrode 57 is formed in a unit pixel space, for example, to have a frame similar to the pixel opening area, and the counter electrode 57 is formed on the surface of the lower substrate like the gate bus line 51. Is placed on.

The pixel electrode 59 is arranged above the counter electrode 57 with a gate insulating film and a source insulating film interposed therebetween, and a slit for switching the liquid crystal in a region surrounded by the counter electrode 57 having a rectangular frame shape. It is formed into a structure.

The thin film transistor TFT is disposed adjacent to the intersection of the gate bus line 51 and the data bus line 55. The thin film transistor TFT is a gate electrode and data bus line extending from the gate bus line 51. And a drain electrode formed to extend from 55, a source electrode extended from the pixel electrode 59, and a channel layer 60 formed on the gate electrode.

The storage capacitor Cst is formed at a portion where the counter electrode 57 and the pixel electrode 59 overlap each other.

According to the conventional FFS mode liquid crystal display configured as described above, it can be seen that the counter electrode 57 is formed on the lower substrate, unlike the normal twisted nematic (TN) mode.

In this case, the common electrode line 53 including the counter electrode 57 has capacitance due to overlap with the data bus line 55 and storage capacitance formed at a portion overlapping with the pixel electrode 59.

Therefore, the conventional FFS mode liquid crystal display device as described above has the following problems.

In general, the signal distortion of the common electrode line in the FFS mode is caused by the resistance of the common electrode line 53 and the capacitance of the data bus line 55, and the storage capacitance of the pixel electrode 59. The amount of storage capacitance formed between and is so large that the RC delay of the common electrode line 53 is deepened.

Unlike the general TN mode liquid crystal display, the FFS mode liquid crystal display device is formed by connecting the common electrode line 53 (Vcom) to the transparent conductive film (ITO: Induim Tin Oxide) of the counter electrode on the lower substrate. The counter electrode has a storage capacitance of a size that spans the pixel electrode and the front surface of the pixel with an insulating layer interposed therebetween, resulting in a 7 to 8 times RC delay compared to the TN mode.

In the case of a small inch liquid crystal display, the storage capacitance of the common electrode line 53 when the common electrode line design is applied to the pixel structure has a small influence on the RC delay of the common electrode line 53 by 7 to 8 times that of the TN. In large monitors, large TVs, and wide types, the storage capacitance of one common electrode line 53 is 10 to 20 times larger than that of TN, resulting in damage to screen quality due to RC delay.

In particular, when driving the FFS mode with dot inversion, the data signals of R and B always have the same polarity in the R, G, and B strip arrays, and in the case of G, have the opposite polarities of R and B. In general screen driving, the polarities of the entire screen are conflicted with each other and become 0, but in a specific pattern (1 skip line and 2 skip dot patterns), as shown in FIG. 3, the polarities of + to-in the n-th gate line are shown. Will have

This polarity causes coupling distortion due to the RC delay in the common electrode line described above. In this case, the coupling distortion of the common electrode line is distorted in the direction of decreasing the brightness of R and B, and the brightness of G is increasing.

Due to the distortion of the Vcom, a greenish defect occurs in which the entire screen is closer to green.

Accordingly, the present invention has been made to solve the above problems, and provides an FFS mode liquid crystal display device suitable for improving screen quality by preventing the screen from becoming greenish due to distortion of the common voltage. There is a purpose.

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In the FFS mode liquid crystal display according to the present invention, a transparent counter electrode is formed on a lower substrate, and a common bus line is connected to the counter electrode. A unit pixel region is defined, the opposing electrodes corresponding to the unit pixel regions are divided into a plurality of regions, and the common electrode line is connected to each of the separated counter electrodes one to one to dedicate one unit pixel region. A plurality of the common electrode line in charge is configured.
Here, the counter electrode connected to each of the plurality of common electrode lines preferably forms a pixel electrode and a storage capacitance formed in a slit form in the unit pixel region.
In addition, the counter electrode may be formed of an opaque conductive film.
In addition, the FFS mode liquid crystal display device of the present invention includes a gate bus line and a data bus line arranged to cross each other to define a unit pixel region; A thin film transistor formed at an intersection of the gate bus line and the data bus line; A slit pixel electrode formed in the pixel region; Counter electrodes formed in the pixel region and divided into a plurality of regions to form a plurality of capacitances with the pixel electrode; And a plurality of common electrode lines formed in the pixel area in the same direction as the counter electrodes in the same direction as the gate bus lines, and connected to the counter electrodes in a one-to-one manner.
Hereinafter, an FFS mode liquid crystal display device of the present invention will be described with reference to the accompanying drawings.

First, the FFS mode LCD of the present invention forms a plurality of common electrode lines and counter electrodes per pixel to disperse the entire storage capacitance, thereby improving the screen quality by eliminating the signal delay (RC delay) of the common electrode lines. It is a technical feature.

To this end, in the present invention, a plurality of common electrode lines are formed per pixel, and respective counter electrodes are formed on each common electrode line, thereby causing Greenish, Crosstalk, etc., which are generated due to the delay of the common electrode lines. Reduces the failure of.

This will be described in more detail as follows.

In general, as shown in FIG. 4, the signal distortion of the common electrode is influenced by the capacitance and the storage capacitance between the data line and the counter electrode.

In this case, the degree of distortion is expressed as follows.

[Equation 1]

Vcom_RC = Vcom_R_tot × (Cstorage_tot + Cdata_com_cross) × Δd

In Equation 1, Vcom_RC is an RC delay applied to one common electrode line Vcom, Vcom_R_tot is a wiring resistance applied to one common electrode line, and Cstorage_tot is the sum of parts connecting the storage capacitance applied to each pixel to the common electrode line. , Cdata_com_cross is the sum of the portions connecting the capacitance between the data bus line and the common electrode line applied to each pixel to the common electrode line, and Δd is the data high voltage and the data low voltage, and represents the amount of change in the data voltage.

In this case, the coupling signal distortion affecting the greenish may be expressed by Equation 2 below.

[Equation 2]

Vcom_decay_peak_level = (Cdata_com_cross / Cdot_total) × Δd

Here, Cdot_total may be expressed as Equation 3 below.

[Equation 3]

Cdot_total = Cstorage_dot × Clc_frange

In this equation, Vcom_decay_peak_level is the maximum change amount of the coupled and distorted voltage, and Cdot_total represented by Equation 3 is the total amount of capacitance applied to one pixel.

When comparing the effect of the capacitance of Cstorage_tot on Vcom RC by pixel size, FFS pixel of 80㎛ of pixel size and TN mode of storage on common method use 5.2 times as much storage of FFS mode pixel. The capacity difference is shown, and the storage capacity of FFS pixels of 130µm and TN mode pixels is about 12 times the storage capacity.

Here, the storage capacity increases with increasing pixel area because the overlapping area of the pixel electrode of the FFS is multiplied by a multiplier, and TN is because the capacity of the storage capacitance is maintained or decreased by increasing the pixel electrode capacitance capacity. to be.

In addition, Cdata_cross capacitance is about 1/100 times the capacity of Cstorage capacitance. Since the impact on RC is minimal, the amount of RC delay is determined in the capacity of the storage capacitance.

Therefore, the RC delay in a large panel of 20 inches or more will have 10 times more RC delay than the TN mode of the same inch of storage on common due to the effect of storage capacitance.

Accordingly, in order to solve the above problem, the common wiring is formed of multiple wirings as shown in FIG. 5 so as to optimize the effect of the storage capacitance in the pixel applied to the common electrode line on the signal delay of the common electrode line.

5 is a layout diagram illustrating a unit cell of an FFS mode liquid crystal display according to an exemplary embodiment of the present invention, wherein the gate bus line 100 and the data bus line 200 are arranged to cross each other, A thin film transistor TFT is formed, and a slit pixel electrode 300 is formed in the pixel region defined by the gate bus line 100 and the data bus line 200.

A plurality of common electrode lines 400a and 400b are formed in the pixel area, and a plurality of counter electrodes 500a and 500b forming a storage capacitance with the pixel electrode 300 are formed.

For reference, in the exemplary embodiment of the present invention, two common electrode lines and two counter electrodes are used as an example. Hereinafter, for convenience of description, the common electrode line is defined as the first and second common electrode lines 400a and 400b and the counter electrode is defined as the first and second counter electrodes 500a and 500b.

As described above, when multiple common electrode lines are formed, a storage capacitance is formed by the pixel electrode 300 and the first counter electrode 500a in the unit pixel region, and the pixel electrode 300 and the second counter electrode 500b are formed. Since the storage capacitance is also formed between), the storage capacitance is divided into two parts within the unit pixel area.

At this time, the formation of the plurality of common electrode lines 400a and 400b in the unit pixel region does not cause the addition or change of the existing manufacturing process.

That is, a conventional FFS mode liquid crystal display device includes a first masking process for patterning a transparent conductive film used as a counter electrode, a second masking process for patterning a common electrode line and a gate bus line, and a channel layer of a thin film transistor (TFT). A third masking process for patterning, a fourth masking process for patterning the source / drain electrodes and data bus lines, a fifth masking process for forming contact holes, and a sixth masking process for pixel electrode patterning.

Accordingly, the FFS mode liquid crystal display device of the present invention uses the sixth masking process from the first masking process as it is, but in the first masking process of patterning the transparent conductive film used as the counter electrode, the transparent conductive film is formed in the unit pixel region. The number of common electrode lines to be separated may be separated, and in the second masking process of forming the common electrode line and the gate bus line, the common electrode lines may be patterned by the number of counter electrodes formed in the first masking process.

As described above, in the FFS mode LCD of the present invention, as shown in FIG. 5, the pixel electrode 300 is formed in a slit shape, and the first counter electrode 500a and the second counter electrode are formed at the portion between the slit and the slit. Pattern 500b to separate. At this time, the light leakage phenomenon and the non-opening area by patterning the first and second counter electrodes 500a and 500b between the slits are limited to additional parts of the common electrode line.

The RC delay of the common electrode line formed as described above may be calculated by Equation 4 below.

[Equation 4]

Vcom_RC = Vcom_R_tot × {(Cstorage_tot / 2) + (Cdata_com_cross)} × Δd

Here, in contrast to Equation 4 and Equation 1, Cstorage_tot is divided by the number of storage formations, and Cdata_com_cross is maintained at a predetermined amount in one common electrode line. As shown in FIG. 6, the Cdata_com_cross capacitance is kept different for each common electrode line in parallel, and as a result, Vcom_RC of each common electrode line is reduced to 1/2.

In this case, the coupling signal distortion may be expressed by Equation 5 below.

[Equation 5]

Vcom_decay_peak_level = (Cdata_com_cross / Cdot_total) × Δd

Here, Cdot_total may be expressed as Equation 6 below.

[Equation 6]

Cdot_total = (Cstorage_dot / 2) × Clc_frange

In this case, Equation 5 is the same as Equation 2, but when Equation 6 is compared with Equation 3, it decreases to 1/2 so that the result value of Equation 5 is increased.

That is, the value of Vcom_decay_peak_level increases, but the value of the entire Vcom_RC is reduced to half (1/2), and Vcom_decay_peak_level of one common electrode line is kept constant.

Thus, greenish and crosstalk defects due to Vcom distortion are solved.

The above embodiment has been described in the case where two common electrode lines are formed, but three may be formed.

For example, when three common electrode lines are formed, the RC delay of the common electrode line may be expressed as in Equation 7 below.

[Equation 7]

Vcom_RC = Vcom_R_tot × {(Cstorage_tot / 3) + (Cdata_com_cross)} × Δd

Comparing Equation 7 with Equation 6 above, Cstorage_tot is decreased, and Cdata_com_cross is increased due to an increase in common wiring.

However, since the Cstorage_tot value is larger than that of Cdata_com_cross, the total Vcom_RC is reduced to 1/3.

In this case, the coupling signal distortion may be expressed by Equation 8 below.

[Equation 8]

Vcom_decay_peak_level = (Cdata_com_cross / Cdot_total) × Δd

Here, Cdot_total may be expressed as Equation 9 below.

[Equation 9]

Cdot_total = (Cstorage_dot / 3) × Clc_frange

In this case, Equation 8 is the same as Equation 2, but when Equation 9 is compared with Equation 3, the Equation 8 is reduced to 1/3 so that the result value of Equation 8 is increased.

That is, the value of Vcom_decay_peak_level increases, but the value of the entire Vcom_RC is reduced to half (1/2), and Vcom_decay_peak_level of one common electrode line is kept constant.

Thus, greenish and crosstalk defects due to Vcom distortion are solved.

As such, when the storage capacitance of a predetermined value or more is formed, the storage capacitance is determined by dividing the n common pole lines, thereby minimizing the RC delay value of each common electrode line.

Although the embodiments of the present invention have been described above, it is clear that the present invention can use various changes, modifications, and equivalents, and that the above embodiments can be appropriately modified and applied in the same manner. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the FFS mode liquid crystal display device of the present invention has the following effects.

Regardless of pixel size and storage capacity, Greenish and Crosstalk phenomena caused by signal distortion of common electrode wiring are reduced to reduce signal distortion by reducing overall capacitance on common electrode line. Can be improved.

Claims (6)

In a fringe field switching mode liquid crystal display in which a transparent counter electrode is formed on a lower substrate and a common electrode line is connected to the counter electrode. A unit pixel area is defined by a gate bus line and a data bus line, and the counter electrodes corresponding to the unit pixel areas are divided into a plurality of areas to form a plurality of storage capacitances, and one to one on each of the separated counter electrodes. And a plurality of common electrode lines dedicated to one unit pixel area by connecting the common electrode lines. 2. The fringe field switching mode liquid crystal display of claim 1, wherein the counter electrodes respectively connected to the plurality of common electrode lines form a pixel electrode and a storage capacitance formed in a slit form in the unit pixel region. . delete delete The fringe field switching mode liquid crystal display device according to claim 1 or 2, wherein the counter electrode comprises an opaque conductive film. A gate bus line and a data bus line intersecting each other to define a unit pixel area; A thin film transistor formed at an intersection of the gate bus line and the data bus line; A slit pixel electrode formed in the pixel region; Counter electrodes formed in the pixel region and divided into a plurality of regions to form a plurality of capacitances with the pixel electrode; And And a plurality of common electrode lines formed in the same direction as the counter electrodes in the same direction as the gate bus line in the pixel area, and connected to the counter electrodes in a one-to-one manner. LCD display device.

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