KR100611762B1 - fabrication method of Thin Film Transitor - Google Patents

Abstract

Provided is a method of manufacturing a thin film transistor. The method includes forming a first amorphous silicon layer on an insulating substrate; Crystallizing the first amorphous silicon layer by SGS to form a first polycrystalline silicon layer; Forming a second amorphous silicon layer on the first polycrystalline silicon layer; Crystallizing the second amorphous silicon layer to form a second polycrystalline silicon layer, and then patterning the first and second polycrystalline silicon layers to form a semiconductor layer pattern; Forming a gate insulating film on the semiconductor layer pattern; And forming a gate electrode on the gate insulating film. By first crystallizing the amorphous silicon layer by the SGS method and then forming the amorphous silicon layer again and performing the second crystallization, the characteristics of the thin film transistor are improved, the device characteristics are uniform, and the amount of Ni in the channel portion is reduced to reduce the leakage current. There is an advantage to provide a method for manufacturing a thin film transistor that can remove the and improve the uniformity of the interfacial properties of the thin film transistor.

Seed, SGS method

Description

Manufacturing Method of Thin Film Transistor {fabrication method of Thin Film Transitor}             

1A to 1E are process flowcharts for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention;

2 is a cross-sectional view illustrating a method of manufacturing a thin film transistor according to a first embodiment of the present invention;

3 is a cross-sectional view illustrating a method of manufacturing a thin film transistor according to a second embodiment of the present invention;

4 is a cross-sectional view illustrating a method of manufacturing a thin film transistor according to a third embodiment of the present invention;

Figure 5 is a graph comparing the uniformity of the interface characteristics of the conventional thin film transistor and the interface characteristics of the thin film transistor according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 110 buffer layer

120: first amorphous silicon layer 125: first polycrystalline silicon layer

130, 250, 350, 450: seed 140: second amorphous silicon layer

145: second polycrystalline silicon layer 150: semiconductor layer pattern

230: first capping layer pattern 235: second capping layer

240, 340, 440: metal catalyst 330: first capping layer

335 second capping layer pattern 430 capping layer

The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor comprising primary crystallization of an amorphous silicon layer by the SGS method, and then again forming an amorphous silicon layer. will be.

In general, the polycrystalline silicon layer is widely used as a semiconductor layer for thin film transistors because of its advantages in that it can be applied to high field effect mobility, high speed operation circuits, and CMOS circuits. Thin film transistors using such polycrystalline silicon layers are mainly used in active elements of active matrix liquid crystal display (AMLCD) and switching elements and driving elements of organic electroluminescent element (OLED).

In this case, the polycrystalline silicon layer used for the thin film transistor may be fabricated using a direct deposition method, a technique using high temperature heat treatment, or a laser heat treatment method. Although the laser heat treatment method is capable of low temperature processing and can implement high field effect mobility, a lot of alternative technologies have been studied because expensive laser equipment is required.

Currently, the method of crystallizing amorphous silicon using a metal has been studied a lot because it has the advantage that can be crystallized in a short time at a lower temperature than the solid phase crystallization (SPC, Solid Phase Crystallization). Crystallization using metal is divided into Metal Induced Crystallization (MIC) and Metal Induced Lateral Crystallization (MILC). However, even in the method using a metal, there is a problem in that device characteristics of the thin film transistor are degraded due to metal contamination.

On the other hand, in order to reduce the amount of metal and to form a high quality polycrystalline silicon layer, a technique of forming a high quality polycrystalline silicon layer by high temperature treatment, rapid thermal treatment or laser irradiation by adjusting the ion concentration of the metal through an ion implanter and a metal induced crystallization method In order to flatten the surface of the polycrystalline silicon layer, a method of mixing a viscous organic film and a liquid metal, depositing a thin film by spin coating, and then crystallizing the same by a heat treatment process has been developed. However, even in the crystallization method, there is a problem in terms of size and uniformity of grain size which are most important in the polycrystalline silicon layer.

In order to solve the above problem, a method of manufacturing a polycrystalline silicon layer by a crystallization method using a cover layer (Korean Publication No. 2003-0060403) has been developed. The method comprises forming an amorphous silicon layer on a substrate, forming a capping layer thereon, and then depositing a metal catalyst layer on the capping layer to diffuse the metal catalyst through the capping layer to the amorphous silicon layer by heat treatment or laser. After forming a seed, a polycrystalline silicon layer is obtained using the same. The method has the advantage that the metal catalyst can be prevented more than necessary because the metal catalyst diffuses through the cover layer. However, even in the above method, there is a problem that it is difficult to control uniform low concentration of the metal catalyst, and it is difficult to control the location, growth direction, and size of crystal grains, and the surface of the silicon layer is damaged in the process of removing the capping layer. There may be a problem that the uniformity of the interfacial properties of the thin film transistor is reduced.

The technical problem to be achieved by the present invention is to solve the problems of the prior art described above, by forming a seed through the patterning of the capping layer to crystallize, thereby improving the device characteristics by adjusting the size and position and direction of crystal growth It is an object of the present invention to provide a method for manufacturing a thin film transistor which can improve the uniformity of the interfacial properties of the thin film transistor and at the same time obtain a uniform value.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a thin film transistor. The method includes forming a first amorphous silicon layer on an insulating substrate; Crystallizing the first amorphous silicon layer by SGS to form a first polycrystalline silicon layer; Forming a second amorphous silicon layer on the first polycrystalline silicon layer; Crystallizing the second amorphous silicon layer to form a second polycrystalline silicon layer, and then patterning the first and second polycrystalline silicon layers to form a semiconductor layer pattern; Forming a gate insulating film on the semiconductor layer pattern; And forming a gate electrode on the gate insulating film.

The second polycrystalline silicon layer may crystallize the second amorphous silicon layer by heat treatment, or may be crystallized by a laser.

Crystallization by the SGS method comprises the steps of forming and patterning a first capping layer on the first amorphous silicon layer; Forming a second capping layer on the first capping layer pattern; Forming a metal catalyst layer on the second capping layer; Diffusing the metal catalyst; And removing the second capping layer and the first capping layer pattern after crystallizing the first amorphous silicon layer.

Crystallization by the SGS method comprises the steps of forming a first capping layer on the first amorphous silicon layer; Forming a second capping layer on the first capping layer and patterning the second capping layer; Forming a metal catalyst layer on the second capping layer pattern; Diffusing the metal catalyst; And removing the second capping layer pattern and the first capping layer after crystallizing the first amorphous silicon layer.

Crystallization by the SGS method may include forming a capping layer and forming a groove on the first amorphous silicon layer; Forming a metal catalyst layer on the capping layer; Diffusing the metal catalyst; And removing the capping layer after crystallizing the first amorphous silicon layer.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings in order to describe the present invention in more detail. Like numbers refer to like elements throughout.

1A to 1E are process flowcharts for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention, and FIGS. 2 to 4 are thin film transistors according to the first, second and third embodiments of the present invention, respectively. 5 is a graph comparing the uniformity of the interfacial properties of the thin film transistor according to the present invention and the uniformity of the interfacial properties of the conventional thin film transistor.

Referring to FIG. 1A, a buffer layer 110 is formed on a substrate 100. The substrate 100 preferably uses an insulating substrate such as glass, and the buffer layer 110 serves to protect the semiconductor layer formed in a subsequent process from impurities flowing out of the substrate 100. The buffer layer 110 is preferably formed of a silicon oxide film.

The first amorphous silicon layer 120 is formed on the entire surface of the substrate on which the buffer layer 110 is formed. The first amorphous silicon layer 120 may be performed using chemical vapor deposition (CVD).

Referring to FIG. 1B, the first amorphous silicon layer 120 is crystallized using the SGS method to form the first polycrystalline silicon layer 125. Seeds 130 and first grain boundaries 140a are formed in the first polycrystalline silicon layer 125.

The SGS (Super Grain Silicon) method refers to a crystallization method capable of controlling the size of the crystal grains, the location and direction of crystal growth by crystallization by forming seeds through selective diffusion of a metal catalyst. Through the SGS method, grains ranging in diameter from tens to hundreds of micrometers can be grown. In the present invention, the crystallization by the SGS method is exemplified through various embodiments such as a lamination structure of a capping layer and a method of patterning.

Referring to FIG. 2, a first capping layer is formed on the substrate 100 on which the buffer layer 110 and the first amorphous silicon layer 120 are sequentially formed. The first capping layer may be formed of a silicon nitride film or a silicon oxide film, and may be formed using a plasma enhanced chemical vapor deposition (PECVD) method. Subsequently, the first capping layer is patterned to form a first capping layer pattern 230. In this case, the first capping layer may be patterned by adjusting a formation position of a seed or a growth direction of crystallization, which will be described later.

The first capping layer pattern 230 adjusts the thickness of the silicon nitride layer or the silicon oxide layer or makes the metal catalyst impossible to diffuse by adjusting the density. That is, the first capping layer pattern 230 serves as a metal catalyst non-diffusion layer.

Subsequently, a second capping layer 235 is formed on the first capping layer pattern 230. The second capping layer 235 may be formed of a silicon nitride layer or a silicon oxide layer, and may be thinner than the first capping layer pattern 230 or may be adjusted to a lower density than the first capping layer pattern 230. The metal catalyst is adjusted to be diffusible. That is, the second capping layer 235 plays a role of the metal catalyst spreadable layer. In general, since the oxide film or the nitride film acts as a barrier in the diffusion of impurities, the metal catalyst can be prevented from diffusing by increasing the density of the silicon oxide film or the silicon nitride film. On the other hand, lowering the density of the silicon oxide film or the silicon nitride film facilitates diffusion of the metal catalyst.

Subsequently, a metal catalyst 240 layer is formed on the second capping layer 235. The metal catalyst 240 is preferably nickel, and the metal catalyst 240 layer may be formed using a sputter. In addition, the method may be formed by ion implantation, and may be formed using a plasma. The method using plasma may be formed by placing a metal material on the second capping layer 235 and exposing it to a plasma. .

Subsequently, the metal catalyst 240 is diffused. The diffusion may be performed by heat treatment at 200 to 700 ° C. for 1 hour, and the metal catalyst 240 passes through the second capping layer 235 to the first amorphous silicon layer 120 through heat treatment. Spreads. The diffused metal catalyst 240 forms a seed 250 in the first amorphous silicon layer 120. The seed 250 refers to a metal silicide in which a metal catalyst is formed to meet silicon. Crystallization, which will be described later, is performed from the seed 250. Usually, only about 1/100 of the metal catalyst diffuses to form the seed. The metal catalyst that is not diffused by the first capping layer pattern 230 is left in the second capping layer 235.

Subsequently, the first amorphous silicon layer 120 is crystallized to form the first polycrystalline silicon layer 125. The crystallization may be performed through heat treatment, and the heat treatment may be performed by heating for a long time in a crucible. At this time, the crystallization may be made at 400 to 1000 ° C, preferably made at 550 to 600 ° C. When the heat treatment at the temperature is grown from the seed 250 to the side to meet the neighboring crystal grains to form a grain boundary (140a of Figure 1) is completely crystallized.

Referring to FIG. 3, a first capping layer 330 is formed on the substrate 100 on which the first amorphous silicon layer 120 is formed. The second capping layer is formed on the first capping layer 330 and then patterned. The second capping layer pattern 335 may be formed of a silicon nitride layer or a silicon oxide layer, and the thickness of the second capping layer pattern 335 may be greater than that of the first capping layer 330, or the density may be greater than that of the first capping layer 330. Adjust the catalyst to be non-diffused. That is, the second capping layer pattern 335 serves as a metal catalyst non-diffusion layer.

Except for the above, it is the same as the manufacturing method of the thin film transistor according to the first embodiment of the present invention.

Referring to FIG. 4, a capping layer 430 is formed on the substrate 100 on which the first amorphous silicon layer 120 is formed. Subsequently, a groove is formed in the capping layer 430, and a metal catalyst 440 layer is formed on the capping layer 430. Unlike the first and second embodiments of the present invention, only one capping layer is formed in the third embodiment of the present invention. The capping layer 430 may be formed of a silicon nitride film or a silicon oxide film, and a portion where the groove is formed is thin so that the metal catalyst 440 may be diffused.

Except for the above, it is the same as the manufacturing method of the thin film transistor according to the first embodiment of the present invention.

As described above, when the amorphous silicon layer is crystallized by the SGS method, the size of the crystal grains formed in the polycrystalline silicon layer is large, so that the thin film transistor having good characteristics and uniform characteristics can be manufactured.

Meanwhile, in the process of manufacturing a thin film transistor, the step of removing the capping layer is performed. This step is usually carried out by washing with HF solution. However, the surface of the silicon layer may be damaged in the process of removing the capping layer using the HF solution. In particular, seed and grain boundaries with relatively low crystallinity may be more damaged. Since the surface of the silicon layer means an interface between the silicon layer and the gate insulating layer, damage to the surface may cause deterioration of the characteristics of the thin film transistor at the interface.

In addition, since a small amount of Ni remains, leakage current may occur, and there is a need for improvement.

Referring to FIG. 1C, a second amorphous silicon layer 140 is formed on the first polycrystalline silicon layer 125. The second amorphous silicon layer 140 may be performed using chemical vapor deposition (CVD).

Next, the second amorphous silicon layer 140 is crystallized. The crystallization may be made through heat treatment. The heat treatment may be performed by heating in a crucible (Furnace) for a long time, or may be made by Rapid Thermal Annealing (RTA). At this time, the crystallization temperature may be made at 400 to 1000 ° C, preferably 550 to 750 ° C.

When the heat treatment is performed, a small amount of Ni remaining in the first polycrystalline silicon layer 125 without being formed as a seed diffuses into the second amorphous silicon layer 140 to crystallize the second amorphous silicon layer 140. Promote In addition, crystallization of the second amorphous silicon layer 140 may be effected by the size, shape, or direction of the crystal grains formed on the first polycrystalline silicon layer 125.

In addition, the crystallization may be made through a laser. When the laser is irradiated to the second amorphous silicon layer 140, the second amorphous silicon layer 140 is crystallized by the absorbed heat. Same as crystallization by heat treatment except as mentioned above.

Referring to FIG. 1D, a second polycrystalline silicon layer 145 is formed on the first polycrystalline silicon layer 125. It can be seen that the grain boundary 140b formed in the second polycrystalline silicon layer 145 is formed according to the grain boundary 140a formed in the first polycrystalline silicon layer 125.

Therefore, crystal grains having excellent crystallinity and large size may be formed in the second polycrystalline silicon layer 145. In addition, since Ni is hardly present on the surface of the second polycrystalline silicon layer 145, leakage current can be reduced, and since there is no damage to the surface of the silicon layer due to HF cleaning, the interfacial characteristics of the thin film transistor can be made uniform.

Referring to FIG. 5, the vertical axis of the graph represents an s-factor (V / dec) value representing the interface characteristics of the thin film transistor, and the horizontal axis of the graph represents 25 thin film transistors each selected to measure uniformity. . The S factor value of the conventional thin film transistor is about 0.48 to 0.66, indicating that the uniformity is not good. On the other hand. The value of the S factor of the thin film transistor according to the present invention shows a value from about 0.48 to 0.58, indicating that the property is not only improved overall but also more uniform than the uniformity of the interface property of the conventional thin film transistor. Can be.

Referring to FIG. 1E, the first and second polycrystalline silicon layers 125 and 145 are patterned and the source / drain regions 150S and 150D and the channel layer 150C are formed through an ion implantation process. That is, the semiconductor layer pattern 150 is formed.

After the gate insulating layer 160 is formed on the semiconductor layer pattern 150, the metal layer and the photoresist layer are sequentially stacked on the gate insulating layer 160. The gate electrode 170 is formed by patterning the photoresist layer and etching the metal layer using the patterned photoresist layer as a mask. The thin film transistor can be completed using the resultant product.

As described above, according to the present invention, the amorphous silicon layer is first crystallized by the SGS method, and then the amorphous silicon layer is formed again to perform secondary crystallization, thereby controlling the size of the crystal grains and the position and direction in which the crystals are grown. In addition to improving the characteristics and obtaining a uniform value, there is an advantage to provide a method for manufacturing a thin film transistor which can reduce the amount of Ni to reduce the leakage current and improve the uniformity of the interfacial characteristics of the thin film transistor.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (13)

Forming a first amorphous silicon layer on the substrate; Crystallizing the first amorphous silicon layer by SGS to form a first polycrystalline silicon layer; Forming a second amorphous silicon layer on the first polycrystalline silicon layer; Crystallizing the second amorphous silicon layer to form a second polycrystalline silicon layer, and then patterning the first and second polycrystalline silicon layers to form a semiconductor layer pattern; Forming a gate insulating film on the semiconductor layer pattern; And And forming a gate electrode on the gate insulating film. The method of claim 1, The second polycrystalline silicon layer is a method of manufacturing a thin film transistor, characterized in that for crystallizing the second amorphous silicon layer by heat treatment. The method of claim 1, The second polycrystalline silicon layer is a method of manufacturing a thin film transistor, characterized in that the crystallization of the second amorphous silicon layer by a laser. The method of claim 1, Crystallization by the SGS method Forming and patterning a first capping layer on the first amorphous silicon layer; Forming a second capping layer on the first capping layer pattern; Forming a metal catalyst layer on the second capping layer; Diffusing a metal catalyst of the metal catalyst layer; And And removing the second capping layer and the first capping layer pattern after crystallizing the first amorphous silicon layer. The method of claim 4, wherein The first and second capping layer is a method of manufacturing a thin film transistor, characterized in that consisting of a silicon nitride film or a silicon oxide film. The method of claim 4, wherein The thickness of the first capping layer pattern is thicker than the thickness of the second capping layer manufacturing method of the transistor. The method of claim 4, wherein The density of the first capping layer pattern is greater than the density of the second capping layer manufacturing method of the thin film transistor. The method of claim 1, Crystallization by the SGS method Forming a first capping layer on the first amorphous silicon layer; Forming a second capping layer on the first capping layer and patterning the second capping layer; Forming a metal catalyst layer on the second capping layer pattern; Diffusing a metal catalyst of the metal catalyst; And Removing the second capping layer pattern and the first capping layer after crystallizing the first amorphous silicon layer. The method of claim 8, The first and second capping layer is a method of manufacturing a thin film transistor, characterized in that consisting of a silicon nitride film or a silicon oxide film. The method of claim 8, And the thickness of the second capping layer pattern is thicker than the thickness of the first capping layer. The method of claim 8, The density of the second capping layer pattern is a method of manufacturing a thin film transistor, characterized in that greater than the density of the first capping layer. The method of claim 1, Crystallization by the SGS method Forming a capping layer and forming a groove on the first amorphous silicon layer; Forming a metal catalyst layer on the capping layer; Diffusing the metal catalyst of the metal catalyst; And And removing the capping layer after crystallizing the first amorphous silicon layer. The method of claim 12, The capping layer is a method of manufacturing a thin film transistor, characterized in that consisting of a silicon nitride film or a silicon oxide film.

Images