KR100610283B1 - Memory - Google Patents

Abstract

Provides a memory capable of suppressing the disturb phenomenon. In this memory, when the rewrite operation is performed on some selection storage means or the rewrite operation is not performed on all the selection storage means, each of the selected word lines and the bit lines corresponding to the non-rewrite storage means are respectively written. While maintaining the potential difference with each other at a predetermined value or less, the length of the period for applying the voltage for rewriting to each of the selected word line and the bit line corresponding to the rewriting memory means is not increased. Is different from the length of the transition period of at least one of the potentials among the bit lines corresponding to the memory means.

Word line, memory, transition period, rewrite

Description

Memory {MEMORY}

1 is a block diagram showing the overall configuration of a ferroelectric memory of a simple matrix type according to a first embodiment of the present invention.

Fig. 2 is a diagram showing data stored in a selected word line and a memory cell connected to the selected word line of the memory cell array according to the first embodiment of the present invention.

3 is a diagram showing definitions of cell regions of a memory cell array according to a first embodiment of the present invention;

4 is a voltage waveform diagram for explaining a read-write operation of a memory according to the first embodiment of the present invention;

Fig. 5 is a voltage waveform diagram of an internal signal used for supplying voltage to word lines and bit lines of a memory according to the first embodiment of the present invention.

FIG. 6 is a voltage waveform diagram showing another example of a method of applying a voltage to a word line and a bit line of a memory according to the first embodiment of the present invention shown in FIG.

FIG. 7 is a view for explaining a problem in the rewrite operation in the voltage waveform diagram shown in FIG. 6; FIG.

Fig. 8 is a circuit diagram showing the construction of a state machine circuit for generating a state signal according to the first embodiment of the present invention.

FIG. 9 is a circuit diagram for explaining the configuration of a modification of the state machine circuit according to the first embodiment shown in FIG.

FIG. 10 is a circuit diagram for explaining the configuration of a modification of the state machine circuit according to the first embodiment shown in FIG.

FIG. 11 is a circuit diagram for explaining the configuration of a modification of the state machine circuit according to the first embodiment shown in FIG.

FIG. 12 is a circuit diagram for explaining the configuration of a modification of the state machine circuit according to the first embodiment shown in FIG.

FIG. 13 is a circuit diagram for explaining the configuration of a modification of the state machine circuit according to the first embodiment shown in FIG.

Fig. 14 is a circuit diagram showing the configuration of a word line source driver for generating a word line source control signal.

FIG. 15 is a circuit diagram showing a configuration of a row decoder of a memory according to the first embodiment of the present invention shown in FIG.

Fig. 16 is a circuit diagram showing the configuration of a bit line source driver for generating a bit line source control signal.

FIG. 17 is a circuit diagram showing a configuration of a sense amplifier of a memory according to the first embodiment of the present invention shown in FIG.

FIG. 18 is a voltage waveform diagram showing a method of applying a voltage to a word line and a bit line of a memory according to a second embodiment of the present invention; FIG.

Fig. 19 is a circuit diagram showing the construction of a state machine circuit which generates a state signal of the memory according to the second embodiment of the present invention.

20 is a voltage waveform diagram showing a method of applying a voltage to a word line and a bit line of a memory according to a third embodiment of the present invention;

Fig. 21 is a circuit diagram showing the construction of a state machine circuit which generates a state signal of the memory according to the third embodiment of the present invention.

Fig. 22 is a voltage waveform diagram showing a method of applying a voltage to a word line and a bit line of a memory according to a modification of the present invention.

Fig. 23 is a voltage waveform diagram of an internal signal used to supply voltage to word lines WL and bit lines BL of a memory according to a modification of the present invention.

FIG. 24 is a circuit diagram showing the construction of a state machine circuit which generates a state signal of the memory according to the modification of the present invention shown in FIG.

Fig. 25 is a diagram showing the configuration of a memory cell of a conventional DRAM.

Fig. 26 is a sectional view showing the structure of a trench capacitor of a conventional DRAM.

Fig. 27 is an equivalent circuit diagram showing a memory cell of a conventional one transistor one capacitor type ferroelectric memory.

Fig. 28 is an equivalent circuit diagram showing a memory cell array of a conventional simple matrix ferroelectric memory.

Fig. 29 is a hysteresis diagram for explaining the operation of a conventional simple matrix ferroelectric memory.

30 is a hysteresis diagram for explaining a disturb phenomenon in a conventional ferroelectric memory of a simple matrix method.

Fig. 31 is an equivalent circuit diagram showing a memory cell of a conventional one transistor ferroelectric memory.

Fig. 32 is a hysteresis diagram for explaining the operation of a conventional one transistor ferroelectric memory.

Fig. 33 is an equivalent circuit diagram for explaining a voltage application state at the time of writing of the conventional single transistor ferroelectric memory shown in Fig. 31;

Fig. 34 is an equivalent circuit diagram for explaining a voltage application state during standby of the conventional one transistor ferroelectric memory shown in Fig. 31;

<Explanation of symbols for the main parts of the drawings>

101: select transistor

102: capacitor

102a: upper electrode

102b: dielectric film

102c: lower electrode

The present invention relates to a memory, and more particularly to a memory having a storage means connected between a word line and a bit line.

(Explanation of background technology)

Conventionally, volatile memory and nonvolatile memory are known as semiconductor memories. In addition, DRAM (Dynamic Random Access Memory) is known as a volatile memory, and flash EEPROM (Electrically Erasable and Programmable Read Only Memory) is known as a nonvolatile memory. DRAM and flash EEPROMs are widely used because they can be highly integrated.

Fig. 25 is an equivalent circuit diagram showing the configuration of a memory cell of a conventional DRAM. 26 is a cross-sectional view showing the structure of a trench capacitor used in a conventional DRAM. First, referring to FIG. 25, a memory cell 103 of a DRAM as a conventional volatile memory is composed of one select transistor 101 and one capacitor 102. The information of the memory cell is stored in the capacitor 102 as electric charges. When reading the information of the memory cell, the word transistor WL rises, so that the selection transistor 101 is turned on. As a result, the cell capacitance Ccell and the bit line capacitance Cbl are capacitively combined. Thereby, since the bit line potential is determined by the amount of charge stored in the memory cell, the potential can be read out.

In the memory cell of the conventional DRAM having the above-described configuration, in order to ensure the cell capacity Ccell of the capacitor 102 even in the case of miniaturization, as shown in FIG. 26, the upper electrode constituting the capacitor 102 ( Trench type capacitors in which 102a, the lower electrode 102c and the dielectric film 102b extend in the longitudinal direction are used. However, if further miniaturization proceeds, it becomes difficult to secure the capacity of the capacitor 102 even with the trench type capacitor shown in FIG. In other words, the high integration of DRAM due to the reduction of design rules is approaching its limit.

In addition, in a flash EEPROM (hereinafter referred to as a flash memory) as a nonvolatile memory, a memory cell of a CHE (channel column electron) writing system such as a stack type and a split gate type has a limitation in miniaturization of a channel length. Further, in a memory cell of an FN (Fowler Node Heim) write method such as a NAND type, the limit of miniaturization is equivalent to that of a logic transistor. However, the operation of the flash memory requires a high voltage of 15 V to 20 V. When the low power supply voltage of the logic transistor proceeds, the generation efficiency when generating a high voltage of 15 V to 20 V from the low power supply voltage decreases. For this reason, since power consumption increases and the area of a charge pump part also becomes large, there exists a problem which hinders refinement | miniaturization.

On the other hand, a ferroelectric memory is known as one of the nonvolatile memories that are drawing attention recently. This ferroelectric memory is a memory that uses pseudo capacitance change due to the polarization direction of the ferroelectric as a memory element. This ferroelectric memory is, in principle, capable of rewriting data at high speed and at low voltage, and thus has been spotlighted as an ideal memory having both the advantages of high speed and low voltage DRAM and the advantages of nonvolatile flash memory.

Memory cell systems of ferroelectric memories are broadly classified into three types: one transistor, one capacitor, one simple matrix, and one transistor. Fig. 27 is an equivalent circuit diagram showing a memory cell of a ferroelectric memory of one transistor and one capacitor system. 28 is an equivalent circuit diagram showing a memory cell array of a ferroelectric memory of a simple matrix method. FIG. 29 is a hysteresis diagram for explaining the operation of the simple matrix ferroelectric memory, and FIG. 30 is a hysteresis diagram for explaining the disturb phenomenon in the simple matrix ferroelectric memory. FIG. 31 is an equivalent circuit diagram showing a memory cell of a one transistor ferroelectric memory, and FIG. 32 is a hysteresis diagram for explaining the operation of the one transistor ferroelectric memory. FIG. 33 is an equivalent circuit diagram for explaining a voltage application state during the writing of the one-transistor ferroelectric memory shown in FIG. 31, and FIG. 34 is a standby state of the one-transistor ferroelectric memory shown in FIG. It is an equivalent circuit diagram for demonstrating a voltage application state.

First, as shown in FIG. 27, the memory cell 113 of the one transistor one capacitor ferroelectric memory is composed of one selection transistor 111 and one ferroelectric capacitor 112 similarly to DRAM. The difference from the DRAM is that the capacitor is the ferroelectric capacitor 112. In operation, the selection transistor 111 is turned on because the word line WL rises. As a result, the capacitor capacitor Ccell of the ferroelectric capacitor 112 and the bit line capacitor Cbl are connected. Subsequently, the plate line PL is pulse driven, so that different charges in the polarization direction of the ferroelectric capacitor 112 are transferred to the bit line BL. As in the case of DRAM, data is read as the voltage of the bit line BL.

In this one transistor one capacitor ferroelectric memory, since the structure is similar to that of DRAM, there is a limit to the miniaturization of the ferroelectric capacitor 112. For this reason, there is a limit to high integration like DRAM.

Next, with reference to FIGS. 28-30, the ferroelectric memory of a simple matrix system is demonstrated. As shown in FIG. 28, the memory cell 121 of the simple matrix ferroelectric memory has a ferroelectric capacitor 122 positioned at an intersection of a word line WL, a bit line BL, and a word line WL and a bit line BL. Consists of

One end of the ferroelectric capacitor 122 is connected to the word line WL, and the other end of the ferroelectric capacitor 122 is connected to the bit line BL. In this simple matrix ferroelectric memory, since the potential due to the capacitive coupling between the bit line BL and the ferroelectric capacitor 122 is read out, the capacity must be secured as in DRAM. However, in this simple matrix ferroelectric memory, since the memory cell 121 is constituted only by the ferroelectric capacitor 122, and there is no selection transistor, the degree of integration can be higher than that of the one transistor one capacitor method.

Here, the operation of the simple matrix ferroelectric memory will be described with reference to FIGS. 28 and 29. In addition, the voltage applied to each cell at the time of reading / writing is shown in Table 1 below.

Standby Reading Entry "1" Entry "0" WL optional 1 / 2VCC VCC 0 VCC Non-selective WL 1 / 2VCC 1 / 3VCC 2 / 3VCC 1 / 3VCC Select BL 1 / 2VCC 0 → Floating VCC 0 Unselected BL 1 / 2VCC 2 / 3VCC 1 / 3VCC 2 / 3VCC

In the write operation, both ends of the ferroelectric capacitor 122 are at the same potential in the standby state. When data "0" is written, VCC is applied to the word line WL and 0V is applied to the bit line BL. At this time, a voltage of VCC is applied to the ferroelectric capacitor 122. This shifts to the point A shown in FIG. Thereafter, when both ends of the ferroelectric capacitor 122 are set to the same potential, the transition to "0" shown in FIG. When data "1" is written, 0 V is applied to the word line WL and VCC is applied to the bit line BL. At this time, a voltage of -VCC is applied to the ferroelectric capacitor 122. This shifts to the point B of FIG. Thereafter, when both ends of the ferroelectric capacitor 122 are set to the same potential, the transition to "1" shown in FIG.

In the read operation, first, the bit line BL is precharged to 0V. Then, the word line WL is raised to VCC. This voltage VCC is capacitively divided into CFE and CBL when the capacitance CFE of the ferroelectric capacitor 122 and the parasitic capacitance of the bit line BL are CBL. The capacitance CFE of the ferroelectric capacitor 122 can be approximated as C0 or C1 based on the retained data. Therefore, the potential of the bit line BL is represented by the following equations (1) and (2).

The above equation (1) shows the potential V0 of the bit line BL when the data "0" is held, and the above equation (2) shows the potential V1 of the bit BL when the data "1" is held.

Data is read by discriminating the potential difference between the bit line potential V0 of the above formula (1) and the bit line potential V1 of the above formula (2) by the read amplifier. At the time of reading this data, the data of the memory cell is destroyed, so that after the data is read, a write operation (restoration) according to the read data is performed.

In addition, the simple matrix ferroelectric memory has a problem of disturbing data of unselected cells. That is, a voltage of 1/3 VCC is applied to all unselected memory cells at the time of writing and reading. Therefore, as shown in FIG. 30, the amount of polarization decreases due to the hysteresis characteristics of the ferroelectric, resulting in data deletion.

Subsequently, a single transistor ferroelectric memory will be described with reference to FIGS. 31 to 34. The memory cell 131 of the one transistor ferroelectric memory has a structure in which a ferroelectric capacitor 132 is connected to a gate of the MOS transistor 133 as shown in FIG. In this one-transistor ferroelectric memory, one end of the ferroelectric capacitor 132 is connected to the word line WL, and the other end of the ferroelectric capacitor 132 is connected to the gate of the MOS transistor 133 constituting the cell transistor. Connected. In this one-transistor ferroelectric memory, the threshold voltage of the MOS transistor 133 changes according to the polarization direction of the ferroelectric capacitor 132, so that the memory cell current changes. By determining the change in this memory cell current, data is read. In this one-transistor ferroelectric memory, data is read by detecting a memory cell current. Therefore, as in the one-transistor one-capacitor ferroelectric memory shown in Fig. 27, the ferroelectric capacitor is considered in consideration of the bit line capacity. It is not necessary to increase the capacitor capacity to some extent. For this reason, since the ferroelectric capacitor 132 can be made small, it is suitable for miniaturization.

The operation of the one transistor ferroelectric memory will be described below. First, in the standby state, all word lines WL, bit lines BL, and source lines SL are 0V. In the write operation, when writing the data "1", Vpp (step-up voltage) is applied to the word line WL. At this time, the gate capacitance of the MOS transistor 133 and the potential-divided potential VCC are applied to the ferroelectric capacitor 132. Thereby, although it is an initial state, it transfers to the point A shown in FIG. Subsequently, when the word line WL is returned to 0 V, the word line WL transitions to the data "1" shown in FIG. When data "0" is written, 0 V is applied to the word line WL and Vpp is applied to the bit line BL. In this case, a voltage of -VCC is applied to the ferroelectric capacitor 132. This shifts to the point B shown in FIG. After that, when the bit line BL is returned to 0V, the transition to the data "0" shown in FIG.

In the read operation of the one-transistor ferroelectric memory, the word line WL is raised to a voltage Vr that does not polarize inversion. As a result, the gate voltage of the cell transistor (MOS transistor) 133 changes according to the writing state. Since the current flowing through the cell transistor 133 is different due to the change in the gate voltage of the cell transistor 133, the current difference is read out through the bit line BL. In other words, in the single-transistor ferroelectric memory, the current of the cell transistors is read instead of the potential difference due to the capacitive coupling between the ferroelectric capacitor and the bit line capacitance, so that polarization inversion at the time of reading is not necessary. For this reason, nondestructive reading is possible.

However, in this single transistor ferroelectric memory, there is a problem of disturbing unselected cells as in the above-described simple matrix ferroelectric memory. In addition, the reverse bias state to the ferroelectric capacitor 132 continues, so that there is also a problem of so-called reverse bias retention in which data changes. That is, when data is written, as shown in FIG. 33, after writing data by applying Vpp to the word line WL, and returning to the standby state, as shown in FIG. 34, the potential opposite to the polarization is shown. Is still applied. For this reason, there exists a problem that data holding time becomes short.

Therefore, conventionally, a method of reducing the disturb phenomenon caused by the unselected cells of the single transistor ferroelectric memory has been proposed. Such a method is disclosed, for example, in Japanese Patent Laid-Open No. 10-64255. In the data writing process of Japanese Patent Laid-Open No. 10-64255, first of all, as a first procedure, + V to the word line of the selected cell, 1 / 3V to the other word line, 0V to the bit line of the selected cell, and the like. Apply a voltage of 2 / 3V to the bit line. Subsequently, as a second procedure, a voltage of 0V is applied to the word line of the selected cell, 1 / 3V to the other word line, 1 / 3V to the bit line of the selected cell, and 0V to the other bit line. In the first procedure, -V is applied to the word line of the selected cell, -1 / 3V to the other word line, 0V to the bit line of the selected cell, and -2 / 3V to the other bit line, respectively. In the second procedure subsequent to this, 0V is applied to the word line of the selected cell, -1 / 3V to the other word line, -1 / 3V to the bit line of the selected cell, and 0V to the other bit line, respectively. As a result, since a voltage of 1 / 3V having different polarities is applied once to most cells of the unselected cells through the first and second procedures, the disturb phenomenon can be greatly reduced.

However, in the technique disclosed in Japanese Patent Laid-Open No. 10-64255, since no voltage is applied in the second procedure with respect to the memory cell that shares the word line and the bit line with the selected cell among the unselected cells, There was a problem in that the disturbance of the cells could not be avoided. Moreover, in the said patent document 1, the method of reducing the disturbance phenomenon at the time of reading is not described at all.

The present invention has been made to solve the above problems, and one object of the present invention is to provide a memory capable of suppressing the disturb phenomenon.

In order to achieve the above object, the memory according to the first aspect of the present invention includes a bit line, a word line arranged to intersect the bit line, and storage means connected between the bit line and the word line. In addition, when the read operation is performed on the selection storage means connected to the selected word line, and then the rewriting operation is performed on some selection storage means or the rewriting operation is not performed on all the selection storage means. Each of the bit lines corresponding to the word line and the non-rewritable storage means is raised while maintaining the potential difference of each other below a predetermined value, and is rewritten to each of the selected word lines and the bit lines corresponding to the rewritten memory means. The length of the period for applying the voltage for the mouth is different from the length of the transition period of the potential of at least one of the word line and the bit line corresponding to the non-rewritten memory means. In addition, the voltage for rewriting is preferably a voltage pulse. The transition period means an interval at which the potential of at least one of the word line and the bit line corresponding to the non-rewritten memory means is changed at the time of rising.

In the memory according to this first aspect, as described above, when the read operation is performed on the selection storage means connected to the selected word line, and then the rewrite operation is performed on some selection storage means, the rewrite operation is performed. Is adjusted, the voltage in the first direction and the voltage having the electric field inverse to the first direction are the same for the non-selected storage means connected to at least word lines other than the selected word line through the read operation and the rewrite operation. The number of times can be applied. Thereby, the disturb phenomenon at the time of the read operation of the unselected storage means connected to word lines other than the selected word line can be suppressed. In addition, the potential difference of the predetermined value is increased during the rewrite operation by raising each of the selected word lines and the bit lines corresponding to the non-rewritable storage means while keeping the potential difference between each other below a predetermined value. If the word line is kept below the potential difference between the bit line corresponding to the non-rewritten memory means, the selected word line and the non-rewritten memory means are raised in the process of raising the selected word line and the bit line corresponding to the non-rewritten memory means. It is possible to suppress that the potential difference between the corresponding bit line is larger than the potential difference between the selected word line during the rewrite operation and the bit line corresponding to the non-rewritten storage means. Thus, even when the timing of starting the rising of the selected word line and the timing of starting the rising of the bit line corresponding to the storage means not rewritten are different from each other, the bit line corresponding to the selected word line and the non-rewriting memory means is selected. In the process of raising, it is possible to suppress the application of a voltage larger than the voltage applied in the rewrite operation to the storage means that is not rewritten. For this reason, the disturb phenomenon of the memory means which is not rewritten in the rewrite operation can be suppressed.

In the memory according to the first aspect, when the rewrite operation is performed on the selection storage means, the length of the period for applying a voltage for rewriting to each of the selected word line and the bit line corresponding to the rewriting memory means is set to the word. By varying the length of the transition period of at least one of the potentials among the lines and the bit lines corresponding to the non-rewritten storage means, for example, the selected word lines and the bit lines corresponding to the rewritten memory means, respectively If the length of the period for applying the voltage for rewriting to the circuit is longer than the length of the transition period, the memory read and rewrite operation is performed by the transition period in which the word line and the bit line corresponding to the non-rewritten storage means are short. It is necessary to rewrite the selection storage means by lengthening the period for rewriting the selection storage means while speeding up the speed. It is possible to secure the length of the period. This makes it possible to reliably rewrite data to the selection storage means while speeding up the operation of the memory.

In the memory according to the first aspect, preferably, the length of the period for applying the voltage is longer than the length of the transition period of the potential of at least one of the word line and the bit line corresponding to the non-rewritten storage means. With such a configuration, a period in which the write lines are rewritten to the selective storage means while the read and rewrite operations of the memory are accelerated by the short transition period of the bit lines corresponding to the word lines and the non-rewritten storage means. By lengthening, the period of the length required for rewriting to the selection memory means can be ensured. This makes it possible to reliably rewrite data to the selection storage means while speeding up the operation of the memory.

In the memory according to the first aspect, preferably, the rewrite operation is composed of a plurality of operations, and performs a read operation performed on a selection storage means connected to the selected word line and a rewrite operation consisting of a plurality of operations. Through this, at least the voltage for supplying the electric field in the first direction and the voltage for supplying the electric field in the first direction and the reverse of the first direction are applied to the non-selection storage means, which is at least a storage means other than the selection memory means. With this arrangement, the voltage for supplying the electric field in the first direction and the voltage for supplying the electric field in the first direction to at least all the storage means connected to the word line except the selected word line through the read operation and the rewrite operation. Since each of the same number of times is applied, polarization deterioration in all unselected storage means connected to at least word lines other than the selected word line can be suppressed through the read operation and the rewrite operation. Thereby, the disturb phenomenon in the storage means can be suppressed through the read operation and the rewrite operation.

In the memory according to the first aspect, preferably, at least one of the selected word line and the bit line corresponding to the non-rewritable storage means gradually rises to the voltage applied to the non-rewritten storage means. In such a configuration, for example, either the selected word line or the bit line corresponding to the storage means for which the rewrite operation is not performed while suppressing the disturbance by gradually increasing the disturbance by the voltage that can be suppressed is performed. , You can rise before the other side. Incidentally, to raise gradually means to include not only the case of raising gradually but also the case of raising continuously.

In this case, preferably, at least one of the selected word line and the bit line corresponding to the non-rewritten storage means rises in steps of 1/3 or less of the potential difference applied to the rewritten memory means. With this arrangement, the potential difference between the selected word line and the bit line corresponding to the non-rewritable memory means when the rewrite operation is performed can be suppressed from being greater than 1/3 of the potential difference applied to the memory means to be rewritten. The occurrence of the disturb phenomenon due to the application of a potential difference larger than 1/3 of the potential difference applied to the rewritten memory means can be suppressed from occurring. Incidentally, in the present invention, 1/3 of the potential difference applied to the rewriting means means substantially one third of the potential difference applied to the rewriting means in the rewriting operation. That is, it also includes a case where the potential difference is slightly larger than 1/3 of the potential difference applied to the memory means that is instantaneously rewritten by noise or the like.

In the memory according to the first aspect, preferably, the bit line corresponding to the non-rewritable storage means is a voltage applied to the non-rewritable storage means before the selected word line is raised, and has a potential difference from the word line. Rising while keeping below a predetermined potential difference. In such a configuration, when the selected word line is raised, the potential difference between the selected word line and the bit line corresponding to the non-rewritten storage means corresponds to the selected word line and the non-rewritten storage means when the rewrite operation is performed. It can be suppressed that it becomes larger than the potential difference with a bit line. For this reason, it is possible to reliably suppress that a potential difference larger than the potential difference applied when the rewrite operation is performed to the storage means that is not rewritten.

In this case, preferably, the bit line corresponding to the non-rewritten storage means rises by 1/3 of the potential difference applied to the memory means to be rewritten as the first step, and then as the second step. , By 1/3 of the potential difference applied to the rewriting memory means. With this arrangement, the bit line corresponding to the non-rewritable storage means can be raised stepwise by 1/3 of the potential difference applied to the rewritable storage means capable of suppressing the disturbance. The storage means for which the write operation is not performed can be raised before the selected word line.

Further, in this case, preferably, even when the bit line corresponding to the non-rewritable storage means rises by 1/3 of the potential difference applied to the memory means to be rewritten as the first step, the selected word line also includes: A voltage of 1/3 of the potential difference applied to the rewriting means is applied. In such a configuration, in the first step, the potential difference between the selected word line and the bit line corresponding to the non-rewritable memory means becomes 0V, so that the potential difference applied to the non-rewritten memory means can be 0V. Thereby, in the first step, the disturb phenomenon of the memory means which is not rewritten can be suppressed.

In the memory according to the first aspect, preferably, the storage means includes a ferroelectric film disposed between the word line and the bit line at a position where the word line and the bit line intersect. In this configuration, the disturb phenomenon can be suppressed in the simple matrix ferroelectric memory.

A memory according to the second aspect of the present invention includes a bit line, a word line arranged to intersect the bit line, and storage means connected between the bit line and the word line, and reads out to the selection storage means connected to the selected word line. The bit corresponding to the selected word line and the non-rewritten storage means when the operation is performed and then the rewrite operation is performed on some selection storage means or the rewrite operation is not performed on all the selection storage means. Each of the lines is raised while maintaining the potential difference with each other below a predetermined value, and at least one of the selected word line and the bit line corresponding to the non-rewritten storage means is applied to the rewritten memory means. Increment up or down by 1/3 or less. Incidentally, in the present invention, 1/3 of the potential difference applied to the rewriting means means substantially one third of the potential difference applied to the rewriting means in the rewriting operation. That is, it also includes a case where the potential difference is slightly larger than 1/3 of the potential difference applied to the memory means which is instantaneously rewritten by noise or the like.

In the memory according to the second aspect, as described above, when the read operation is performed on the selection storage means connected to the selected word line, and then the rewrite operation is performed on some selection storage means, the rewrite operation is performed. Is adjusted, the voltage in the first direction and the voltage having the electric field inverse to the first direction are the same for the non-selected storage means connected to at least word lines other than the selected word line through the read operation and the rewrite operation. Can be applied as many times. Thereby, the disturb phenomenon at the time of the read operation of the non-selection storage means connected to word lines other than the selected word line can be suppressed. Further, the potential difference of the predetermined value is selected during the rewrite operation by raising each of the selected word lines and the bit lines corresponding to the non-rewritable storage means while keeping the potential difference between each other below a predetermined value. If the word line is kept below the potential difference between the bit line corresponding to the non-rewritten memory means, the selected word line and the non-rewritten memory means are raised in the process of raising the selected word line and the bit line corresponding to the non-rewritten memory means. It is possible to suppress that the potential difference between the corresponding bit line is larger than the potential difference between the selected word line during the rewrite operation and the bit line corresponding to the non-rewritten storage means. As a result, even when the timing of starting the rising of the selected word line and the timing of starting the rising of the bit line corresponding to the storage means not rewritten are different from each other, the bit line corresponding to the selected word line and the non-rewriting memory means is selected. In the process of raising, it is possible to suppress the application of a voltage larger than the voltage applied in the rewrite operation to the storage means that is not rewritten. For this reason, the disturb phenomenon of the memory means which is not rewritten in the rewrite operation can be suppressed. Further, the rewrite operation is performed by raising at least one of the selected word line and the bit line corresponding to the non-rewritable storage means stepwise by 1/3 or less of the potential difference applied to the rewritten memory means. It is possible to suppress that the potential difference between the selected word line and the bit line corresponding to the non-rewritten memory means is greater than 1/3 of the potential difference applied to the memory means to be rewritten. Thereby, the occurrence of the distub phenomenon can be suppressed due to the application of a potential difference larger than 1/3 of the potential difference applied to the memory means to be rewritten to the memory means that is not rewritten.

In the memory according to the second aspect, preferably, the bit line corresponding to the non-rewritable storage means has a potential difference from the word line to a voltage applied to the non-rewritten storage means before the selected word line rises. Rising while keeping below a predetermined potential difference. With this arrangement, when the selected word line is raised, the potential difference between the selected word line and the bit line corresponding to the non-rewritable storage means corresponds to the selected word line and non-rewritten storage means when the rewrite operation is performed. It can be suppressed that it becomes larger than the potential difference with a bit line. For this reason, it is possible to reliably suppress that a potential difference larger than the potential difference applied when the rewrite operation is performed to the storage means that is not rewritten.

In this case, preferably, the bit line corresponding to the non-rewritten storage means rises by 1/3 of the potential difference applied to the memory means to be rewritten as the first step, and then as the second step. , By 1/3 of the potential difference applied to the rewriting memory means. With this arrangement, the bit line corresponding to the non-rewritable storage means can be raised stepwise by 1/3 of the potential difference applied to the rewritable storage means capable of suppressing the disturbance. The storage means for which the write operation is not performed can be raised before the selected word line.

Further, in this case, preferably, even when the bit line corresponding to the non-rewritable storage means rises by 1/3 of the potential difference applied to the memory means to be rewritten as the first step, the selected word line also includes: A voltage of 1/3 of the potential difference applied to the rewriting means is applied. In such a configuration, in the first step, the potential difference between the selected word line and the bit line corresponding to the non-rewritable memory means becomes 0V, so that the potential difference applied to the non-rewritten memory means can be 0V. Thereby, in the first step, the disturb phenomenon of the memory means which is not rewritten can be suppressed.

In the memory according to the second aspect, preferably, the storage means includes a ferroelectric film disposed between the word line and the bit line at a position where the word line and the bit line intersect. In this configuration, the disturb phenomenon can be suppressed in the simple matrix ferroelectric memory.

A memory according to the third aspect of the present invention provides a read operation for a bit line, a word line arranged to intersect the bit line, a storage means connected between the bit line and the word line, and a selection storage means connected to the selected word line. Each bit line corresponding to the selected word line and the non-rewritable storage means when the rewriting operation is performed on some selection storage means or the rewriting operation is not performed on all selection storage means. While increasing the potential difference between each other below a predetermined value, the length of the period for applying the voltage for rewriting to each of the selected word line and the bit line corresponding to the rewritten memory means is determined. A control circuit is provided for differenting the length of the transition period of at least one of the potentials among the bit lines corresponding to the non-write memory means. In addition, the voltage for rewriting is preferably a voltage pulse. The transition period means an interval at which the potential of at least one of the word line and the bit line corresponding to the non-rewritten memory means is changed at the time of rising.

In the memory according to the third aspect, as described above, when the control circuit performs a read operation on the selection storage means connected to the selected word line, and then performs a rewrite operation on some selection storage means. When the rewrite operation is adjusted, the voltage in the first direction and the electric field in the first direction and inverse to the non-selected storage means connected to at least word lines other than the selected word line through the read operation and the rewrite operation. Each voltage can be applied the same number of times. Thereby, the disturb phenomenon at the time of the read operation of the unselected storage means connected to word lines other than the selected word line can be suppressed. In addition, the potential difference of the predetermined value is increased during the rewrite operation by raising each of the selected word lines and the bit lines corresponding to the non-rewritable storage means while keeping the potential difference between each other below a predetermined value. If the word line is kept below the potential difference between the bit line corresponding to the non-rewritten memory means, the selected word line and the non-rewritten memory means are raised in the process of raising the selected word line and the bit line corresponding to the non-rewritten memory means. It is possible to suppress that the potential difference between the corresponding bit line is larger than the potential difference between the selected word line during the rewrite operation and the bit line corresponding to the non-rewritten storage means. As a result, even when the timing of starting the rising of the selected word line and the timing of starting the rising of the bit line corresponding to the storage means not rewritten are different from each other, the bit line corresponding to the selected word line and the non-rewriting memory means is selected. In the process of raising, it is possible to suppress the application of a voltage larger than the voltage applied in the rewrite operation to the storage means that is not rewritten. For this reason, the disturb phenomenon of the memory means which is not rewritten in the rewrite operation can be suppressed.

In the memory according to the third aspect, the length of the period in which a voltage for rewriting is applied to each of the selected word line and the bit line corresponding to the rewriting memory means when the rewriting operation is performed to the selection storage means is a word. By varying the length of the transition period of at least one of the potentials among the lines and the bit lines corresponding to the non-rewritten storage means, for example, to each of the selected word line and the bit lines corresponding to the rewritten memory means. If the length of the period for applying the voltage for rewriting is longer than the length of the transition period, the read and rewrite operations of the memory are performed by the short transition period of the word lines and the bit lines corresponding to the non-rewritten storage means. It is necessary for rewriting to the selection storage means by lengthening the period for rewriting the selection storage means while increasing the speed. It is possible to secure the length of the period. This makes it possible to reliably rewrite data to the selection storage means while speeding up the operation of the memory.

In the memory according to the third aspect, preferably, the control circuit is, in response to the clock signal, the start point and the end point of the transition period of at least one of the potentials of the word line and the bit line corresponding to the non-rewritten storage means. Clock control for generating a first signal for setting a second signal and a second signal for setting a start point and an end point of a period in which a voltage for rewriting is applied to each of the selected word line and the bit line corresponding to the rewritten memory means. It includes a circuit portion. In this configuration, the clock control circuit unit is used to provide a voltage for rewriting so that the length of the period for applying the voltage for rewriting is longer than the length of the transition period set by the first signal. When the second signal for setting the start point and the end point is generated in response to the clock signal, the voltage for the transition period and the rewrite is increased when the pulse width of the clock signal is reduced in order to speed up the read and rewrite operation of the memory. Even when the length of the period to be applied is shortened, it is possible to easily secure a period of length necessary for rewriting to the selection storage means. This makes it possible to reliably rewrite data to the selection storage means while speeding up the operation of the memory.

In the memory according to the third aspect, preferably, the control circuit comprises: a first circuit for setting the start point and the end point of the transition period of the potential of at least one of the word line and the bit line corresponding to the non-rewritten storage means; And a delay circuit section for generating a second signal for setting a start point and an end point of a period in which a voltage for rewriting is applied to each of the signal and the bit line corresponding to the selected word line and the rewriting memory means. With this configuration, the time point of the period in which the voltage for rewriting is applied so that the length of the period for applying the voltage for rewriting becomes longer than the length of the transition period set by the first signal using the delay circuit section. And generating the second signal for setting the end point, the selection storage means by easily lengthening the period for rewriting the selection storage means while speeding up the read and rewrite operation of the memory by a short transition period. The period of length necessary for rewriting can be secured. This makes it possible to reliably rewrite data to the selection storage means while speeding up the operation of the memory.

In the memory according to the third aspect, preferably, the length of the period for applying the voltage is longer than the length of the transition period of the potential of at least one of the word line and the bit line corresponding to the non-rewritten storage means. With such a configuration, a period for rewriting the selected storage means can be easily performed while the read and rewrite operations of the memory are accelerated by the short transition period between the word lines and the bit lines corresponding to the non-rewritten storage means. By lengthening, the period of the length required for rewriting to the selection memory means can be ensured. This makes it possible to reliably rewrite data to the selection storage means while speeding up the operation of the memory.

In the memory according to the third aspect, preferably, the rewriting operation is composed of a plurality of operations, and performs a read operation performed on a selection storage means connected to the selected word line and a rewrite operation consisting of a plurality of operations. Through this, at least the voltage for supplying the electric field in the first direction and the voltage for supplying the electric field in the first direction and the reverse of the first direction are applied to the non-selection storage means, which is at least a storage means other than the selection memory means. With this arrangement, the voltage for supplying the electric field in the first direction and the voltage for supplying the electric field in the first direction to at least all the storage means connected to the word line except the selected word line through the read operation and the rewrite operation. Since each of the same number of times is applied, polarization deterioration in all unselected storage means connected to at least word lines other than the selected word line can be suppressed through the read operation and the rewrite operation. Thereby, the disturb phenomenon in the storage means can be suppressed through the read operation and the rewrite operation.

In the memory according to the third aspect, preferably, at least one of the selected word line and the bit line corresponding to the non-rewritten storage means gradually rises to the voltage applied to the non-rewritten storage means. In such a configuration, for example, either the selected word line or the bit line corresponding to the storage means for which the rewrite operation is not performed while suppressing the disturbance by gradually increasing the disturbance by a voltage that can be suppressed is performed. Can be raised before the other side. In addition, to raise gradually means not only to raise not only a stage but also to raise continuously.

In this case, preferably, at least one of the selected word line and the bit line corresponding to the non-rewritten storage means rises stepwise by 1/3 or less of the potential difference applied to the rewritten memory means. With this arrangement, the potential difference between the selected word line and the bit line corresponding to the non-rewritable memory means when the rewrite operation is performed can be suppressed from being greater than 1/3 of the potential difference applied to the memory means to be rewritten. The occurrence of the disturb phenomenon due to the application of a potential difference larger than 1/3 of the potential difference applied to the rewritten memory means can be suppressed from occurring. Incidentally, in the present invention, 1/3 of the potential difference applied to the rewriting means means substantially one third of the potential difference applied to the rewriting means in the rewriting operation. That is, it also includes a case where the potential difference is slightly larger than 1/3 of the potential difference applied to the memory means which is instantaneously rewritten by noise or the like.

In the memory according to the third aspect, preferably, the bit line corresponding to the non-rewritable storage means is a voltage applied to the non-rewritable storage means before the selected word line rises so as to have a potential difference with the word line. Rising while keeping below a predetermined potential difference. With this arrangement, when the selected word line is raised, the potential difference between the selected word line and the bit line corresponding to the non-rewritable storage means corresponds to the selected word line and non-rewritten storage means when the rewrite operation is performed. It can be suppressed that it becomes larger than the potential difference with a bit line. For this reason, it is possible to reliably suppress that a potential difference larger than the potential difference applied when the rewrite operation is performed to the storage means that is not rewritten.

In this case, preferably, the bit line corresponding to the non-rewritten storage means rises by 1/3 of the potential difference applied to the memory means to be rewritten as the first step, and then as the second step. , By 1/3 of the potential difference applied to the rewriting memory means. With this arrangement, the bit line corresponding to the non-rewritable storage means can be raised stepwise by 1/3 of the potential difference applied to the rewritable storage means capable of suppressing the disturbance. The storage means for which the write operation is not performed can be raised before the selected word line.

Further, in this case, preferably, even when the bit line corresponding to the non-rewritable storage means rises by 1/3 of the potential difference applied to the memory means to be rewritten as the first step, the selected word line also includes: A voltage of 1/3 of the potential difference applied to the rewriting means is applied. In such a configuration, in the first step, the potential difference between the selected word line and the bit line corresponding to the non-rewritable memory means becomes 0V, so that the potential difference applied to the non-rewritten memory means can be 0V. Thereby, in the first step, the disturb phenomenon of the memory means which is not rewritten can be suppressed.

In the memory according to the third aspect, preferably, the storage means comprises a ferroelectric film disposed between the word line and the bit line at a position where the word line and the bit line intersect. In this configuration, the disturb phenomenon can be suppressed in the simple matrix ferroelectric memory.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described based on drawing.

(First embodiment)

First, with reference to FIG. 1, the whole structure of the ferroelectric memory of the simple matrix system of 1st Embodiment is demonstrated. The ferroelectric memory of the first embodiment includes a memory cell array 1, a row decoder 2, a column decoder 3, a row address buffer 4, a column address buffer 5, and a write amplifier 6 ), Input buffer 7, read amplifier 8, output buffer 9, voltage generation circuit 10, state machine circuit 11, word line source driver 12, bits The line source driver 13, the sense amplifier 14, and the clock generation circuit 15 are provided.

In the memory cell array 1, a plurality of word lines WL and a plurality of bit lines BL are arranged to cross each other, and a simple matrix type memory cell composed of only a ferroelectric capacitor (not shown) is disposed at each crossing position. have. The ferroelectric capacitor constituting this memory cell is an example of the "memory means" of the present invention. The ferroelectric capacitor constituting the memory cell is composed of a word line WL, a bit line BL, and a ferroelectric film (not shown) disposed between the word lines WL and the bit line BL. The row decoder 2 is connected to the word line WL of the memory cell array 1, and the column decoder 3 is connected to the bit line BL through the sense amplifier 14.

The word line source driver 12 is connected to the row decoder 2, and the voltage generation circuit 10 is connected to the word line source driver 12. The state machine circuit 11 is connected to the word line source driver 12. The bit line source driver 13 is connected to the sense amplifier 14, and the voltage generation circuit 10 is connected to the bit line source driver 13. The voltage generation circuit 10 is configured to supply 1 / 3VCC, 2 / 3VCC, and VCC to the word line source driver 12 and the bit line source driver. In addition, the write amplifier 6 and the read amplifier 8 are connected to the sense amplifier 14. The read amplifier 8 is connected to the output buffer 9, and the write amplifier 6 is connected to the input buffer 7. The clock generation circuit 15 is also connected to the row address buffer 4, the column address buffer 5, the write amplifier 6, and the read amplifier 8.

2 to 4, the read-write operation in the ferroelectric memory of the simple matrix method according to the first embodiment will be described. In the description of the first embodiment, as shown in Fig. 2, it is assumed that the selection WL is the word line WL3, and the non-selection WL (non-selection word line) is the word lines WL0-2 and the word lines WL4-7. Further, among the memory cells connected to the selection WL (word line WL3), data "1" is stored in the memory cells connected to the bit line BL3 and the bit line BL5, and the other bit lines BL0 to 2, 4, and the like. Assume that data "0" is stored in the memory cells connected to 6, 7). In addition, below, the bit lines BL3 and BL5 connected to the memory cell which stored the data "1" are described as "1" read bit line BL ("1" read BL), and the memory which stored data "0". The bit lines BL0 to 2, 4, 6, and 7 connected to the cell are referred to as "0" lead bit lines BL ("0" lead BL). As shown in Fig. 3, among the memory cells connected to the selection WL (WL3), the memory cell group storing the data "0" is selected from the first cell region and the memory cells connected to the selection WL. The memory cell group storing "1" is assumed to be the second cell area. Further, among the memory cells connected to the non-selected WL, the memory cell group connected to the bit line BL3 and the bit line BL5 ("1" read bit BL) is selected from the third cell region and the memory cell connected to the unselected WL. A memory cell group connected to bit lines ("0" lead BL) other than BL3 and bit line BL5 is referred to as a fourth cell region. The memory cells included in the first and second cell regions connected to the selection WL are examples of the "selective storage means" of the present invention, and the memory cells included in the third and fourth cell regions are those of the present invention. This is an example of "non-selective storage means".

As shown in Fig. 4, the read-write operation is performed in the period of T0 to T62. The period of T0 is a period in which all word lines WL and bit lines BL are inactive (standby state). The period of T1 is a period for performing a read operation. The period of T3 and T5 is a period for performing the rewrite operation. In these periods of T3 and T5, electric fields in opposite directions are applied to the memory cells in each period. T21, T22, T41, T42, T61, and T62 are periods for sequentially changing the voltage of the word line WL or the bit line BL. In addition, the period of T1, T21, and T22 is an example of the "transition period" of this invention. Next, with reference to FIG. 3 and FIG. 4, each operation | movement in the period of T0-T62 is demonstrated.

First, in the standby state of T0, all word lines WL (WL0 to WL7) and bit lines BL (BL0 to BL7) are each VSS (0V). Then, the signal shifts from the period T0 to the period T1 (period for performing the read operation) by a signal input from the outside. In this period of T1, the voltage of the selection WL (WL3) selected by the address signal or the like input from the outside is raised to VCC. At this time, the unselected WLs WL0 to 2 and WL4 to 7 hold VSS. In addition, during a predetermined period of time T1, all the bit lines BL ("1" lead BL and "0" lead BL: BL0 to BL7) are in a high impedance state having an indeterminate voltage between VCC and VSS (open state). ). Thereby, the voltage corresponding to "0" data or "1" data recorded in the memory cells of the first and second cell regions connected to the selection WL (WL3) is output to the bit lines BL0 to BL7, It is input to the sense amplifier 14 (refer FIG. 1) through each bit line BL0-BL7. Then, the voltage input to the sense amplifier 14 and the reference potential generated separately are compared and amplified by the sense amplifier 14, so that the data of the memory cell is either "0" data or "1" data. One determination is made.

In the period in which the bit lines BL0 to BL7 are in the high impedance state during the period of T1, different voltages are applied to the memory cells in the first to fourth cell regions (see FIG. 3), respectively. That is, the voltage of VCC-Vr0 ("0" data read voltage) is applied to the memory cell of the first cell region. In addition, a voltage of VCC-Vr1 ("1" data read voltage) is applied to the memory cell in the second cell region. The voltage of -Vr1 is applied to the memory cells of the third cell region, and the voltage of -Vr0 is applied to the memory cells of the fourth cell region. After the high impedance state has elapsed during the period of T1, all the bit lines BL0 to BL7 are set to VSS. At this time, the voltage of VCC is applied to the memory cells of the first and second cell regions, while the voltage is not applied to the memory cells of the third and fourth cell regions.

Subsequently, the process shifts to the period T21 due to a signal input from the outside, a signal generated in the memory, or the like. The transition from T22 to T62 after the period of T21 is also performed by a signal input from the outside, a signal generated in the memory, or the like, similarly to the transition from the period of T1 to the period of T21. In the transition from this period T1 to T21, in the first embodiment, the voltage between the selection WL (WL3) and the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6 and 7) is the same 1 / 3VCC, respectively, at the same time. Is raised. In addition, the voltages of the unselected WLs WL0 to 2 and WL4 to 7 and the &quot; 1 &quot; read BLs BL3 and BL5 are also raised to 1/3 VCC, respectively. Thus, in the period of T21, the potential difference between the word lines WL and the bit lines BL of all the memory cells in the first to fourth cell regions becomes 0V. In addition, the delay of the voltage transfer causes unselected WLs (WL0 to 2, 4 to 7), "1" leads BL (BL3 and BL5) and "0" leads BL (BL0 to 2, 4, 6 and 7). Note that even when the voltage applied to each of the memory cells is slightly delayed to become 1/3 VCC, when all transitions from the period T1 to the period T21, all word lines (selection WL (WL3) and non-selection WL (WL0 to 2, 4 to 7)) and the potential difference between the bit lines BL ("1" leads BL (BL3 and BL5) and "0" leads BL (BL0 to 2, 4, 6 and 7)) in the range of 1/3 VCC or less. Since not all voltages above 1/3 VCC are applied to all memory cells.

Subsequently, the process shifts to the period of T22. In the period of T22, the voltages of the selected WL (WL3), the non-selected WLs (WL0 to 2, 4 to 7), and the "1" read BLs BL3 and BL5 are maintained at 1 / 3VCC and "0". The voltages of the leads BL0 to 2, 4, 6 and 7 rise to 2/3 VCC. As described above, in the present embodiment, the voltage of the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6 and 7) is increased in two stages over the period of T1 to T22. During this period of T22, a voltage of -1/3 VCC is applied to the memory cells in the first and fourth cell regions, and the voltage applied to the memory cells in the second and third cell regions is maintained at 0V.

Subsequently, the process shifts to a period of T3 where the first rewrite operation is performed on the memory cell. In the first embodiment, as shown in Fig. 4, the length of the period of T3 is set to twice the length of each period of T1 to T22. In the period of T3, the voltage of the selection WL (WL3) is raised to VCC again. In addition, the voltages of the non-selective WLs (WL0 to 2, 4 to 7) and the "0" read BLs (BL0 to 2, 4, 6, and 7) are maintained at 1 / 3VCC and 2 / 3VCC, respectively, and "1". The voltages of the leads BL3 and BL5 fall to VSS. As a result, the voltage of VCC is applied to the memory cells of the second cell region connected to the "1" leads BL3 and BL5, so that "0" data is rewritten to the memory cells of the second cell region. . The period of T3 is set to have a length twice the length of each period of T1 to T22, so that "0" data can be reliably rewritten to the memory cells of the second cell area. Meanwhile, 1 / 3VCC is applied to the memory cells of the first and third cell regions, and −1 / 3VCC is applied to the memory cells of the fourth cell region.

Next, the process shifts to the period of T41. In the period of T41, the voltage of the selected WL (WL3) is reduced to 1 / 3VCC, while the voltage of the non-selected WL (WL0 to 2, 4 to 7) is maintained at 1 / 3VCC. In addition, the voltage of the "1" leads BL (BL3 and BL5) is increased to 1 / 3VCC, and the voltage of the "0" leads BL (BL0 to 2, 4, 6, and 7) is maintained at 2 / 3VCC. As a result, a voltage of −1/3 VCC is applied to the memory cells of the first cell region, and a voltage of 0 V is applied to the memory cells of the second and third cell regions. In addition, the voltage applied to the memory cell in the fourth cell region is maintained at -1/3 VCC.

Subsequently, the process shifts to the period of T42. In the period of T42, the voltage of the selected WL (WL3) is maintained at 1 / 3VCC, while the voltage of the non-selected WL (WL0 to 2, 4 to 7) is raised to 2 / 3VCC. In addition, while maintaining the voltage of the "1" leads BL (BL3 and BL5) to 1/3 VCC, the voltage of the "0" leads BL (BL0 to 2, 4, 6 and 7) is reduced to 1/3 VCC. As a result, a voltage of 0 V is applied to the memory cell of the first cell region, and a voltage applied to the memory cell of the second cell region is maintained at 0 V. FIG. In addition, a voltage of 1/3 VCC is applied to the memory cells in the third and fourth cell regions. In addition, the voltage applied to the memory cell from each of the &quot; 0 &quot; read BLs BL0 to 2, 4, 6 and 7 and the unselected WLs WL0 to 2 and 4 to 7 is delayed due to the delay of the transfer of the voltage. Even when it becomes slightly delayed to become / 3VCC and 2 / 3VCC, all word lines (selected WL (WL3) and unselected WL (WL0 to 2, 4 to 7)) and bit lines at the time of transition from the period T41 to the period T42. The potential difference between BL ("1" lead BL (BL3 and BL5) and "0" lead BL (BL0 to 2, 4, 6 and 7) is in the range of 1/3 VCC or less, so that 1 / No voltage greater than 3 VCC is applied.

Subsequently, the process shifts to the period of T5 for performing the second rewrite operation on the memory cell. In the first embodiment, as shown in Fig. 4, the length of the period of T5 is set to twice the length of each of the periods of T1 to T22, T41 and T42. In the period of T5, the voltage of the selected WL (WL3) is lowered to VSS, and the voltage of the non-selected WL (WL0 to 2, 4 to 7) is maintained at 2/3 VCC. The voltage of the "1" leads BL (BL3 and BL5) is raised to VCC and the voltage of the "0" leads BL (BL0 to 2, 4, 6, and 7) is maintained at 1/3 VCC. As a result, -1/3 VCC is applied to the memory cell of the first cell region, and -VCC is applied to the memory cell of the second cell region. For this reason, "1" data is rewritten to the memory cell of the second cell area. The period of T5 is set to have a length twice the length of each of the periods T1 to T22, T41, and T42, so that "0" data can be reliably rewritten to the memory cells of the second cell area. . In addition, voltages of -1/3 VCC are applied to the memory cells of the first and third cell regions, respectively, and voltages of 1/3 VCC are applied to the memory cells of the fourth cell region. As a result, 1 / 3VCC supplied with the first rewrite operation (period T3) and -1 / 3VCC, which is the reverse voltage, are applied to the memory cells of the first and third cell regions, and the fourth cell region is provided. In the memory cells of, since -1 / 3VCC applied by the first rewrite operation (period of T3) and 1 / 3VCC, which is the inverse voltage, are applied to the memory cells of the first, third and fourth cell regions. The disturb of is canceled.

Subsequently, the process shifts to the period of T61. In the period of T61, the voltage of the selection WL (WL3) is raised to 1 / 3VCC, and the voltage of the non-selection WL (WL0 to 2, 4 to 7) is maintained at 1 / 3VCC. The voltage of the "1" leads BL (BL3 and BL5) is reduced to 1 / 3VCC, while the voltage of the "0" leads BL (BL0 to 2, 4, 6, and 7) is held at 1 / 3VCC. As a result, a voltage of 0 V is applied to the memory cells in the first and second cell regions. In addition, while the voltage of 1/3 VCC is applied to the memory cell of the third cell region, the voltage applied to the memory cell of the fourth cell region is maintained at 1/3 VCC.

Subsequently, the process shifts to the period of T62. In the period of T62, the voltages of the select WL (WL3), the "1" lead BLs BL3 and BL5, and the "0" lead BLs BL0 to 2, 4, 6 and 7 are maintained at 1 / 3VCC, The voltage of the non-selective WLs (WL0 to 2, 4 to 7) is reduced to 1/3 VCC. As a result, the voltages of all the word lines WL0 to WL7 and the bit lines BL0 to BL7 are 1/3 VCC. For this reason, the voltage applied to all the memory cells in the first to fourth cell regions is 0V.

Finally, the process shifts to the period of the standby state T0. In the period of T0, as described above, the voltages of all the word lines WL0 to 7 and the bit lines BL0 to 7 are reduced to VSS, so that the voltage applied to all the memory cells in the first to fourth cell regions becomes 0V. . After this period of T0, all the memory cells are kept in the standby state of 0V until the next read-write operations T1 to T62 are started.

5 shows a voltage waveform diagram of an internal signal used to supply voltages VSS, 1 / 3VCC, 2 / 3VCC and VCC to the word lines WL and bit lines BL of the memory according to the first embodiment. In FIG. 5, CLK is a clock signal input to the state machine circuit 11 (see FIG. 1) from the clock generation circuit 15 (see FIG. 1), and CSB is an inversion input to the state machine circuit 11 from the outside. Chip select signal. The state machine circuit 11 is activated by inverting the chip selection signal CSB to L level. Further, STT1 to 5 are state signals generated by the state machine circuit 11, respectively, and the state signals STT1 to 5 are the word line source driver 12 and the bit line source driver (from the state machine circuit 11). 13) is supplied. CUP and CUPB are inverted count up signals which are inverted signals of the count up signal and the count up signal generated in the state machine circuit 11, respectively.

Further, XSE3B, XSE1 and XSE0 are word line source control signals used for selecting and supplying any one of VSS, 1 / 3VCC and VCC to select WL (WL3), respectively. STT1 to 5 are supplied to the word line source driver 12 to generate the word lines. In addition, XUE2B, XUE1 and XUE0 are word line source control signals used to select and supply any one of VSS, 1 / 3VCC and 2 / 3VCC to unselected WLs WL0-2, 4-7, respectively. Is generated inside the word line source driver 12 in the same manner as the word line source control signals XSE3B, XSE1 and XSE0.

In addition, YHE3B, YHE1, and YHE0 select one of VSS, 1 / 3VCC, and VCC through the sense amplifier to the bit lines BL (&quot; 1 &quot; leads BL: BL3 and BL5) from which the H level data is read. Bit line source control signal used to supply. The bit line source control signals YHE3B, YHE1 and YHE0 are generated inside the bit line source driver 13 by supplying the state signals STT1 to 5 to the bit line source driver 13 (see Fig. 1). In addition, YLE2B, YLE1, and YLE0 apply any one of VSS, 1 / 3VCC, and 2 / 3VCC to the bit lines BL ("1" lead BL: BL3 and BL5) from which L-level data is read through a sense amplifier. A bit line source control signal used to select and supply. The bit line source control signals YLE2B, YLE1 and YLE0 are generated inside the bit line source driver 13 by supplying the state signals STT1 to 5 to the bit line source driver 13. In the voltage waveform diagram shown in FIG. 5, when the inverting chip select signal CSB is at the L level when the clock signal CLK is raised, the word line WL and the bit line BL are operated from the standby state (period T0) to the operating state (the period T0). Each of the internal signals described above is configured to transition to the periods T1 to T62.

Subsequently, an operation of each internal signal will be described with reference to FIG. 5. First, when the inverting chip select signal CSB is at the L level, the clock signal CLK is at the H level, whereby the state signal STT1 rises to the H level. Then, as the clock signal CLK gradually goes to the H level, the state signals STT2 to 4 sequentially rise to the H level. After the state signal STT4 rises to the H level, the state signal STT5 rises to the H level in accordance with the clock signal CLK of the second H level. That is, the rise of the state signal STT5 is delayed by the HK clock signal CLK2 with respect to the rise of the state signal STT4. As a result, the delay amount of the rise of the state signal STT5 is twice the delay amount of the rise of the state signals STT2 to 4 delayed by one clock signal CLK at the H level relative to the previous state signal. State signals STT2 to STT4 are examples of the "first signal" of the present invention, and state signals STT4 and STT5 are examples of the "second signal" of the present invention.

Then, in accordance with the clock signal CLK of the next H level of the clock signal CLK in which the state signal STT5 rises to the H level, the state signal STT1 falls to the L level, and in accordance with the clock signal CLK of the next H level, STT2 drops to L level. After the state signal STT2 falls to the L level, the state signal STT3 falls to the L level in accordance with the second H level clock signal CLK. That is, the reduction of the state signal STT3 delays two high-level clock signals CLK with respect to the decrease of the state signal STT2. Thereby, the delay amount of the fall of the state signal STT3 becomes twice the delay amount of the descending state by the state signals STT1 and STT2 which delays one clock signal CLK of H level with respect to the previous state signal.

Thereafter, the state signals STT4 and 5 sequentially fall to the L level as the clock signal CLK becomes the H level sequentially. As described above, when the state signals STT1 to 5 become H level or L level in accordance with the clock signal CLK, the combination of the H level or the L level of the state signals STT1 to 5 is 10 or less. Combinations (combinations of the respective periods A to J in FIG. 5). Each of the periods T0 to T62 described above is specified by the 10 combinations A to J of the state signals STT1 to 5. The word line source control signals XSE3B, XSE1, XSE0, XUE2B, XUE1 and XUE0 and the bit line source control signals YHE3B, YHE1, YHE0, YLE2B, YLE1 and YLE0 according to the specified period are respectively the word line source driver ( 12) and the bit line source driver 13.

In the first embodiment, as described above, in the periods T21 and T22 before the period T3 in which the first rewrite operation is performed, the voltage of the "0" read BL (BL0 to 2, 4, 6 and 7) is 1 /. In the period T3 during which the first rewrite operation is performed by increasing the voltages in 3 VCC steps, when the selection WL (WL3) is raised to VCC, the voltage of the &quot; 0 &quot; read BL is already 2 during the rewrite operation. Since / 3VCC can be set, the potential difference between the selection WL and the "0" read BL is selected by the selection WL and "0" when the rewrite operation is performed even when a voltage delay is slightly delayed through the "0" read BL. It can be suppressed that it becomes larger than the potential difference (1 / 3VCC) with the lead BL. For this reason, it is possible to suppress the application of a voltage larger than 1/3 VCC applied when the rewrite operation is performed to the memory cells in the first cell region. As a result, it is possible to suppress the disturb phenomenon of the memory cell in the first cell region caused by the application of a voltage larger than 1/3 VCC applied when the rewrite operation is performed.

Further, in the first embodiment, at the first rewrite operation (period T3), the voltages of 1/3 VCC and −1 are respectively applied to the memory cells of the first and third cell regions and the memory cells of the fourth cell region. A voltage of 1/3 VCC is applied and -1/3 VCC respectively to the memory cells of the first and third cell regions and the memory cells of the fourth cell region during the second rewrite operation (period T5). The voltage (± 1/3 VCC) in reverse directions is applied to the memory cells in the first, third and fourth cell regions one by one by applying a voltage of 1/3 VCC and a read operation and a rewrite operation. Through this, polarization deterioration in the memory cells of the first, third and fourth cell regions can be suppressed. Thereby, the disturb phenomenon in the memory cells of the first, third and fourth cell regions can be suppressed through the read operation and the rewrite operation.

In the first embodiment, the length of the periods T3 and T5 for the rewrite operation is set to be twice the length of each of the periods T1 to T22 to speed up the memory read and rewrite operations. In the case where the pulse width of the clock signal CLK for generating each period of T1 to T62 is made small, even when the length of each period of T1 to T62 is shortened, the memory cell of the second cell region (see FIG. 3) is used. A period of length necessary for rewriting can be secured. This makes it possible to reliably rewrite data to the memory cells of the second cell region while speeding up the operation of the memory.

As another example of the method of applying the voltage to the word line WL and the bit line BL, as shown in FIG. 6, the selection WL (WL3) and the &quot; 0 &quot; lead BL (in the period T2 after the period T1 in which the read operation is performed). When the voltages of BL0 to 2, 4, 6, and 7 (see Fig. 3) are set to VSS, respectively, and the transition from the period T2 to the period T3 for performing the rewrite operation, the selections WL (WL3) and " It is also conceivable to set the voltages of the 0 "leads BL (BL0 to 2, 4, 6 and 7) to VCC and 2 / 3VCC, respectively. In this case, when the voltages of the selection WL (WL3) and the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6, and 7) rise at exactly the same timing as in the a state shown in Fig. 7, the selection WL and The potential difference V (WL) -V (BL) with the "0" lead BL does not become larger than 1 / 3VCC. Therefore, in this a state, a voltage greater than 1/3 VCC is applied to the memory cells in the first cell region connected to the selection WL (WL3) and the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6, and 7). It doesn't work.

However, since the "0" read BLs BL0 to 2, 4, 6, and 7 actually have a predetermined length, the "0" read BL from the bit line source driver 13 through the sense amplifier 14 is lost. Some time is required for the voltage supplied to the ends of (BL0 to 2, 4, 6 and 7) to be transferred to the center portion. As a result, in the memory cell connected to the center portion of the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6 and 7), the timing at which the voltage is applied is slightly delayed compared to the memory cell connected to the end portion. In this case, as in the b state shown in FIG. 7, the potential difference V (WL) -V (BL) between the selection WL (WL3) and the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6, and 7) is 1; Since the voltage (maximum VCC) is larger than / 3 VCC, a voltage larger than 1/3 VCC is applied to the memory cell connected to the center portion of the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6 and 7). As described above, in another example shown in FIG. 6, a voltage larger than 1/3 VCC is applied every time the rewrite operation is performed, thereby connecting to the center portion of the "0" leads BL (BL0 to 2, 4, 6 and 7). In the memory cell, as shown in Fig. 30, data destruction due to the disturb phenomenon occurs.

On the other hand, in the first embodiment in which data read-write operation is performed along the voltage waveform diagram as shown in Figs. 4 and 5, as described above, the period T3 (Fig. 5) in which the rewrite operation is performed. In the period T22 before, the voltage of the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6, and 7) rises to 2 / 3VCC, so that unlike the voltage application method according to another example shown in FIG. Even when propagation of the signal is delayed slightly, the potential difference between the selection WL (WL3) and the &quot; 0 &quot; leads BL (BL0 to 2, 4, 6, and 7) does not become larger than 1/3 VCC. As a result, in the first embodiment, the disturb phenomenon of the memory cells in the first cell region due to the application of a voltage larger than 1 / 3VCC can be suppressed.

Subsequently, various internal signals described above (state signals STT1 to 5, count up signal CUP, inverted count up signal CUPB, word line source control signals XSE3B to 0, XUE2B to 0, and bit line source control signals YHE3B to 0, The configuration of a circuit for generating YLE2B to 0) will be described. 8 is a circuit diagram showing the configuration of the state machine circuit 11 that generates the state signals STT1 to 5, the count up signal CUP, and the inverted count up signal CUPB. In addition, this state machine circuit 11 is an example of the "control circuit" and "clock control circuit part" of this invention. As shown in FIG. 8, the state machine circuit 11 includes six delay flip-flop circuits 16a to 16f (hereinafter referred to as DFF circuits 16a to 16f) and three selector circuits 17 to 16. As shown in FIG. 19, eight NAND circuits 20 to 27, two OR circuits 28 and 29, one AND circuit 30, and one NOR circuit 31 are provided.

The clock signal CLK and the inverted reset signal RSTB are supplied to the DFF circuits 16a to 16f, respectively. The inversion reset signal RSTB is input from an input terminal / R of the DFF circuits 16a to 16f. The output signal of the selector circuit 17 is input to the input terminal D of the DFF circuit 16a. The state signal STT1 is output from the output terminal QT of the DFF circuit 16a. This state signal STT1 is input to the "0" side of the selector circuit 17, the NAND circuit 18, and the cut-off DFF circuit 16b. The inverted state signal STT1B, which is an inverted signal of the state signal STT1, is output from the output terminal QB of the DFF circuit 16a. This inverted state signal STT1B is input to the "1" side of the selector circuit 17. The state signal STT2 is output from the output terminal QT of the DFF circuit 16b, and the inverted state signal STT2B, which is an inverted signal of the state signal STT2, is output from the output terminal QB of the DFF circuit 16b. The state signal STT2 is input to the NAND circuit 22, while the inverted state signal STT2B is input to the NAND circuit 23. The output signal of the NAND circuit 22 is input to the NAND circuit 24. The output signal of the NAND circuit 23 is input to the OR circuit 28 and the NAND circuit 30, and the output of the OR circuit 28 is input to the NAND circuit 24. The output signal of the NAND circuit 24 is input to the selector circuit 18. The output signal of the selector circuit 18 is input to the input terminal D of the DFF circuit 16c.

The state signal STT3 is output from the output terminal QT of the DFF circuit 16c, and the inverted state signal STT3B, which is an inverted signal of the state signal STT3, is output from the output terminal QB of the DFF circuit 16c. The state signal STT3 is input to the NAND circuit 23, the "0" side of the selector circuit 18 and the input terminal D of the DFF circuit 16d, while the inverted state signal STT3B is the NAND circuit 22 and the selector. It is input to the "1" side of the circuit 18. The state signal STT4 is output from the output terminal QT of the DFF circuit 16d, and the inverted state signal STT4B, which is an inverted signal of the state signal STT4, is output from the output terminal QB of the DFF circuit 16d. The state signal STT4 is input to the NAND circuit 25, while the inverted state signal STT4B is input to the NAND circuit 26. The output signal of the NAND circuit 25 is input to the OR circuit 29 and the NAND circuit 30, and the output of the OR circuit 29 is input to the NAND circuit 27. The output signal of the NAND circuit 26 is input to the NAND circuit 27. The output signal of the NAND circuit 27 is input to the selector circuit 19. The output signal of the selector circuit 19 is input to the input terminal D of the DFF circuit 16e.

State signal STT5 is output from output terminal QT of DFF circuit 16e, and inverted state signal STT5B, which is an inverted signal of state signal STT5, is output from output terminal QB of DFF circuit 16e. The state signal STT5 is input to the NAND circuit 26, the &quot; 0 &quot; side of the selector circuit 19, and the NAND circuit 20, while the inverted state signal STT5B is the NAND circuit 25 and the selector circuit 19. It is input to the "1" side of. The output signal of the AND circuit 30 is input to the NOR circuit 31. The output signal of the NOR circuit 31 is input to the input terminal D of the DFF circuit 16f. The count up signal CUP is output from the output terminal QT of the DFF circuit 16f, and the inverted count up signal CUPB, which is an inverted signal of the count up signal CUP, is output from the output terminal QB of the DFF circuit 16f. . The count up signal CUP is input to the NOR circuit 31, while the inverted count up signal CUPB is input to the OR circuit 28 and the OR circuit 29. The state signals STT1 to STT5 are output to the outside from the output terminals QT of the respective DFF circuits 16a to 16e, and the inverted state signals STT1B to STT5B are the output terminals QB of the respective DFF circuits 16a to 16e, respectively. Is output from the outside.

5 and 8, the operation of the state machine circuit according to the first embodiment will be described.

In the state machine circuit 11 according to the first embodiment, the state signal output from the DFF circuits 16a to 16f by inputting the L level inversion reset signal RSTB to the DFF circuits 16a to 16f in the standby state. STT1 to STT5 and the count up signal CUP are all at L level. At this time, since the L-level state signals STT1 and STT5 are input to the NAND circuit 20, the H-level signal is input from the NAND circuit 20 to the NAND circuit 21. In this state, the H level inverting chip select signal CSB is input to the NAND circuit 21. As a result, an L level signal is input from the NAND circuit 21 to the selector circuit 17. For this reason, since the input of the selector circuit 17 switches to the "0" side, the L-state state signal STT1 output from the DFF circuit 16a is supplied to the DFF circuit 16a via the selector circuit 17. As a result, the state signal STT1 output from the DFF circuit 16a is maintained at the L level, so the state signal STT2 output from the DFF circuit 16b to which the state signal STT1 is input is maintained at the L level. In this standby state, the state signals STT3 to STT5 and the count up signal CUP output from each of the DFF circuits 16c to 16f are also maintained at the L level. Further, the inverted state signals STT1B to STT5B and the inverted count up signal CUPB output from each of the DFF circuits 16a to 16f are maintained at the H level.

Subsequently, while the H level signal is input from the NAND circuit 20 to the NAND circuit 21, the L level inverting chip select signal CSB is input to the NAND circuit 21. As a result, the H level signal is input from the NAND circuit 21 to the selector circuit 17. For this reason, since the input of the selector circuit 17 switches to the "1" side, the inverted state signal STT1B of H level output from the DFF circuit 16a is supplied to the DFF circuit 16a via the selector circuit 17. Thereafter, the H-level clock signal CLK is inputted to the DFF circuit 16a, so that the H-level state signal STT1 is output from the DFF circuit 16a. This high level state signal STT1 is input to the DFF circuit 16b. Subsequently, after the clock signal CLK input to the DFF circuit 16b falls to the L level and rises to the H level, the state signal STT2 of the H level is output from the DFF circuit 16b.

The state signal STT2 of H level is input to the NAND circuit 22. In addition, since the inverted state signal STT3B of high level is input from the DFF circuit 16c to the NAND circuit 22, the low level signal is input from the NAND circuit 22 to the NAND circuit 24. On the other hand, the inverted state signal STT2B of L level is input from the DFF circuit 16b to the NAND circuit 23. In addition, since the L-level state signal STT3 is input to the NAND circuit 23 from the DFF circuit 16c, the H-level signal is input to the OR circuit 28 from the NAND circuit 23. At this time, since the H level inversion count-up signal CUPB is input from the DFF circuit 16f to the OR circuit 28, the H level signal is input from the OR circuit 28 to the NAND circuit 24. For this reason, the H level signal is input from the NAND circuit 24 to the selector circuit 18. As a result, since the input of the selector circuit 18 is switched to the "1" side, the inverted state signal STT3B of the H level output from the DFF circuit 16c is supplied to the DFF circuit 16c via the selector circuit 18. . Subsequently, after the clock signal CLK input to the DFF circuit 16c falls to the L level and rises to the H level, the state signal STT3 of the H level is output from the DFF circuit 16c. Then, the state signal STT3 of H level is input to the DFF circuit 16d. Subsequently, after the clock signal CLK input to the DFF circuit 16d falls to the L level and rises to the H level, the state signal STT4 of the H level is output from the DFF circuit 16d.

The state signal STT4 of H level is input to the NAND circuit 25. In addition, since the inverted state signal STT5B of high level is input from the DFF circuit 16e to the NAND circuit 25, the low level signal is input from the NAND circuit 25 to the OR circuit 29. At this time, since the high level inversion count-up signal CUPB is input from the DFF circuit 16f to the OR circuit 29, the high level signal is input from the OR circuit 29 to the NAND circuit 27. On the other hand, the inverted state signal STT4B of L level is input from the DFF circuit 16d to the NAND circuit 26. In addition, since the L-level state signal STT5 is input to the NAND circuit 26 from the DFF circuit 16e, the H-level signal is input to the NAND circuit 27 from the NAND circuit 26. For this reason, the L level signal is input from the NAND circuit 27 to the selector circuit 19. As a result, since the input of the selector circuit 19 is held to the "0" side, the L-level state signal STT5 output from the DFF circuit 16e is supplied to the DFF circuit 16e via the selector circuit 19. Thereby, even when the clock signal CLK input to the DFF circuit 16e falls to L level and then rises to H level, the state signal STT5 output from the DFF circuit 16e is maintained at L level. do.

The L level signal output from the NAND circuit 25 is also input to the AND circuit 30. At this time, since the H level output signal of the NAND circuit 23 is also input to the AND circuit 30, an L level signal is input from the AND circuit 30 to the NOR circuit 31. Since the L-level count-up signal CUP is input to the NOR circuit 31 from the DFF circuit 16f, the H-level signal is input from the NOR circuit 31 to the DFF circuit 16f. As a result, the H-level clock signal CLK when the state signal STT5 is maintained at the L level is input to the DFF circuit 16f, whereby the H-level count-up signal CUP and the L-level inversion count are received from the DFF circuit 16f. The up signal CUPB is output.

The L level inversion count up signal CUPB is input to the OR circuit 29. Since the L level signal is input to the OR circuit 29 from the NAND circuit 25, the L level signal is input to the NAND circuit 27 from the OR circuit 25. Since the H level signal is input from the NAND circuit 26 to the NAND circuit 27, the H level signal is input from the NAND circuit 27 to the selector circuit 19. As a result, since the input of the selector circuit 19 is switched to the "1" side, the inverted state signal STT5B of the H level output from the DFF circuit 16e is supplied to the DFF circuit 16e via the selector circuit 19. . As a result, the H-level clock signal CLK when the state signal STT3 is maintained at the H level is input to the DFF circuit 16f, and then the clock signal CLK input to the DFF circuit 16e is lowered to the L level. Then, by raising to H level, the state signal STT5 of H level is output from the DFF circuit 16e. In this way, the rise of the state signal STT5 to the H level is delayed for two periods of the clock signal CLK of the two H levels from the rise of the state signal STT4 to the H level.

The LFF inverted state signal STT5B is output from the DFF circuit 16e. The L level inverted state signal STT5B is input to the NAND circuit 25. The H-level state signal STT4 is input to the NAND circuit 25 from the DFF circuit 16d, so that the H-level signal is input from the NAND circuit 25 to the AND circuit 30. Since the H level signal is input from the NAND circuit 23 to the AND circuit 30, the H level signal is input from the AND circuit 30 to the NOR circuit 31. Since the H level count-up signal CUP is input from the DFF circuit 16f to the NOR circuit 31, an L-level signal is input from the NOR circuit 31 to the DFF circuit 16f. As a result, the H-level clock signal CLK when the state signal STT4 rises to the H level is input to the DFF circuit 16f, whereby the L-level count-up signal CUP and the H-level inversion count are received from the DFF circuit 16f. The up signal CUPB is output.

On the other hand, the H level state signal STT5 output from the DFF circuit 16e is input to the NAND circuit 20. Since the N-level state signal STT1 is input to the NAND circuit 20 from the DFF circuit 16a, the L-level signal is output from the NAND circuit 20. Thereby, since the L level signal is input from the NAND circuit 20 and the inverting chip selection signal CSB of the H level is input to the NAND circuit 21, the HAND signal is input from the NAND circuit 21 to the selector circuit 17. The signal of the level is input. As a result, since the input of the selector circuit 17 is switched to the "1" side, the L-level inverted state signal STT1B output from the DFF circuit 16a is supplied to the DFF circuit 16a via the selector circuit 17. Thereafter, the clock signal CLK input to the DFF circuit 16a falls to the L level and then rises to the H level, whereby the LFF state signal STT1 is output from the DFF circuit 16a. The L-level state signal STT1 is input to the DFF circuit 16b. Subsequently, after the clock signal CLK input to the DFF circuit 16b falls to the L level and then rises to the H level, the LFF state signal STT2 and the H level inverted state signal are increased from the DFF circuit 16b. STT2B is output.

Then, the L-level state signal STT2 is input to the NAND circuit 22. Since the inverted state signal STT3B of L level is input to the NAND circuit 22 from the DFF circuit 16c, the H level signal is input from the NAND circuit 22 to the NAND circuit 24. On the other hand, the H level inverted state signal STT2B output from the DFF circuit 16b is input to the NAND circuit 23. In addition, since the high-level state signal STT3 is input from the DFF circuit 16c to the NAND circuit 23, the low-level signal is input from the NAND circuit 23 to the OR circuit 28. At this time, since the H level inversion count-up signal CUPB is input from the DFF circuit 16f to the OR circuit 28, the H level signal is input from the OR circuit 28 to the NAND circuit 24. For this reason, the L level signal is input from the NAND circuit 24 to the selector circuit 18. Thereby, since the input of the selector circuit 18 is hold | maintained at the "0" side, the H-state state signal STT3 output from the DFF circuit 16c is supplied to the DFF circuit 16c via the selector circuit 18. As shown in FIG. For this reason, even when the clock signal CLK input to the DFF circuit 16c falls to the L level and then rises to the H level, the state signal STT3 output from the DFF circuit 16c is maintained at the H level. do.

The L level signal output from the NAND circuit 23 is also input to the AND circuit 30. At this time, since the H level signal is input from the NAND circuit 25 to the AND circuit 30, the L level signal is input from the AND circuit 30 to the NOR circuit 31. Since the L-level count-up signal CUP is input to the NOR circuit 31 from the DFF circuit 16f, the H-level signal is input from the NOR circuit 31 to the DFF circuit 16f. As a result, the H-level clock signal CLK when the state signal STT3 is maintained at the H level is input to the DFF circuit 16f, whereby the H-level count-up signal CUP and the L-level inverted count are received from the DFF circuit 16f. The up signal CUPB is output.

The L level inversion count up signal CUPB is input to the OR circuit 28. Since the L level signal is input from the NAND circuit 23 to the OR circuit 28, the L level signal is input from the OR circuit 28 to the NAND circuit 24. Since the H level signal is input from the NAND circuit 22 to the NAND circuit 24, the H level signal is input from the NAND circuit 24 to the selector circuit 18. As a result, since the input of the selector circuit 18 is switched to the &quot; 1 &quot; side, the L level inverted state signal STT3B output from the DFF circuit 16c is supplied to the DFF circuit 16c via the selector circuit 18. . Subsequently, after the clock signal CLK input to the DFF circuit 16c falls to the L level and rises to the H level, the state signal STT3 of the L level is output from the DFF circuit 16c. In this way, the reduction to the L level of the state signal STT3 is delayed for two periods of the clock signal CLK of two H levels from the fall to the L level of the state signal STT2.

Thereafter, in the same manner as when the state signals STT4 and STT5 are raised to the H level, the state signal STT4 is lowered to the L level by delaying for one clock period against the fall of the state signal STT3 to the L level. At the same time, the state signal STT5 is lowered to the L level by a delay of one clock period. However, the operation at this time performs the operation of replacing the H level and the L level of each signal in the operation when raising the state signals STT4 and STT5 to the H level.

Instead of the state machine circuit 11 shown in FIG. 8, a state machine circuit 91 as shown in FIG. 9 can be used for the memory according to the first embodiment. In addition, this state machine circuit 91 is an example of the "control circuit" of this invention. In the state machine circuit 91, unlike the clock synchronous state machine circuit 11 (see FIG. 8), the state machine circuit 91 is constituted by supplying the L-level inversion chip select signal CSB. The delay circuits of the subsequent stages are configured to sequentially generate output signals delayed from the output signals of the delay circuits of the previous stages without using a clock signal inside each of the delay circuits 96a to 96e. The delay circuits 96a to 96e are examples of the "delay circuit part" of the present invention.

Specifically, this state machine circuit 91 includes five delay circuits 96a to 96e, two NAND circuits 97 and 98, and one inverter circuit 99 as shown in FIG. It consists of). The state signals STT1 to STT4 output from each of the delay circuits 96a to 96d are input to the delay circuits 96b to 96e at the subsequent stage. In addition, the output signal of the NAND circuit 97 is input to the delay circuit 96a. The state signal STT5 output from the delay circuit 96e is input to the inverter circuit 99. The output signal of the inverter circuit 99, the inversion reset signal RSTB, and the output signal of the NAND circuit 97 are input to the NAND circuit 98. In addition, the output signal of the NAND circuit 98 and the inverting chip select signal CSB are input to the NAND circuit 97.

In addition, as shown in FIG. 10, the delay circuit 96c alternately connects two types of inverter circuits 96f and 96g having different configurations in series, and the inverter circuit 96f on the input side of the state signal STT2. ) Is arranged. As shown in Fig. 11, the delay circuit 96e alternately connects two types of inverter circuits 96f and 96g in series, and arranges the inverter circuit 96g on the input side of the state signal STT4. It is comprised by doing.

In addition, the inverter circuit 96f is composed of a CMOS inverter composed of a p-channel transistor 96h and an n-channel transistor 96i, as shown in FIG. In addition, the p-channel transistor 96h is configured such that the gate width GW becomes smaller than the gate length GL, and the n-channel transistor 96i has a gate compared to the gate length GL. It is comprised so that width GW may become large. As a result, the inverter circuit 96f is configured to slow the rise of the output signal with respect to the degradation of the input signal and to accelerate the fall of the output signal with respect to the rise of the input signal. On the other hand, the inverter circuit 96g is constituted by a CMOS inverter composed of a p-channel transistor 96j and an n-channel transistor 96k, as shown in FIG. In addition, the p-channel transistor 96j is configured to have a larger gate width GW compared to the gate length GL, and the n-channel transistor 96k is compared with the gate length GL. It is comprised so that gate width GW may become small. Thereby, the inverter circuit 96g is comprised so that the rise of an output signal may accelerate with respect to the fall of an input signal, and the fall of an output signal will become slow with respect to a rise of an input signal. With this configuration, in the delay circuit 96c, the delay amount of the decrease in the output signal (state signal STT3) with respect to the decrease in the input signal (state signal STT2) is the output signal (in response to the rise of the input signal (state signal STT2). It is approximately doubled compared to the delay amount of the rise of the state signal STT3). In the delay circuit 96e, the delay amount of the rise of the output signal (state signal STT5) with respect to the rise of the input signal (state signal STT4) is the output signal (state signal STT5) of the decrease of the input signal (state signal STT4). It is about doubled compared to the delay amount of decrease of).

The delay circuits 96a, 96b, and 96d are each composed of a CMOS inverter composed of a p-channel transistor and an n-channel transistor, each having a gate length GL and a gate width GW having substantially the same size. As a result, the delay circuits 96a, 96b, and 96d are configured such that the delay amount of the rise of the output signal with respect to the degradation of the input signal and the delay amount of the fall of the output signal with respect to the rise of the input signal are substantially the same. . The delay amount of the rise of the output signal (state signal STT5) relative to the rise of the input signal (state signal STT4) by the delay circuit 96e is determined by the input signal (state signal STT1) of each of the delay circuits 96b to 96d. The output signal (state signals STT2 to 4) with respect to the rise of -3 is configured to be about twice the delay amount of the rise. In addition, the delay amount of the reduction of the output signal (state signal STT3) with respect to the decrease of the input signal (state signal STT2) by the delay circuit 96c is the input signal (state signal STT1) of each of the delay circuits 96b to 96d. Delay amount of the rise of the output signal (state signals STT2 to 4) with respect to the rise of ˜3) and decrease of the input signal (state signals STT1, STT3 and STT4) by the delay circuits 96b, 96d, and 96e, respectively. The output signal (state signals STT2, STT4 and STT5) is configured to be about twice the delay amount of the decrease.

When the state machine circuit 91 according to the modification of the first embodiment is used, the delay amount of the rise of the state signal STT5 which sets the end point for the rise of the state signal STT4 which sets the start point of the period T3 for rewriting, The delay amount of the fall of the state signal STT3 which sets the end point for the fall of the state signal STT2 which sets the time point of the period T5 is set to the rise of the state signal STT1-3 of the preceding stage which sets the time point of the period T1-T22, respectively. The delay amount of the rise of the state signals STT2 to 4 at the subsequent stages for setting the end points of the periods T1 to T22 can be set to about twice the delay. As a result, the lengths of the periods T3 and T5 for rewriting can be approximately twice the lengths of the respective periods of the periods T1 to T22. Therefore, the memory is read and rewritten in a short transition period (each period of the T1 to T62). By increasing the period for rewriting the memory cells in the second cell region (see FIG. 3) while speeding up the write operation, a period of length necessary for rewriting to the memory cells in the second cell region can be ensured. Can be. This makes it possible to reliably rewrite data to the memory cells of the second cell region while speeding up the operation of the memory.

FIG. 14 is a circuit diagram showing the configuration of the word line source driver 12 which generates word line source control signals XSE3B to 0 and XUE2B to 0. As shown in FIG. As shown in Fig. 14, the word line source driver 12 combines the state signals STT1 to 5 and the inverted state signals STT1B to 5B supplied from the state machine circuit 11, thereby providing a word line source control signal. Generate XSE3B-0 and XUE2B-0. In addition, the word line source driver 12 uses a combination of the generated word line source control signals XSE3B to 0 to generate a word line source of any one of VSS (0V), 1 / 3VCC, and VCC from one output terminal. By outputting the signal SLSX and combining the generated word line source control signals XUE2B to 0, the word line source signal of any one of VSS (0 V), 1/3 VCC and 2/3 VCC from the other output terminal. It is configured to output USSX.

Specifically, the word line source driver 12 includes six NAND circuits 32 to 37, two NOR circuits 38 and 39, four NAND inverter circuits 40 to 43, and two It consists of two stage inverter circuits 44 and 45, two p-channel transistors 46 and 49, and four n-channel transistors 47, 48, 50 and 51. The state signal STT1 and the inverted state signal STT2B are input to the NAND circuit 32. The state signal STT4 and the inverted state signal STT5B are input to the NAND circuit 33. In addition, the inverted state signal STT2B and the state signal STT3 are input to the NAND circuit 34. The inverted state signal STT2B and the inverted state signal STT5B are input to the NAND circuit 35. The inverted state signal STT3B and the state signal STT5 are input to the NAND circuit 36. The state signal STT4 and the inverted state signal STT1B are input to the NAND circuit 37. In addition, state signals STT1 and STT2 are input to the NOR circuit 38. In addition, the state signals STT2 and STT5 are input to the NOR circuit 39.

In addition, the output signals of the NAND circuits 32 and 33 are input to the NAND-inverter circuit 40. In addition, the output signals of the NAND circuits 33 to 35 are input to the NAND inverter circuit 41. In addition, the output signals of the NAND circuit 36 and the NOR circuit 38 are input to the NAND-inverter circuit 42. In addition, the output signals of the NAND circuits 35 and 37 are input to the NAND-inverter circuit 43. In addition, the output signal of the NAND circuit 37 is input to the two-stage inverter circuit 44. In addition, the output signal of the NOR circuit 39 is input to the two-stage inverter circuit 45.

The output signal (word line source control signal XSE3B) of the NAND-inverter circuit 40 is supplied to the gate of the p-channel transistor 46. The output signal (word line source control signal XSE1) of the NAND-inverter circuit 41 is supplied to the gate of the n-channel transistor 47. The output signal (word line source control signal XSE0) of the NAND-inverter circuit 42 is supplied to the gate of the n-channel transistor 48. The output signal (word line source control signal XUE1) of the NAND-inverter circuit 43 is supplied to the gate of the n-channel transistor 50. The output signal (word line source control signal XUE2B) of the two-stage inverter circuit 44 is supplied to the gate of the p-channel transistor 49. The output signal (word line source control signal XUE0) of the two-stage inverter circuit 45 is supplied to the gate of the n-channel transistor 51.

In addition, VCC is supplied to the source of the p-channel transistor 46, and the drain of the p-channel transistor 46 is connected to the drains of the n-channel transistors 47 and 48. In addition, 1 / 3VCC is supplied to the source of the n-channel transistor 47, and VSS (GND potential: 0V) is supplied to the source of the n-channel transistor 48.

In addition, 2/3 VCC is supplied to the source of the p-channel transistor 49, and the drain of the p-channel transistor 49 is connected to the drains of the n-channel transistors 50 and 51. In addition, 1 / 3VCC is supplied to the source of the n-channel transistor 50, and VSS (GND potential: 0V) is supplied to the source of the n-channel transistor 51.

In the operation of the word line source driver 12, first, in the period T0 (see FIG. 5), the L level state signals STT1 to 5 and the H level inverted state signals STT1B to 5B are inputted, respectively, so that the NAND circuit ( The H level signals are output from the 32 to 34, 36 and 37 and the NOR circuits 38 and 39, respectively, and the L level signals are output from the NAND circuit 35. Thereby, the word line source control signals XSE3B, XSE0, XUE2B and XUE0 of H level are output from the NAND-inverter circuits 40 and 42 and the two-stage inverter circuits 44 and 45, respectively, and the NAND circuit From (41 and 43), word line source control signals XSE1 and XUE1 of L level are output, respectively. For this reason, since the p-channel transistor 46 and the n-channel transistor 47 are turned off and the n-channel transistor 48 is turned on, the word line source signal SLSX of VSS is transmitted through the n-channel transistor 48. Is output to the outside. In addition, since the p-channel transistor 49 and the n-channel transistor 50 are turned off and the n-channel transistor 51 is turned on, the word line source signal USSX of VSS is transferred through the n-channel transistor 51. It is output to the outside.

Subsequently, when the transition is made to the period T1 (see FIG. 5), the state signal STT1 and the inverted state signal STT1B become H level and L level, respectively, so that the L from the NAND circuits 32 and 35 and the NOR circuit 38 are L. FIG. A signal of the level is output, and a signal of the H level is output from the NAND circuits 33, 34, 36, and 37 and the NOR circuit 39. As a result, the word line source control signals XSE3B to 0 and XUE1 output from the NAND-inverter circuits 40 to 42 and 43 become L level, and the word line source to be output from the two-stage inverter circuits 44 and 45. Control signals XUE2B and XUE0 are held at H level. For this reason, since the p-channel transistor 46 is turned on and the n-channel transistors 47 and 48 are turned off, the word line source signal SLSX of VCC is output to the outside via the p-channel transistor 46. . In addition, since the p-channel transistor 49 and the n-channel transistor 50 are kept in the off state and the n-channel transistor 51 is in the on state, the word line source signal of VSS is transmitted through the n-channel transistor 51. The USSX continues to output externally.

Subsequently, when the transition is made to the period T21 (see FIG. 5), the state signal STT2 and the inverted state signal STT2B become H level and L level, respectively, so that signals of H level are respectively supplied from the NAND circuits 32 to 37. While being output, signals of L level are output from the NOR circuits 38 and 39, respectively. Thereby, the word line source control signals XSE3B, XSE1, XUE1, and XUE2B of H level are output from the NAND inverter circuits 40, 41, and 43 and the inverter circuit 44 of the two stages, respectively, and the NAND inverter circuit The word line source control signals XSE0 and XUE0 of L level are output from the 42 and the inverter circuit 45 of the two stages, respectively. For this reason, since the p-channel transistor 46 and the n-channel transistor 48 are turned off, respectively, and the n-channel transistor 47 is turned on, the word of 1 / 3VCC is transmitted through the n-channel transistor 47. The line source signal SLSX is output to the outside. In addition, since the p-channel transistor 49 and the n-channel transistor 51 are turned off and the n-channel transistor 50 is turned on, respectively, the word line of 1/3 VCC is provided through the n-channel transistor 50. The source signal USSX is output to the outside.

Subsequently, the transition to the period T22 (see Fig. 5) causes the state signal STT3 and the inverted state signal STT3B to be at the H level and the L level, respectively, so that the signals at the H level are respectively supplied from the NAND circuits 32 to 37. While being output, signals of L level are output from the NOR circuits 38 and 39, respectively. As a result, the word line source signal SLSX of 1 / 3VCC and the word line source signal USSX of 1 / 3VCC are continuously output to the outside by the operation similar to the above-described period T21.

Subsequently, when the transition is made to the period T3 (see FIG. 5), the state signal STT4 and the inverted state signal STT4B are set to H level and L level, respectively, so that the H level from the NAND circuits 32 and 34 to 37 are respectively increased. While the signal is output, the L level signal is output from the NAND circuit 33 and the NOR circuits 38 and 39, respectively. Thereby, the L-level word line source control signals XSE3B to 0 and XUE0 are output from the NAND-inverter circuits 40 to 42 and the two-stage inverter circuit 45, respectively, and the NAND-inverter circuit 43 and From the two-stage inverter circuit 44, word line source control signals XUE2B and XUE1 of H level are respectively output. For this reason, since the p-channel transistor 46 is turned on and the n-channel transistors 47 and 48 are turned off, respectively, the word line source signal SLSX of the VCC is externally transferred through the p-channel transistor 46. Is output. In addition, since the p-channel transistor 49 and the n-channel transistor 51 are kept in the off state, respectively, and the n-channel transistor 50 is kept in the on state, the n-channel transistor 50 makes up the 1/3 VCC. The word line source signal USSX continues to be output externally.

Subsequently, the transition to the period T41 (see FIG. 5) causes the state signal STT5 and the inverted state signal STT5B to be at the H level and the L level, respectively, so that the signals of the H level are respectively supplied from the NAND circuits 32 to 37. While being output, signals of L level are output from the NOR circuits 38 and 39, respectively. As a result, the word line source signal SLSX of 1 / 3VCC and the word line source signal USSX of 1 / 3VCC are output to the outside by the same operation as in the above-described period T21.

Subsequently, the transition to the period T42 (see FIG. 5) causes the state signal STT1 and the inverted state signal STT1B to be at the L level and the H level, respectively, so that the signals of the H level are respectively supplied from the NAND circuits 32 to 36. While being output, signals of L level are output from the NAND circuit 37 and the NOR circuits 38 and 39, respectively. As a result, the H-level word line source control signals XSE3B and XSE1 are output from the NAND-inverter circuits 40 and 41, respectively, and the NAND-inverter circuits 42 and 43 and the two-stage inverter circuits 44 and 45 are output. L word line source control signals XSE0, XUE1, XUE2B and XUE0 are respectively outputted from the &quot; L &quot; For this reason, since the p-channel transistor 46 and the n-channel transistor 48 are turned off, respectively, and the n-channel transistor 47 is turned on, the word of 1 / 3VCC is transmitted through the n-channel transistor 47. The line source signal SLSX continues to be output externally. In addition, since the p-channel transistor 49 is turned on and the n-channel transistors 50 and 51 are turned off, the word line source signal USSX of 2 / 3VCC is output to the outside through the p-channel transistor 49. do.

Subsequently, when the transition is made to the period T5 (see Fig. 5), the state signal STT2 and the inverted state signal STT2B become L level and H level, respectively, so that the NAND circuits 32, 33, 35, and 36 and the NOR circuit ( Signals of H level are output from 38, and signals of L level are output from NAND circuits 34 and 37 and NOR circuit 39, respectively. As a result, the H-level word line source control signals XSE3B and XSE0 are output from the NAND inverter circuits 40 and 42, respectively, and the NAND inverter circuits 41 and 43 and the two stage inverter circuits 44 and 45 are output. ), L-level word line source control signals XSE1, XUE1, XUE2B and XUE0 are output. For this reason, since the n-channel transistor 48 is turned on and the p-channel transistor 46 and the n-channel transistor 47 are turned off, the word line source signal SLSX of VSS is passed through the n-channel transistor 48. Is output to the outside. In addition, since the p-channel transistor 49 remains on and the n-channel transistors 50 and 51 remain off, the word line source signal USSX of 2/3 VCC continues through the p-channel transistor 49. Is output to the outside.

Subsequently, the transition to the period T61 (see FIG. 5) causes the state signal STT3 and the inverted state signal STT3B to become L level and H level, respectively, from the NAND circuits 32 to 35 and the NOR circuit 38. Signals of H level are output, respectively, and signals of L level are respectively output from the NAND circuits 36 and 37 and the NOR circuit 39. As a result, the H-level word line source control signals XSE3B and XSE1 are output from the NAND-inverter circuits 40 and 41, respectively, and the NAND-inverter circuits 42 and 43 and the two-stage inverter circuits 44 and 45 are output. ), L-level word line source control signals XSE0, XUE1, XUE2B and XUE0 are respectively output. For this reason, since the p-channel transistor 46 and the n-channel transistor 48 are turned off and the n-channel transistor 47 is turned on, the word line source of 1/3 VCC is provided through the n-channel transistor 47. The signal SLSX is output externally. In addition, since the p-channel transistor 49 remains on and the n-channel transistors 50 and 51 remain off, the word line source signal USSX of 2/3 VCC continues through the p-channel transistor 49. Is output to the outside.

Subsequently, when the transition is made to the period T62 (see Fig. 5), the state signal STT4 and the inverted state signal STT4B become L level and H level, respectively, so that the NAND circuits 32 to 35 and 37 and the NOR circuit 38 are performed. From the NAND circuit 36 and the NOR circuit 39, signals of H level are output, respectively. Thereby, the word line source control signals XSE3B, XSE1, XUE1, and XUE2B of H level are output from the NAND inverter circuits 40, 41, and 43 and the inverter circuit 44 of the two stages, respectively, and the NAND inverter circuit The word line source control signals XSE0 and XUE0 of L level are output from the 42 and the inverter circuit 45 of the two stages, respectively. For this reason, since the p-channel transistor 46 and the n-channel transistor 48 are kept in the off state and the n-channel transistor 47 is in the on state, the word of 1 / 3VCC is passed through the n-channel transistor 47. The line source signal SLSX continues to be output externally. In addition, since the p-channel transistor 49 and the n-channel transistor 51 are turned off and the n-channel transistor 50 is turned on, the word line source signal of 1/3 VCC is transmitted through the n-channel transistor 50. USSX is output to the outside.

Finally, if the state transitions back to the period T0 (see Fig. 5), the state signal STT5 and the inverted state signal STT5B become L level and H level, respectively, so that the state signals STT1 to 5 become L level. The inverted state signals STT1B to 5B all become H levels. As a result, the word line source signal SLSX of VSS and the word line source signal USSX of VSS are output to the outside by the same operation as the first period T0 described above.

Next, with reference to FIG. 15, the structure of the row decoder 2 supplied with the word line source signals SLSX and USSX from the word line source driver 12 will be described. The row decoder 2 according to the first embodiment includes four p-channel transistors 52 to 55, five n-channel transistors 56 to 60, and three inverter circuits 61 to 63. . The address signal RALOW is supplied to the source of the p-channel transistor 52 from the row address buffer 4 (see FIG. 1), and the address signal RAUPP is supplied to the gate. In addition, VSS (GND potential: 0V) is supplied to the source of the n-channel transistor 56, and the address signal RAUPP is supplied from the row address buffer 4 (see FIG. 1) to the gate. The drain of the p-channel transistor 52 and the drain of the n-channel transistor 56 are connected to the gate of the n-channel transistor 58, and the p-channel transistor 54 is interposed through the inverter circuit 62. It is connected to the gate of. The word line source signal SLSX is supplied from the word line source driver 12 (see FIGS. 1 and 14) to the sources of the p-channel transistor 54 and the n-channel transistor 58. The drains of the p-channel transistor 54 and the n-channel transistor 58 are both connected to the word line WL.

The address signal RALOW is supplied from the row address buffer 4 (see FIG. 1) to the source of the p-channel transistor 53 through the inverter circuit 61, and the row address buffer 4 (FIG. 1) is provided to the gate. Address signal RAUPP is supplied. In addition, VSS (GND potential: 0V) is supplied to the source of the n-channel transistor 57, and the address signal RAUPP is supplied from the row address buffer 4 (see FIG. 1) to the gate. The drain of the p-channel transistor 53 and the drain of the n-channel transistor 57 are connected to the gate of the n-channel transistor 59, and the gate of the p-channel transistor 55 via the inverter circuit 63. Is connected to. In addition, the word line source signal USSX is supplied to the source of the p-channel transistor 55 and the n-channel transistor 59 from the word line source driver 12 (see FIGS. 1 and 14). The drains of the p-channel transistor 55 and the n-channel transistor 59 are both connected to the word line WL. In addition, VSS (GND potential: 0V) is supplied to the source of the n-channel transistor 60, and address signal RAUPP is supplied from the row address buffer 4 (see FIG. 1) to the gate. The drain of the n-channel transistor 60 is connected to the word line WL.

As the operation of the row decoder 2, first, in the standby state period T0 (see FIG. 5), the L level address signal RALOW and the H level address signal RAUPP are supplied from the row address buffer 4 (see FIG. 1). Supplied. As a result, the p-channel transistors 52 and 53 are turned off while the n-channel transistors 56, 57 and 60 are turned on. As a result, the VSS (L level) is supplied to the gate of the n channel transistor 58 through the n channel transistor 56, and the H level signal inverted through the inverter circuit 62 receives the p channel transistor ( 54). As a result, the n-channel transistor 58 and the p-channel transistor 54 are both turned off. In addition, while the VSS (L level) is supplied to the gate of the n channel transistor 59 through the n channel transistor 57, the H level signal inverted through the inverter circuit 63 receives the p channel transistor 55. Is supplied to the gate. As a result, the n-channel transistor 59 and the p-channel transistor 55 are both turned off. In addition, VSS is supplied to the word line WL through the n-channel transistor 60.

Subsequently, the process shifts to the periods T1 to T62 (see FIG. 5) in the operating state. In the periods T1 to T62 of this operating state, when the word line WL is selected, the address signal RALOW becomes H level and the address signal RAUPP becomes L level. As a result, the p-channel transistors 52 and 53 are turned on, and the n-channel transistors 56, 57 and 60 are turned off. Therefore, the H-level address signal RALOW is supplied to the gate of the n-channel transistor 58 through the p-channel transistor 52, and the L-level address signal RALOW inverted through the inverter circuit 62 is p. Supplied to the gate of the channel transistor 54. As a result, since both the n-channel transistor 58 and the p-channel transistor 54 are turned on, the word line source signal SLSX is transferred to the word line WL through the n-channel transistor 58 and the p-channel transistor 54. Supplied. Further, the L-level address signal RALOW inverted by the inverter circuit 61 is supplied to the gate of the n-channel transistor 59 through the p-channel transistor 53, and further inverted through the inverter circuit 63. The high level address signal RALOW is supplied to the gate of the p-channel transistor 55. As a result, since the n-channel transistor 59 and the p-channel transistor 55 are both turned off, the word line source signal USSX is not supplied to the word line WL.

In the periods T1 to T62 (see Fig. 5) in the operating state, when the word line WL is not selected, both the address signal RALOW and the address signal RAUPP become L level. As a result, the p-channel transistors 52 and 53 are turned on, and the n-channel transistors 56, 57 and 60 are turned off. Therefore, the L-level address signal RALOW is supplied to the gate of the n-channel transistor 58 through the p-channel transistor 52, and the H-level address signal RALOW inverted through the inverter circuit 62 is p. Supplied to the gate of the channel transistor 54. As a result, since the n-channel transistor 58 and the p-channel transistor 54 are both turned off, the word line source signal SLSX is not supplied to the word line WL. Further, the H-level address signal RALOW inverted by the inverter circuit 61 is supplied to the gate of the n-channel transistor 59 through the p-channel transistor 53, and further inverted through the inverter circuit 63. The low level address signal RALOW is supplied to the gate of the p-channel transistor 55. As a result, since the n-channel transistor 59 and the p-channel transistor 55 are both turned on, the word line source signal USSX is supplied to the word line WL through the n-channel transistor 59 and the p-channel transistor 55. do.

FIG. 16 is a circuit diagram showing the configuration of the bit line source driver for generating the bit line source control signals YHE3B to 0 and YLE2B to 0. FIG. As shown in FIG. 16, the bit line source driver 13 combines the state signals STT1 and STT3 to 5 supplied from the state machine circuit 11 with the inverted state signals STT2B, 4B and 5B. The bit line source control signals YHE3B to 0 and YLE2B to 0 are generated. The bit line source driver 13 combines the generated bit line source control signals YHE3B to 0 to form a bit line source signal HSY of any one of VSS, 1 / 3VCC, and VCC from one output terminal. And combines the generated bit line source control signals YLE2B to 0 to output the bit line source signal LSY of any one of VSS, 1 / 3VCC and 2 / 3VCC from the other output terminal. Consists of.

Specifically, the bit line source driver 13 includes five NAND circuits 64 to 68, one NOR circuit 69, three NAND-inverter circuits 70 to 72, and three two. The inverter circuits 73 to 75 of the stage, two p-channel transistors 76 and 79, and four n-channel transistors 77, 78, 80 and 81 are constituted. The state signal STT3 and the inverted state signal STT2B are input to the NAND circuit 64. The state signal STT4 and the inverted state signal STT5B are input to the NAND circuit 65. The inverted state signals STT2B and STT5B are input to the NAND circuit 66. The state signal STT1 and the inverted state signal STT4B are input to the NAND circuit 67. In addition, the state signals STT1 and STT3 are input to the NAND circuit 68. In addition, the state signals STT1 and STT5 are input to the NOR circuit 69.

In addition, the output signals of the NAND circuits 64, 65, and 66 are input to the NAND-inverter circuit 70. The inverted state signal STT5B and the output signal of the NAND circuit 67 are input to the NAND-inverter circuit 71. In addition, the output signals of the NAND circuits 66 and 68 are input to the NAND-inverter circuit 72. In addition, the output signal of the NAND circuit 64 is input to the two-stage inverter circuit 73. In addition, the output signal of the NAND circuit 68 is input to the two-stage inverter circuit 74. In addition, the output signal of the NOR circuit 69 is input to the two-stage inverter circuit 75.

The output signal of the NAND-inverter circuit 70 (bit line source control signal YHE1) is supplied to the gate of the n-channel transistor 77. In addition, the output signal (bit line source control signal YHE0) of the NAND-inverter circuit 71 is supplied to the gate of the n-channel transistor 78. The output signal (bit line source control signal YLE1) of the NAND-inverter circuit 72 is supplied to the gate of the n-channel transistor 80. The output signal (bit line source control signal YHE3B) of the two-stage inverter circuit 73 is supplied to the gate of the p-channel transistor 76. The output signal (bit line source control signal YLE2B) of the two-stage inverter circuit 74 is supplied to the gate of the p-channel transistor 79. The output signal (bit line source control signal YLE0) of the two-stage inverter circuit 75 is supplied to the gate of the n-channel transistor 81. The other configuration of the bit line source driver 13 is the same as that of the word line source driver 12 described above.

As the operation of the bit line source driver 13, first, in the period T0 (see FIG. 5), the NAND state signals STT1 and STT3 to 5 and the inverted state signals STT2B, 4B and 5B of the H level are input, respectively, to thereby NAND. The H level signals are output from the circuits 64, 65, 67 and 68 and the NOR circuit 69, and the L level signals are output from the NAND circuit 66, respectively. Thereby, the L-level bit line source control signals YHE1 and YLE1 are output from the NAND inverter circuits 70 and 72, respectively, and from the NAND circuit 71 and the two-stage inverter circuits 73 to 75, respectively. The bit line source control signals YHE0, YHE3B, YLE2B and YLE0 of the H level are output. For this reason, since the p-channel transistor 76 and the n-channel transistor 77 are turned off and the n-channel transistor 78 is turned on, the bit line source signal HSY of VSS is transmitted through the n-channel transistor 78. Is output to the outside. In addition, since the p-channel transistor 79 and the n-channel transistor 80 are turned off and the n-channel transistor 81 is turned on, the bit line source signal LSY of VSS is passed through the n-channel transistor 81. It is output to the outside.

Subsequently, the transition to the period Tl (see FIG. 5) causes the state signal STT1 to become H level, thereby outputting the H level signal from the NAND circuits 64, 65, and 68, and the NAND circuits 66 and 67. ) And the NOR circuit 69 output an L level signal. As a result, the bit line source control signals YHE1, YHE0, YLE1, and YLE0 output from the NAND-inverter circuits 70 to 72 and the two-stage inverter circuits 75 become L levels, and the two-stage inverter circuits ( The bit line source control signals YHE3B and YLE2B output from 73 and 74 become H level. For this reason, the p-channel transistors 76 and 79 and the n-channel transistors 77, 78, 80 and 81 are both turned off. As a result, the nodes ND1 and ND2 for outputting the bit line source signals HSY and LSY to the outside are respectively in an open state (floating state), so that the bit line source signals HSY and LSY are respectively in a high impedance state.

Subsequently, the transition to the period T21 (see Fig. 5) causes the inverted state signal STT2B to go to the L level because the state signal STT2 goes to the H level, so that the signals of the H level are supplied from the NAND circuits 64 to 66 and 68, respectively. Is output, and L level signals are output from the NAND circuit 67 and the NOR circuit 69, respectively. Thereby, the bit line source control signals YHE1, YLE1, YHE3B, and YLE2B of H level are output from the NAND-inverter circuits 70 and 72 and the two-stage inverter circuits 73 and 74, respectively. The L-level bit line source control signals YHE0 and YLE0 are output from the inverter circuit 71 and the inverter circuit 75 in two stages, respectively. For this reason, since the p-channel transistor 76 and the n-channel transistor 78 are turned off, respectively, and the n-channel transistor 77 is turned on, the bit of 1 / 3VCC is transmitted through the n-channel transistor 77. The line source signal HSY is output externally. In addition, since the p-channel transistor 79 and the n-channel transistor 81 are turned off and the n-channel transistor 80 is turned on, respectively, the 1 / 3-VCC bit line is provided through the n-channel transistor 80. The source signal LSY is output externally.

Subsequently, when the transition to the period T22 (see FIG. 5) occurs, the state signal STT3 becomes H level, so that the H level signals are output from the NAND circuits 64 to 66, respectively, and the NAND circuits 67 and 68. ) And the NOR circuit 69 output signals of L level, respectively. As a result, the H-level bit line source control signals YHE3B and YHE1 are output from the two-stage inverter circuit 73 and the NAND-inverter circuit 70, respectively, while the two-stage NAND-inverter circuits 71 and 72 and the second stage are output. The bit line source control signals YHE0, YLE1, YLE2B, and YLE0 of L level are output from the inverter circuits 74 and 75, respectively. For this reason, since the p-channel transistor 76 and the n-channel transistor 78 are each kept in the off state and the n-channel transistor 77 is in the on state, 1 / 3VCC is provided through the n-channel transistor 77. The bit line source signal HSY is output to the outside. In addition, since the p-channel transistor 79 and the n-channel transistors 80 and 81 are turned off, respectively, the bit line source signal LSY becomes a high impedance state.

Subsequently, when the transition is made to the period T3 (see FIG. 5), the state signal STT4 and the inverted state signal STT4B become the H level and the L level, respectively, so that the H level from the NAND circuits 64, 66, and 67 is respectively increased. While signals are output, signals of L level are output from the NAND circuits 65 and 68 and the NOR circuit 69, respectively. As a result, the L-level bit line source control signals YHE1, YLE1, YLE2B, and YLE0 are respectively output from the NAND-inverter circuits 70 and 72 and the two-stage inverter circuits 74 and 75, and the NAND-inverter is output. The bit line source control signals YHE0 and YHE3B of H level are respectively output from the circuit 71 and the inverter circuit 73 of two stages. For this reason, since the p-channel transistor 76 and the n-channel transistor 77 are turned off and the n-channel transistor 78 is turned on, the bit line source signal HSY of VSS is transmitted through the n-channel transistor 78. Is output to the outside. In addition, since the p-channel transistor 79 and the n-channel transistors 80 and 81 are kept in the off state, respectively, the bit line source signal LSY is kept in the high impedance state.

Subsequently, when the transition is made to the period T41 (see FIG. 5), the state signal STT5 and the inverted state signal STT5B become the H level and the L level, respectively, so that the H level signals are output from the NAND circuits 64 to 67, respectively. While being output, signals of L level are output from the NAND circuit 68 and the NOR circuit 69, respectively. Thereby, the bit line source control signals YHE1 and YHE3B of H level are output from the NAND-inverter circuit 70 and the inverter circuit 73 of the two stages, and the NAND-inverter circuits 71 and 72 and 2, respectively. L-level bit line source control signals YHE0, YLE1, YLE2B and YLE0 are output from the inverter circuits 74 and 75 of the stages, respectively. For this reason, since the p-channel transistor 76 and the n-channel transistor 78 are turned off and the n-channel transistor 77 is turned on, the bit line source of 1/3 VCC is provided through the n-channel transistor 77. The signal HSY is output externally. In addition, since the p-channel transistor 79 and the n-channel transistors 80 and 81 are kept in the off state, respectively, the bit line source signal LSY is kept in the high impedance state.

Subsequently, when the transition is made to the period T42 (see FIG. 5), the state signal STT1 becomes L level, so that signals of H level are output from the NAND circuits 64 to 68, respectively, and from the NOR circuit 69. The L level signal is output. Thereby, the bit line source control signals YHE1, YLE1, YHE3B, and YLE2B of H level are output from the NAND-inverter circuits 70 and 72 and the two-stage inverter circuits 73 and 74, respectively, and the NAND-inverter is output. The L-level bit line source control signals YHE0 and YLE0 are output from the circuit 71 and the two-stage inverter circuit 75, respectively. For this reason, the p-channel transistor 76 and the n-channel transistor 78 are turned off, respectively, and the n-channel transistor 77 is turned on, so that the 1 / 3-channel CCC of the n-channel transistor 77 is changed. The bit line source signal HSY continues to be output externally. In addition, since the p-channel transistor 79 and the n-channel transistor 81 are turned off and the n-channel transistor 80 is turned on, the bit line source signal of 1 / 3VCC is transmitted through the n-channel transistor 80. LSY is output externally.

Subsequently, when the transition is made to the period T5 (see FIG. 5), the inverted state signal STT2B becomes H level because the state signal STT2 becomes L level, and thus the L level from the NAND circuit 64 and the NOR circuit 69, respectively. Signal is output, and H level signals are output from the NAND circuits 65 to 68, respectively. Thereby, the L level bit line source control signals YHE1, YHE0, YHE3B, and YLE0 are output from the NAND inverter circuits 70 and 71 and the two stage inverter circuits 73 and 75, respectively, and the NAND inverters are output. From the circuit 72 and the inverter circuit 74 of the two stages, word line source control signals YLE1 and YLE2B of H level are respectively output. For this reason, since the p-channel transistor 76 and the n-channel transistors 77 and 78 are turned off, respectively, the bit line source signal HSY becomes a high impedance state. In addition, since the p-channel transistor 79 and the n-channel transistor 81 are kept in the off state, and the n-channel transistor 80 is in the on state, the bit line of 1/3 VCC is provided through the n-channel transistor 80. The source signal LSY continues to be output externally.

Subsequently, when the transition to the period T61 (see Fig. 5) occurs, the state signal STT3 becomes L level, so that signals of H level are output from the NAND circuits 64 to 68, respectively, and from the NOR circuit 69. The L level signal is output. As a result, the bit line source signal HSY of 1 / 3VCC and the bit line source signal LSY of 1 / 3VCC are output to the outside by the same operation as in the above-described period T42.

Subsequently, when the transition is made to the period T62 (see FIG. 5), the state signal STT4 and the inverted state signal STT4B become L level and H level, respectively, so that the H level signals are respectively supplied from the NAND circuits 64 to 68. In addition to this, an L level signal is output from the NOR circuit 69. As a result, the bit line source signal HSY of 1 / 3VCC and the bit line source signal LSY of 1 / 3VCC are continuously output to the outside.

Finally, when the transition to the period T0 (see Fig. 5) is made again, the state signal STT5 and the inverted state signal STT5B become L level and H level, respectively, so that the state signals STT1 and 3 to 5 become L level, respectively. , The inverted state signals STT2B, 4B, and 5B become H levels, respectively. As a result, the bit line source signal HSY and the bit line source signal LSY of VSS are output to the outside by the same operation as the first period T0 described above.

With reference to FIG. 17, the structure of the sense amplifier 14 supplied with the bit line source signals HSY and LSY from the bit line source driver 13 is demonstrated. The sense amplifier 14 according to the first embodiment amplifies the voltage corresponding to the data of the memory cell read out from the bit lines BL (BLT and BLB), and the "H" data ("1") of the read data. Data) or "L" data ("0" data). In addition, the sense amplifier 14 supplies the bit line source signal HSY to the bit line BL that has read the data determined as "H" data, and to the bit line BL which has read the data determined as "L" data. It is configured to supply the bit line source signal LSY.

Specifically, as shown in FIG. 17, the sense amplifier 14 according to the first embodiment includes four p-channel transistors 82 to 85, six n-channel transistors 86 to 91, It consists of an amplifier part 92. Sources of the p-channel transistor 82 and the transistor 84 are supplied with the bit line source signal HSY from the bit line source driver 13 (see FIGS. 1 and 16), respectively, and the p channel transistors 83 and 85. The bit line source signal LSY is supplied from the bit line source driver 13 (refer to FIG. 1 and FIG. 16), respectively. The drains of the p-channel transistors 82 and 83 are connected to the bit lines BLT, respectively, while the drains of the p-channel transistors 84 and 85 are connected to the bit lines BLB, respectively. The gates of the p-channel transistors 82 to 85 are connected to the amplifier sections 92, respectively.

The bit line source signal HSY is supplied to the drains of the n channel transistors 86 and 88 from the bit line source driver 13, and the bit line source driver is respectively supplied to the drains of the n channel transistors 87 and 89. The bit line source signal LSY is supplied from (13) (see Figs. 1 and 16). The sources of the n channel transistors 86 and 87 are connected to the bit line BLT, respectively, and the sources of the n channel transistors 88 and 89 are connected to the bit line BLB, respectively. The gates of the n-channel transistors 86 to 89 are connected to the amplifier section 92, respectively. In addition, while the drain of the n-channel transistor 90 is connected to the bit line BLT, the source is connected to the amplifier section 92. The drain of the n-channel transistor 91 is connected to the bit line BLB, and the source thereof is connected to the amplifier section 92. The bit line selection signal BLTG is supplied to the gates of the n-channel transistors 90 and 91 from the outside, respectively. The amplifier unit 92 can be configured with various amplifiers such as a cross-coupler amplifier in which a p-channel transistor and an n-channel transistor are cross-coupled, or a current mirror amplifier.

As the operation of the sense amplifier 14, first, in the standby period T0 (see Fig. 5), the p-channel transistors 82 to 85 or the n-channel transistor are controlled by controlling the potential output from the amplifier section 92. (86 to 89) are turned on. As a result, the bit line source signals HSY and LSY of the VSS from the bit line source driver 13 (see FIGS. 1 and 16) are p-channel transistors 82 and 83, or n-channel transistors 86 and 86, respectively. 87) to the bit line BLT. In addition, the bit line source signals HSY and LSY of the VSS from the bit line source driver 13 (see FIGS. 1 and 16) are transmitted through the p-channel transistors 84 and 85 or the n-channel transistors 88 and 89, respectively. It is supplied to the bit line BLB. As a result, in the standby state, the voltages of the bit lines BLT and BLB become VSS. In addition, the bit lines BLT and BLB may be VSS by supplying VSS from a separately provided precharge circuit.

Subsequently, when the operation transitions to the periods T1 to T62 (see FIG. 5), the word line WL (see FIG. 1) rises, whereby the potential corresponding to the data of the memory cell is transferred from the memory cell to the bit lines BLT and BLB. Delivered. At this time, the bit line selection signal BLTG becomes H level. As a result, since the n-channel transistor 90 and the transistor 91 are turned on, the potential corresponding to the data of the memory cell transferred to the bit lines BLT and BLB is determined from the bit lines BLT and BLB, respectively. 90 and the transistor 91 are transferred to the amplifier unit 92. After that, since the n-channel transistors 90 and 91 are turned off by the bit line selection signal BLTG being at the L level, the reverse flow of current from the amplifier section 92 to the bit lines BLT and BLB is suppressed. When the amplifier unit 92 is activated, the voltage of the data of the memory cell is amplified, and the reference potential is compared with the voltage of the data of the amplified memory cell in the amplifier unit 92 to compare the data of the memory cell. Is determined as "H" data ("1" data) or "L" data ("0" data). As a result, the potential of the H level or the L level is supplied from the amplifier unit 92 to the gates of the p-channel transistors 82 to 85 and the n-channel transistors 86 to 89.

When the "H" data is confirmed, the H-level potential is supplied from the amplifier unit 92 to the node ND3, and the L-level potential is supplied to the node ND4. As a result, the p-channel transistors 83 and 84, whose gates are connected to the node ND3, are turned off, and the n-channel transistors 86 and 89 are turned on. The p-channel transistors 82 and 85 whose gates are connected to the node ND4 are turned on while the n-channel transistors 87 and 88 are turned off. As a result, the bit line source signal HSY is supplied to the bit line BLT through the p channel transistor 82 and the n channel transistor 86, and the p channel transistor 85 and the n channel transistor 89 are supplied to the bit line BLB. The bit line source signal LSY is supplied through

On the other hand, when it is determined by the "L" data, the L-level potential is supplied from the amplifier unit 92 to the node ND3, and the H-level potential is supplied to the node ND4. As a result, the p-channel transistors 83 and 84, whose gates are connected to the node ND3, are turned on, and the n-channel transistors 86 and 89 are turned off. Further, the p-channel transistors 82 and transistors 85 whose gates are connected to the node ND4 are turned off, and the n-channel transistors 87 and 88 are turned on. As a result, the bit line source signal LSY is supplied to the bit line BLT through the p channel transistor 83 and the n channel transistor 87, and the p channel transistor 84 and the n channel transistor 88 are supplied to the bit line BLB. The bit line source signal HSY is supplied through Thereby, for the bit lines BLT and BLB ("1" lead BL (BL3 and BL5, "0" lead BL (BL0 to 2, 4, 6 and 7)), VSS is shown in the voltage waveform as shown in FIG. , 1 / 3VCC, 2 / 3VCC and VCC are applied.

(2nd Example)

18, the read operation and the rewrite operation of the memory according to the second embodiment of the present invention will be described.

In the memory according to the second embodiment, unlike the memory according to the first embodiment, the length of each period of the periods T3 and T5, which are periods for rewriting operations, is three times the length of each period of T1 to T22. Is set to. In other words, in the memory according to the second embodiment, the "0" data can be more reliably rewritten in the memory cell of the second cell area (see FIG. 3) in the period of T3, and in the period of T5, The &quot; 1 &quot; data can be more reliably rewritten into the memory cells of the second cell region (see FIG. 3). The other read operation and the rewrite operation of the memory according to the second embodiment are the same as the read operation and the rewrite operation of the memory according to the first embodiment.

Referring to FIG. 19, unlike the state machine circuit 11 according to the first embodiment, the state machine circuit 11 according to the second embodiment includes seven DFF circuits 16a, 16b, 16c, 16d, and 16e. , 16g and 16h). The clock signal CLK and the inverted reset signal RSTB are input to the DFF circuits 16g and 16h, respectively. The output signal from the NOR circuit 31 is input to the input terminal D of the DFF circuit 16g. The count up signal CUP0 is output from the output terminal QT of the DFF circuit 16g, and the inverted count up signal CUP0B, which is an inverted signal of the count up signal CUP0, is output from the output terminal QB. The count up signal CUP0 is input to the NOR circuit 31, and the inverted count up signal CUP0B is input to the NOR circuit 93. In addition, the output signal of the NOR circuit 93 is input to the input terminal D of the DFF circuit 16h. The count up signal CUP1 is output from the output terminal QT of the DFF circuit 16h, and the inverted count up signal CUP1B, which is an inverted signal of the count up signal CUP1, is output from the output terminal QB. The count up signal CUP1 is input to the NOR circuits 31 and 93, while the inverted count up signal CUP1B is input to the OR circuits 28 and 29. The other configuration of the state machine circuit 11 according to the second embodiment is the same as the configuration of the state machine circuit 11 according to the first embodiment. Incidentally, the configuration of portions other than the state machine circuit 11 of the memory according to the second embodiment is the same as that of the memory according to the first embodiment.

18 and 19, the operation of the state machine circuit according to the second embodiment of the present invention will be described. In the state machine circuit 11 according to the second embodiment, in the same manner as the state machine circuit 11 according to the first embodiment, as the clock signal CLK becomes H level in sequence, the state signal of the H level is sequentially. Outputs STT1 to STT4. Then, the state signal STT4 of H level is input to the NAND circuit 25. Since the inverted state signal STT5B of high level is input from the DFF circuit 16e to the NAND circuit 25, the low level signal is input from the NAND circuit 25 to the OR circuit 29. Since the H level inversion count up signal CUP1B is input to the OR circuit 29 from the DFF circuit 16h, the H level signal is input from the OR circuit 29 to the NAND circuit 27. On the other hand, the inverted state signal STT4B of L level is input to the NAND circuit 26 from the DFF circuit 16d. In addition, since the L-level state signal STT5 is input from the DFF circuit 16e to the NAND circuit 26, the H-level signal is input from the NAND circuit 26 to the NAND circuit 27. As a result, an L-level signal is input from the NAND circuit 27 to the selector circuit 19, so that the input of the selector circuit 19 is held toward the "0" side. For this reason, the L-level state signal STT5 output from the DFF circuit 16e is supplied to the DFF circuit 16e via the selector circuit 19. As a result, the state signal STT5 output from the DFF circuit 16e is maintained at the L level even when the clock signal CLK input to the DFF circuit 16e is subsequently lowered to the L level and then rises to the H level.

The L level signal output from the NAND circuit 25 is also input to the AND circuit 30. In addition, since the H level signal is input from the NAND circuit 23 to the AND circuit 30, the L level signal is input from the AND circuit 30 to the NOR circuit 31. In addition, since the L level count up signal CUP0 is input to the NOR circuit 31 from the DFF circuit 16g, and the L level count up signal CUP1 is input from the DFF circuit 16h, the NOR circuit ( The H level signal is input from the 31 to the DFF circuit 16g. As a result, the H-level clock signal CLK when the state signal STT5 is maintained at the L level is input to the DFF circuit 16g, whereby the count-up signal CUP0 at the H level and the L-level are supplied from the DFF circuit 16g. The level inversion count up signal CUP0B is output.

The L level inversion count up signal CUP0B is input to the NOR circuit 93. Since the L level count-up signal CUP1 is input to the NOR circuit 93 from the DFF circuit 16h, the H level signal is input to the DFF circuit 16h from the NOR circuit 93. As a result, the clock signal CLK input to the DFF circuit 16h falls to the L level and then rises to the H level, thereby inverting the count-up signal CUP1 of the H level and the L level from the DFF circuit 16h. The count up signal CUP1B is output.

The L level inversion count up signal CUP1B is input to the OR circuit 29. Since the L level signal is input from the NAND circuit 25 to the OR circuit 29, the L level signal is input from the OR circuit 29 to the NAND circuit 27. Since the H level signal is input from the NAND circuit 26 to the NAND circuit 27, the H level signal is input from the NAND circuit 27 to the selector circuit 19. Thereby, since the input of the selector circuit 19 switches to the "1" side, the inverted state signal STT5B of H level output from the DFF circuit 16e is supplied to the DFF circuit 16e via the selector circuit 19. For this reason, after the clock signal CLK input to the DFF circuit 16e falls to L level, and then raises to H level, the state signal STT5 of H level and the L level are inverted from the DFF circuit 16e. The state signal STT5B is output. In this way, the rise of the state signal STT5 to the H level is delayed for three periods of the clock signal CLK of the three H levels from the rise of the state signal STT4 to the H level.

Thereafter, similarly to the state machine circuit 11 according to the first embodiment, as the clock signal CLK gradually goes to the H level, the state signals STT1 and STT2 fall to the L level sequentially. After the high-level state signal STT4 is output, the high-level state signal STT5 is output in accordance with the third high-level clock signal, thereby operating the low-level from the DFF circuit 16b. After the state signal STT2 is outputted, the L-state state signal STT3 is output from the DFF circuit 16c in accordance with the third H-level clock signal CLK. Thereby, the fall to the L level of the state signal STT3 is delayed for three periods of the clock signal CLK of three H levels from the fall to the L level of the state signal STT2.

Thereafter, similarly to the state machine circuit 11 according to the first embodiment, as the clock signal CLK gradually goes to the H level, the state signals STT4 and STT5 fall to the L level sequentially.

As described above, since the delay amount of the rise of the state signal STT5 is three clock periods, the delay amount of the rise of the state signals STT5 is three times the delay amount of the one clock period of the rise of the state signals STT2 to STT4. Thus, the length of the period T3 for the rewrite operation set by the period from the rise of the state signal STT4 to the rise of the state signal STT5 is the period T1 corresponding to the interval of the timing at which each of the state signals STT1 and STT2 rises. The period T21 corresponds to the interval of the timing at which each of the state signals STT2 and STT3 rises, and the length is three times the length of each of the period T22 corresponding to the interval of the timing at which the state signals STT3 and STT4 respectively rise. Since the delay amount of the degradation of the state signal STT3 is three clock periods, the delay amount of the degradation of the state signals STT3 is three times the delay amount of one clock period of the degradation of the state signals STT2 to STT4. As a result, the length of the period T5 for the rewrite operation set by the period from the decrease of the state signal STT2 to the decrease of the state signal STT3 is equal to the period T1 corresponding to the interval of the timing at which each of the state signals STT1 and STT2 rises. The period T21 corresponds to the interval of the timing at which the state signals STT2 and STT3 respectively rise, and the length is three times the length of each of the period T22 corresponding to the interval of the timing at which the state signals STT3 and STT4 respectively rise.

In the second embodiment, as described above, the lengths of the periods T3 and T5 for the rewrite operation are made three times the length of each of the periods T1 to T22, so that the memory read and rewrite operations are performed. In order to speed up, when the pulse width of the clock signal CLK for generating each period of T1 to T62 is made small, even when the length of each period of T1 to T62 is shortened, A period of length necessary for rewriting to the memory cell can be ensured. This makes it possible to reliably rewrite data to the memory cells of the second cell region while speeding up the operation of the memory.

Effects other than the above according to the second embodiment are the same as the effects according to the first embodiment.

(Third Embodiment)

20, a read operation and a rewrite operation of the memory according to the third embodiment of the present invention will be described.

In the memory according to the third embodiment, as shown in Fig. 20, unlike the memory according to the first embodiment, the lengths of the respective periods of T3 and T5, which are periods for the rewrite operation, are each of T1 to T22. The length is set to four times the length of the period. That is, in the memory according to the third embodiment, "0" data can be more reliably rewritten in the memory cell of the second cell region (see FIG. 3) in the period of T3, and the second in the period of T5. The &quot; 1 &quot; data can be more reliably rewritten into the memory cells of the cell region (see FIG. 3). The other read operation and rewrite operation of the memory according to the third embodiment are the same as the read operation and the rewrite operation of the memory according to the first embodiment.

Referring to FIG. 21, unlike the state machine circuit 11 according to the first embodiment, the state machine circuit 11 according to the third embodiment includes seven DFF circuits 16a, 16b, 16c, 16d, and 16e. , 16i and 16j). The clock signal CLK and the inverted reset signal RSTB are input to the DFF circuits 16i and 16j, respectively. The output signal from the NOR circuit 31 is input to the input terminal D of the DFF circuit 16i. The count up signal CUP0 is output from the output terminal QT of the DFF circuit 16i. The count up signal CUP0 is input to the NAND circuit 95 and the selector circuit 94. The output signal of the selector circuit 94 is also input to the input terminal D of the DFF circuit 16j. The count up signal CUP1 is output from the output terminal QT of the DFF circuit 16j, and the inverted count up signal CUP1B, which is an inverted signal of the count up signal CUP1, is output from the output terminal QB. The count up signal CUP1 is input to the "0" side of the NAND circuit 95 and the selector circuit 94, and the inverted count up signal CUP1B is input to the "1" side of the selector circuit 94. In addition, the inversion count up signal CUPB is output from the NAND circuit 95. This inversion count up signal CUPB is input to the OR circuits 28 and 29. The other configuration of the state machine circuit 11 according to the third embodiment is the same as the configuration of the state machine circuit 11 according to the first embodiment.

20 and 21, the operation of the state machine circuit according to the third embodiment of the present invention will be described. In the state machine circuit 11 according to the third embodiment, in the same manner as the state machine circuit 11 according to the first embodiment, as the clock signal CLK becomes H level in sequence, the state signal of the H level is sequentially. STT1 to STT4 are output. In the period until the state signal STT4 rises to the H level, all signals input from the NAND circuit 23 and the NAND circuit 25 to the AND circuit 30 are held at the H level. As a result, the H level signal is input from the AND circuit 30 to the NOR circuit 31. Since the L level count up signal CUP0 is input to the NOR circuit 31 from the DFF circuit 16i, the count up signal CUP0 output from the DFF circuit 16i is maintained at the L level. And the count-up signal CUP0 of the L level is input to the selector circuit 94, so that the input of the selector circuit 94 is held to the "0" side. As a result, the L-level count-up signal CUP1 output from the DFF circuit 16j is supplied to the DFF circuit 16j through the selector circuit 94, so that the count-up signal CUP1 output from the DFF circuit 16j is L. Is maintained at the level. For this reason, the L level count up signal CUP0 is input to the NAND circuit 95 from the DFF circuit 16i and the L level count up signal CUP1 is input from the DFF circuit 16j, so that the state signal STT4 is H level. In the period up to the rise, the count up signal CUPB output from the NAND circuit 95 is maintained at the H level. Since the count-up signal CUPB of the H level is input to the OR circuit 29, it is output from the DFF circuit 16e in the same manner as in the first embodiment in the period until the state signal STT4 rises to the H level. The state signal STT5 is kept at the L level.

Then, when the state signal STT4 rises to the high level, the high level state signal STT4 and the high level inverted state signal STT5B are inputted to the NAND circuit 25 to output the low level signal from the NAND circuit 25. . As a result, an L level signal is input from the NAND circuit 25 to the AND circuit 30, and an H level signal is input from the NAND circuit 23, thereby inputting the NOR circuit 31 from the AND circuit 30 to the NOR circuit 31. The L level signal is input. In addition, since the L level count-up signal CUP0 is input to the NOR circuit 31 from the DFF circuit 16i, the H level signal is input from the NOR circuit 31 to the DFF circuit 16i. Thereby, after the clock signal CLK input to the DFF circuit 16i falls to L level, it raises to H level, and the count-up signal CUP0 of H level is output from the DFF circuit 16i.

The count-up signal CUP0 of the H level is input to the selector circuit 94, so that the input of the selector circuit 94 switches to the &quot; 1 &quot; side. As a result, the H level inversion count up signal CUP1B output from the DFF circuit 16j is supplied to the DFF circuit 16j via the selector circuit 94. For this reason, after the clock signal CLK input to the DFF circuit 16j falls to L level, it raises to H level, and the count-up signal CUP1 of H level is output from the DFF circuit 16j. The H-up count-up signal CUP0 is also input to the NOR circuit 31. Since the L level signal is input from the AND circuit 30 to the NOR circuit 31, the L level signal is input from the NOR circuit 31 to the DFF circuit 16i. As a result, the L level count up signal CUP0 is output from the DFF circuit 16i by the H level clock signal CLK which is the same as the H level count up signal CUP1 is output from the DFF circuit 16j. As a result, the H-level count-up signal CUP1 and the L-level count-up signal CUP0 are input to the NAND circuit 95, so that the inverted count-up signal CUPB output from the NAND circuit 95 is maintained at the H level.

The count-up signal CUP0 of the L level is input to the NOR circuit 31. Since the L level signal is input from the AND circuit 30 to the NOR circuit 31, the H level signal is input from the NOR circuit 31 to the DFF circuit 16i. Thereby, after the clock signal CLK input to the DFF circuit 16i falls to L level, it raises to H level, and the count-up signal CUP0 of H level is output from the DFF circuit 16i. At this time, since the count-up signal CUP1 output from the DFF circuit 16j is held at the H level, the inverted count-up signal CUPB at the L level is supplied from the NAND circuit 95 to which the count-up signals CUP0 and CUP1 of the H level are input. Is output.

The L level inversion count up signal CUPB is input to the OR circuit 29. Since the L level signal is input from the NAND circuit 25 to the OR circuit 29, the L level signal is input from the OR circuit 29 to the NAND circuit 27. In addition, since the H level signal is input from the NAND circuit 26 to the NAND circuit 27, the H level signal is input from the NAND circuit 27 to the selector circuit 19. Thereby, the input of the selector circuit 19 switches to the "1" side. For this reason, the H level inverted state signal STT5B output from the DFF circuit 16e is supplied to the DFF circuit 16e via the selector circuit 19. For this reason, after the clock signal CLK input to the DFF circuit 16e falls to L level, it raises to H level, and the state signal STT5 of H level is output from the DFF circuit 16e. In this way, the rise of the state signal STT5 to the H level is delayed by the clock signal CLK of the four H levels from the rise of the state signal STT4 to the H level.

Thereafter, similarly to the state machine circuit 11 according to the first embodiment, as the clock signal CLK gradually goes to the H level, the state signals STT1 and STT2 fall to the L level sequentially. Then, as described above, after the high-level state signal STT4 is output, in accordance with the fourth high-level clock signal, the high-level state signal STT5 is output from the DFF circuit 16b by the same operation. After the low-level state signal STT2 is output, the low-level state signal STT3 is output in accordance with the fourth H-level clock signal CLK. Thereby, the fall to the L level of the state signal STT3 is delayed four times of the clock signal CLK of H level from the fall to the L level of the state signal STT2.

Thereafter, similarly to the state machine circuit 11 according to the first embodiment, as the clock signal CLK is sequentially raised to the H level, the state signals STT4 and STT5 are sequentially lowered to the L level.

As described above, since the delay amount of the rise of the state signal STT5 is for four clock periods, the delay amount of the rise of the state signals STT5 is four times the delay amount for the one clock period of the rise of the state signals STT2 to STT4. . Thus, the length of the period T3 for the rewrite operation set by the period from the rise of the state signal STT4 to the rise of the state signal STT5 is the period T1 corresponding to the interval of the timing at which each of the state signals STT1 and STT2 rises. The period T21 corresponds to the interval of the timing when each of the signals STT2 and STT3 rises, and the length of four times the length of each of the period T22 corresponding to the interval of the timing when the state signals STT3 and STT4 respectively rise. Since the delay amount of the degradation of the state signal STT3 is for four clock periods, the delay amount of the degradation of the state signals STT3 is four times the delay amount for the one clock period of the degradation of the state signals STT2 to STT4. As a result, the length of the period T5 for the rewrite operation set by the period from the decrease of the state signal STT2 to the decrease of the state signal STT3 is equal to the period T1 corresponding to the interval of the timing at which each of the state signals STT1 and STT2 rises. The period T21 corresponds to the interval of the timing at which each of the state signals STT2 and STT3 rises, and the length is four times the length of each of the period T22 corresponding to the interval of the timing at which the state signals STT3 and STT4 respectively rise.

In the third embodiment, as described above, the lengths of the periods T3 and T5 for the rewrite operation are made four times the length of each of the periods T1 to T22, so that the memory read and write operations are performed. In order to speed up, when the pulse width of the clock signal CLK for generating each period of T1 to T62 is made small, even when the length of each period of T1 to T62 is shortened, A period of length necessary for rewriting to the memory cell can be ensured. This makes it possible to reliably rewrite data to the memory cells of the second cell region while speeding up the operation of the memory.

Effects other than the above according to the third embodiment are the same as the effects according to the first embodiment.

In addition, it is thought that the Example disclosed this time is not restrictive as an illustration in all the points. The scope of the present invention is described not by the description of the above-described embodiments, but by the claims, and includes all modifications within the meaning and range equivalent to those of the claims.

For example, in the above embodiment, when the rewrite operation is performed, the bit line BL is raised in stages before the word line WL is raised. However, the present invention is not limited to this, and the bit line BL is raised. The word line WL may be raised in stages prior to making it.

Incidentally, in the above embodiment, the bit lines BL are raised in two steps of 1/3 VCC, but the present invention is not limited to this, but may be made up in three or more steps of 1/3 VCC or less. The bit line BL may be gradually raised smoothly. Even when the bit line BL is raised in this manner, the same effects as in the above embodiment can be obtained.

Further, in the above embodiment, the lengths of the periods of T3 and T5 for the rewrite operation are set to be longer than the lengths of the respective periods of T1 to T22. However, the present invention is not limited to this, and the The length of the periods of T3 and T5 may be set to be substantially the same as the length of each period of T1 to T22. 22 is a voltage waveform diagram showing a method of applying a voltage to word lines WL and bit lines BL of a memory according to a modification of the present invention. Fig. 23 is a voltage waveform diagram of an internal signal used to supply voltage to word lines WL and bit lines BL of a memory according to a modification of the present invention. In the memory voltage application method according to this modification, as shown in Fig. 22, the lengths of the periods of T3 and T5 for the rewrite operation are set to be the same lengths as the lengths of the respective periods of T1 to T22. . As a result, as shown in FIG. 23, each internal signal (state signals STT1 to 5, word line source control signals XSE3B to 0, XUE2B to 0, and bits used to apply voltages to the word lines WL and bit lines BL). The lengths of the periods T3 and T5 in the line source control signals YHE3B to 0 and YLE2B to 0 are also set to the same lengths as the lengths of the respective periods of the corresponding T1 to T22. The configuration other than the above in the method of applying the voltage of the memory according to the modification of the present invention is the same as the configuration according to the first embodiment.

In the memory according to the modification of the present invention, as described above, the &quot; 0 &quot; read bit lines BL (BL0 to 2, 4, 6, and 7) (see Fig. 3) are raised in steps of 1/3 VCC in steps of 1/3. When the rewrite operation is performed, the &quot; 0 &quot; read bit line BL (BL0 to &lt; RTI ID = 0.0 &gt; BL0 &lt; / RTI &gt; Since the potential difference with 2, 4, 6, and 7) can be suppressed from being larger than 1/3 VCC, the disturbance phenomenon is caused by the potential difference larger than 1/3 VCC being applied to the memory cell in the first cell region that is not rewritten. This can be suppressed from occurring.

FIG. 24 is a circuit diagram showing the configuration of the state machine circuit 11 for generating the state signals STT1 to 5 of the memory according to the modification of the present invention shown in FIG. The state machine circuit 11 according to this modification has the configuration of a 5-bit Johnson counter of clock synchronization. Specifically, as shown in FIG. 24, the state machine circuit 11 includes five DFF circuits 16a to 16e, one selector circuit 17, and two NAND circuits 20 and 21. ).

The clock signal CLK and the inverted reset signal RSTB are supplied to the DFF circuits 16a to 16e, respectively. The inversion reset signal RSTB is input from an input terminal / R of the DFF circuits 16a to 16e. The output signal of the selector circuit 17 is input to the input terminal D of the DFF circuit 16a. The state signal STT1 is output from the output terminal QT of the DFF circuit 16a. The state signal STT1 is input to the "0" side of the selector circuit, the NAND circuit 20 and the DFF circuit 16b of the next stage. Similarly, state signals STT1 to 4 of the DFF circuit of the previous stage are input to the DFF circuit of the rear stage, respectively, over the DFF circuits 16b to 16e. The state signal STT5 output from the DFF circuit 16e is input to the NAND circuit 20. In addition, from the output terminal QB of each of the DFF circuits 16a to 16e, inverted state signals STT1B to STT5B, which are inverted signals of the state signals STT1 to STT5 output from the output terminal QT, are externally output. The inverted state signal STT1B output from the output terminal QB of the DFF circuit 16a is input to the "1" side of the selector circuit 17. The NAND circuit 21 is input with an inverted chip select signal CSB supplied from the outside and an output of the NAND circuit 20. The output of the NAND circuit 21 is input to the selector circuit 17.

As the operation of the state machine circuit 11 according to this modification, the state signal STT1 output from the DFF circuits 16a to 16e is first input by inputting the L level inversion reset signal RSTB to the DFF circuits 16a to 16e. 5 becomes L level at all. At this time, the L-level state signals STT1 and STT5 are input to the NAND circuit 20, so that the H-level signal is input from the NAND circuit 20 to the NAND circuit 21. In this state, when the H level inverting chip select signal CSB is input to the NAND circuit 21, the L level signal is input from the NAND circuit 21 to the selector circuit 17. Thereby, since the input of the selector circuit 17 turns to the "0" side, the L-level state signal STT1 output from the DFF circuit 16a is supplied to the DFF circuit 16a via the selector circuit 17. As a result, the state signal STT1 output from the DFF circuit 16a is maintained at the L level, so the state signal STT2 output from the DFF circuit 16b to which the state signal STT1 is input is maintained at the L level. Thereby, L-level state signals STT3 to 5 are continuously output from the DFF circuits 16c to 16e to which the output signals of the preceding DFF circuits are respectively input.

On the other hand, when the L level inverting chip select signal CSB is input to the NAND circuit 21 while the H level signal is input from the NAND circuit 20 to the NAND circuit 21, the NAND circuit 21 is removed from the NAND circuit 21. An H level signal is input to the selector circuit 17. Thereby, since the input of the selector circuit 17 turns to the "1" side, the inverted state signal STT1B of H level output from the DFF circuit 16a is supplied to the DFF circuit 16a via the selector circuit 17.

Subsequently, the clock signal CLK becomes H level, so that the state signal STT1 output from the DFF circuit 16a becomes H level. On the other hand, the state signals STT2 to 5 output from the DFF circuits 16b to 16e are maintained at the L level. In addition, the H-level state signal STT1 output from the DFF circuit 16a is input to the DFF circuit 16b at a later stage. In addition, the H-level state signal STT1 output from the DFF circuit 16a is input to the NAND circuit 20. As a result, the H level signal is input from the NAND circuit 20 to the NAND circuit 21. At this time, since the inverting chip select signal CSB input to the NAND circuit 21 is maintained at the H level, the signal input to the selector circuit 17 from the NAND circuit 21 is maintained at the L level. As a result, since the input of the selector circuit 17 is held at the "0" side, the state signal STT1 of the H level of the DFF circuit 16a is inputted to the DFF circuit 16a through the selector circuit 17, whereby the DFF circuit ( From 16a), the state signal STT1 of H level is continuously output.

Subsequently, the clock signal CLK becomes H level again, so that the state signal STT2 output from the DFF circuit 16b becomes H level. At this time, the state signal STT1 output from the DFF circuit 16a is maintained at the H level, while the state signals STT3 to 5 output from the DFF circuits 16c to 16e are maintained at the L level. Then, by the same operation, the clock signals CLK are sequentially brought to the H level, so that the state signals STT3 to 5 outputted from the DFF circuits 16c to 16e are sequentially turned to the H level. After that, the clock signals CLK are sequentially brought to the H level by the same operation as described above, so that the state signals STT1 to 5 are sequentially turned from the H level to the L level.

In the first to third embodiments, the state machine circuit is configured to delay the rise of the state signal STT5 and the decrease of the state signal STT3 by 2 to 4 clock periods, but the present invention is not limited to this. The state machine circuit may be configured to delay the rise of the state signal STT5 and the decrease of the state signal STT3 for at least five clock periods. For example, by increasing the number of stages of the DFF circuits 16g and 16h of the state machine circuit 11 (see FIG. 19) according to the second embodiment, and adding an appropriate logic circuit, the H level is increased. By delaying the timing at which the inversion count-up signal CUP1B is outputted, the rise of the state signal STT5 and the fall of the state signal STT3 can be delayed for at least five clock periods.

In the above embodiment, the case where the voltage of the VCC used in the read operation and the voltage of the VCC used in the rewrite operation are the same is described as an example, but the present invention is not limited to this, and the read operation The voltage of the VCC used at the time and the voltage of the VCC used at the rewrite operation may be configured differently. For example, the voltage of the VCC at the read operation may be set to about 3.3 V, and the voltage at the VCC at the rewrite operation may be set to about 3.0 V. FIG. In this case, the voltage of 1/3 VCC in the read operation is about 1.1 V, and the voltage of 1/3 VCC in the rewrite operation is about 1.0 V.

As described above, according to the present invention, a memory capable of suppressing the disturb phenomenon can be provided.

Claims (26)

Bit line, A word line arranged to intersect the bit line; Storage means including a ferroelectric capacitor connected between the bit line and the word line, When a read operation is performed on the selected storage means connected to the selected word line, and then a rewrite operation is performed on at least part of the selected storage means, the selected word line corresponds to the selected word line and the non-rewritten storage means. The length of the period in which each of the bit lines are raised while maintaining the potential difference of each other below a predetermined value, and a voltage for rewriting is applied to each of the selected word lines and the bit lines corresponding to the rewritten memory means is set. And a control circuit which is different from the length of the transition period of at least one of the potentials of the word line and the bit line corresponding to the non-rewritten storage means. The method of claim 1, And the length of the period for applying the voltage is longer than the length of the transition period of at least one of the potentials of the word line and the bit line corresponding to the non-rewritten storage means. The method of claim 1, The rewrite operation is made of a plurality of operations, The electric field in the first direction is applied to the non-selected storage means that is at least a storage means other than the selected storage means through a read operation performed on the selected storage means connected to the selected word line and a rewrite operation composed of a plurality of operations. And a voltage for supplying the same voltage and a voltage for supplying an electric field in the first direction and an inverse direction, respectively. The method of claim 1, At least one of the selected word line and a bit line corresponding to the non-rewritten storage means gradually rises to a voltage applied to the non-rewritten storage means. The method of claim 4, wherein At least one of the selected word line and a bit line corresponding to the non-rewritable storage means rises stepwise by 1/3 or less of the potential difference applied to the rewritten memory means. The method of claim 1, The bit line corresponding to the non-rewritten storage means rises while maintaining the potential difference with the word line below a predetermined potential difference at a voltage applied to the non-rewritten storage means before the selected word line rises. Memory. The method of claim 6, The bit line corresponding to the non-rewritten storage means rises by 1/3 of the potential difference applied to the rewritten memory means as the first step, and thereafter, as the second step, the rewritten memory means A memory that rises by one third of the potential difference applied to it. The method of claim 7, wherein When the bit line corresponding to the non-rewritten memory means rises by 1/3 of the potential difference applied to the rewritten memory means as the first step, the selected word line is also written to the rewritten memory means. A memory to which a voltage of 1/3 of an applied potential difference is applied. The method of claim 1, And the storage means has a ferroelectric film disposed between the word line and the bit line at a position where the word line and the bit line intersect. Bit line, A word line arranged to intersect the bit line; Storage means including a ferroelectric capacitor connected between the bit line and the word line, When a read operation is performed on the selected storage means connected to the selected word line, and then a rewrite operation is performed on at least part of the selected storage means, the selected word line corresponds to the selected word line and the non-rewritten storage means. Each of the bit lines is raised while maintaining the potential difference with each other below a predetermined value, and at least one of the bit lines corresponding to the selected word line and the non-rewritten memory means is rewritten. And a control circuit for raising stepwise by 1/3 of the potential difference applied thereto. The method of claim 10, The bit line corresponding to the non-rewritten storage means rises while maintaining the potential difference with the word line below a predetermined potential difference at a voltage applied to the non-rewritten storage means before the selected word line rises. Memory. The method of claim 11, The bit line corresponding to the non-rewritten storage means rises by 1/3 of the potential difference applied to the rewritten memory means as the first step, and then as the second step, the bit line corresponding to the rewritten memory means. Memory that rises by 1/3 of the applied potential difference. The method of claim 12, When the bit line corresponding to the non-rewritten memory means rises by 1/3 of the potential difference applied to the rewritten memory means as the first step, the selected word line is also written to the rewritten memory means. A memory to which a voltage of 1/3 of an applied potential difference is applied. The method of claim 10, And the storage means has a ferroelectric film disposed between the word line and the bit line at a position where the word line and the bit line intersect. Bit line, A word line arranged to intersect the bit line; Storage means including a ferroelectric capacitor connected between the bit line and the word line; When a read operation is performed on the selected storage means connected to the selected word line, and then a rewrite operation is performed on at least part of the selected storage means, the selected word line corresponds to the selected word line and the non-rewritten storage means. The length of the period in which each of the bit lines are raised while maintaining the potential difference of each other below a predetermined value, and a voltage for rewriting is applied to each of the selected word lines and the bit lines corresponding to the rewritten memory means is set. And a control circuit for varying the length of the transition period of at least one of the potentials of the word line and the bit line corresponding to the non-rewritten storage means. The method of claim 15, The control circuit includes, in response to a clock signal, a first signal for setting a start point and an end point of a transition period of at least one of the potential of the word line and a bit line corresponding to the non-rewritten storage means; And a clock control circuit section for generating a second signal for setting a start point and an end point of a period in which a voltage for rewriting is applied to each of the selected word line and the bit line corresponding to the rewritten memory means. The method of claim 15, The control circuit includes a first signal for setting a start point and an end point of a transition period of at least one of the potentials of the word line and the bit line corresponding to the non-rewritten storage means, the selected word line and the rewrite. And a delay circuit section for generating a second signal for setting a start point and an end point of a period for applying a voltage for rewriting to each bit line corresponding to the memory means to be written. The method of claim 15, And the length of the period for applying the voltage is longer than the length of the transition period of at least one of the potentials of the word line and the bit line corresponding to the non-rewritten storage means. The method of claim 15, The rewrite operation is made of a plurality of operations, The electric field in the first direction is applied to the non-selected storage means that is at least a storage means other than the selected storage means through a read operation performed on the selected storage means connected to the selected word line and a rewrite operation composed of a plurality of operations. And a voltage for supplying the same voltage and a voltage for supplying an electric field in the first direction and an inverse direction, respectively. The method of claim 15, At least one of the selected word line and a bit line corresponding to the non-rewritten storage means gradually rises to a voltage applied to the non-rewritten storage means. The method of claim 20, At least one of the selected word line and a bit line corresponding to the non-rewritable storage means rises stepwise by 1/3 or less of the potential difference applied to the rewritten memory means. The method of claim 15, The bit line corresponding to the non-rewritten storage means rises while maintaining the potential difference with the word line below a predetermined potential difference at a voltage applied to the non-rewritten storage means before the selected word line rises. Memory. The method of claim 22, The bit line corresponding to the non-rewritten storage means rises by 1/3 of the potential difference applied to the rewritten memory means as the first step, and then applied to the rewritten memory means as the second step. Memory that rises by 1/3 of the potential difference. The method of claim 23, wherein When the bit line corresponding to the non-rewritten memory means rises by 1/3 of the potential difference applied to the rewritten memory means as the first step, the selected word line is also written to the rewritten memory means. A memory to which a voltage of 1/3 of an applied potential difference is applied. The method of claim 15, And the storage means has a ferroelectric film disposed between the word line and the bit line at a position where the word line and the bit line intersect. Bit line, A word line arranged to intersect the bit line; Storage means including a ferroelectric capacitor connected between the bit line and the word line, When a read operation is performed on the selected storage means connected to the selected word line, and then a rewrite operation is performed on at least part of the selected storage means, the selected word line corresponds to the selected word line and the non-rewritten storage means. The length of a period in which each of the bit lines is raised while maintaining the potential difference between each other below a predetermined value, and a voltage for rewriting is applied to each of the selected word lines and bit lines corresponding to the rewritten memory means. And a control circuit which differs from the length of the transition period of the potential difference when raising the potential difference while maintaining the potential difference with each other below a predetermined value.

Images