KR100610167B1 - Apparatus and Method of Pulse Density Modulation Using Improved Phase Transformation - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse density modulator and a pulse density modulation method, and in particular, to improve the phase shift method, to realize a simple hardware complexity by adding a pattern symbol generator, and to uniformly distribute 0 or 1 to output after modulation. The present invention relates to a pulse density modulator and a pulse density modulation method for reducing noise in the processing of.

Pulse Density Modulation (PDM), DAC,

Description

{Apparatus and Method of Pulse Density Modulation Using Improved Phase Transformation}             

1 illustrates an apparatus for converting a digital signal into an analog signal using pulse density modulation;

FIG. 2 illustrates an apparatus for converting a digital input signal into a pulse density modulation (PDM) signal through a reference table; FIG.

FIG. 3 is a diagram illustrating an apparatus for generating a PDM signal by comparing an input digital signal with a value of a linear transformed counter through a comparator. FIG.

4 is a diagram illustrating a pulse density modulator using phase shift as an embodiment of the present invention;

5 is a flowchart illustrating a pulse density modulation method using phase shift as an embodiment of the present invention;

FIG. 6A shows a comparison between the PDM of the present invention and the prior art PDM technique when the input value S is 34, and

FIG. 6B shows a comparison of the PDM of the present invention and the PDM technique of the prior art when the input value S is 50. FIG.

 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse density modulator and a pulse density modulation method, and in particular, to improve the phase shift method, to realize a simple hardware complexity by adding a pattern symbol generator, and to uniformly distribute 0 or 1 to output after modulation. The present invention relates to a pulse density modulator and a pulse density modulation method for reducing noise in the processing of.

Pulse Density Modulation (PDM) is a type of pulse modulation that modulates the number of pulses of a certain unit of amplitude or width within a certain time period and modulates it according to the size of the modulation signal. Digital-to-Analog Converter for Automatic Frequency Control (AFC) and Automatic Gain Control (AGC) for all mobile communication devices, including code division multiple access (CDMA) devices It is used for analog-to-digital (ADC) and DACs in many devices, including multiple media.

1 is a diagram illustrating an apparatus for converting a digital signal using pulse density modulation into an analog signal. A DAC using a pulse density modulator converts an input digital signal into a PDM signal through the PDM 101 as shown in FIG. The PDM signal generated by 100 is converted into an analog signal through a low-pass filter 102 and used according to the purpose. The PDM converts a multi-bit digital value to one bit of '1' and '0'. It is expressed by the density of high voltage (VH) and low voltage (VL) expressed by, and the method of converting input digital signal into PDM signal is using look-up table, linear conversion of counter value and digital input. There is a method of using the result of comparing the values as a PDM signal. The PDM switching method will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a diagram illustrating an apparatus for converting a digital input signal into a PDM signal through a reference table, and generates a PDM signal corresponding to the value of the reference table 200 one-to-one according to the incoming digital input and the value of the counter 202. In this way, the size of the reference table 200 increases in a situation where a large number of bits are required due to an increase in the required resolution, and the complexity of hardware increases exponentially.

FIG. 3 is a diagram illustrating an apparatus for generating a PDM signal by comparing an input digital signal with a linear transform 304 and a value of the counter 302 through a comparator 300. The PDM signal generation method using the comparator 300 of the value of 302 and the digital input signal is simple in hardware but increases or decreases the total number of '1' or '0' by one when the digital input is increased or decreased by one. In other words, there is a problem in that the durations of '1' or '0' do not increase or decrease only one by one, but the bits that last one or two or more of the same value are clustered.

Each term used below defines T as one period of PDM bits and N as the number of digital input bits, and each bit is the value maintained for the shortest Ts, which corresponds to the clock period of the PDM generator, and Ts is T /. 2 ^N. A digital input value having an N bit resolution is called S and the PDM bit generated therefrom is called D.

<Table 1> is PDM signal generation method using comparator of linearly converted counter value and digital input signal. When N = 4, PDM output pulse of one period (T) is set to '1' and '0'. Example shown. Each bit in Table 1 shows that when the input value increases or decreases from 8 to 1, the duration of 1 or 0 of the PDM output changes to 3 instead of 2. Elements marked with * show PDM result values whose results of the comparator changed as the input value increased or decreased based on S = 8 corresponding to 2 ^N-1 . As the value of the element marked with * changes, the durations of 1 and 0 respectively increase to 3 along with the PDM values on both the left and right sides.

In the case of the DAC using pulse density modulation, the low frequency filter is converted to analog as shown in FIG. 1, and the low frequency filter of the DAC has a higher noise when the high and low voltages of the PDM signals to be input are not uniformly spread. Generates. In other words, the shorter the duration of '0' and '1', the less noise can be reduced.

In the present invention, in the pulse density modulator and the pulse density modulation method, in particular, the phase shift method is improved, and the pattern symbol generator is added to realize simple hardware complexity, and the 0 or 1 is uniformly distributed and outputted after modulation. The present invention provides a pulse density modulator and a pulse density modulation method for reducing noise in processing.

According to an aspect of the present invention, there is provided a pulse density modulator comprising: a subgroup determiner for obtaining a subgroup decision value (m) and a most significant bit (MSB) according to an input value; A bit selector which selects some bits of the input value for phase shifting of the phase, and a phase selected using the bits selected by the bit selector and the subgroup decision value m and the most significant bit MSB obtained from the subgroup determiner. A phase conversion unit for obtaining a conversion value S ', a counter unit for outputting a counter value by the number of subgroups according to the subgroup determination value m, and a linear conversion unit for linearly receiving the counter value of the counter unit A comparator for comparing the phase shift value S ′ of the phase shifter with the counter-transformed counter value of the linear shifter, an output value of the comparator and an image of the subgroup determiner A pattern symbol generator for outputting a pattern symbol according to a sub-determined value m and the most significant bit MSB, and a PDM bit generator for generating PDM bits according to the pattern symbol output from the pattern symbol generator; A pulse density modulator is provided.

A method of the present invention for achieving the above objects, in the pulse density modulation method in a pulse density modulator, the subgroup determination to obtain the subgroup determination value (m) and the most significant bit (MSB) according to the input value A bit selection step of selecting some bits of the input value for phase shifting of the input value, the bit selected in the bit selection step and the subgroup determination value m obtained from the subgroup determination step and the most significant bit ( A phase shifter for obtaining a phase shift value S 'using MSB), a counter step of outputting a counter value for the number of subgroups according to the subgroup determination value m, and receiving the counter value of the counter step A linear transformation step of performing linear transformation, a comparison step of comparing the phase shift value S ′ of the phase transformation step with the linearly converted counter value of the linear transformation step, the ratio PDM according to the pattern symbol generation step of outputting a pattern symbol according to the output value of the step and the sub-decision value (m) of the subgroup determination step and the most significant bit (MSB) and the pattern symbol output from the pattern symbol generation step A pulse density modulation method of a pulse density modulator including a PDM bit generation step of generating a bit is provided.

In addition, in order to achieve the object of the present invention, it is possible to change the above embodiments, the addition of the configuration and the like. Other embodiments are also possible.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed descriptions of related well-known functions or configurations will be omitted if it is determined that the detailed description may unnecessarily obscure the subject matter of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse density modulator and a pulse density modulation method, and in particular, to improve the phase shift method, to realize a simple hardware complexity by adding a pattern symbol generator, and to uniformly distribute 0 or 1 to output after modulation. The present invention relates to a pulse density modulator and a pulse density modulation method for reducing noise in the processing of.

4 is a diagram illustrating a pulse density modulator using a phase shift according to an embodiment of the present invention, and includes a subgroup determiner 400, a bit selector 402, a phase shifter 404, a counter 406, and a linear converter. 408, comparator 410, pattern symbol generator 412, and PDM bit generator 414.

The subgroup determination unit 400 determines a subgroup determination value m according to an input value and obtains a most significant bit (MSB). The equation for obtaining the subgroup decision value m is shown in Equation 1 below.

M = N when S = 0

When S <2 ^N-1 , S ≠ 2 ^k , S ≠ 0, digit of '1' that comes first after '0' from MSB of S expressed as m = N-1-binary

When S <2 ^N-1 , S = 2 ^k , m = N-digit digit of '1' which comes first after '0' from MSB of S expressed as binary

When S≥2 ^N-1 , S ≠ 2 ^N-1 , digit of '0' that comes first after '1' from MSB of S expressed as m = N-1- binary

When S = 2 ^N-1 , m = N-1

The MSB is the significant digit that most significantly affects the size of the numeric value in bitwise operations. That is, the leftmost bit of the bit of the number, k in Equation 1 is a natural number smaller than N-1.

The bit selector 402 selects bits necessary for phase shift. The bit to select is B, and it is selected using Equation 2 below.

B = From (N-m-2) th digit bit of S to binary bit

(If N-m-2 is less than 1, B = 0.)

The phase shift value S 'which is an input of the comparator 410 obtained through the phase shifter 404 may be obtained as shown in Equation 3 below, and the comparator of the comparator result value of the input value S and the subgroup reference value The number of phase shifts of the comparator result value of S 'and the comparator result value of the subgroup reference value is twice as many as the number of phase shifts of the result value.

When S <2 ^N-1 , S '= {(2 ^Nm-2 -B) × 2}% 2 ^Nm-1

When S≥2 ^N-1 , S '= (B × 2)% 2 ^Nm-1

(If N-m-2 is less than 1, B = 0.)

갈아 나오는 패턴이다.The subgroup reference value is determined according to an input value and a subgroup m determined according to the input value and is obtained as in Equation 4 below, and different symbols having 2 ^m bit widths are burned.

It is a pattern to change.

When S <2 ^N-1 , subgroup reference value = 2 ^Nm-1

2^N-k-1 When S≥2 ^N-1 , subgroup reference value =

2 ^Nk-1

The counter 406 exports a counter value by the number of subgroups 2 ^Nm-1 according to the m value determined by the subgroup determining unit 400, and obtains a C value obtained by linearly converting the counter value by the linear converter 408.

The pattern symbol generator 412 is represented by different symbols having 2 ^m bit widths, and is generated by changing a symbol at a position at which the comparator 410 has a value of '1', that is, a phase shifted.

2ⁿ)혹은 2^N-1에서 순차합을 뺀 값(2^N-1 -

2ⁿ)이 될 때 특정 패턴이 반복된다.Table 2 below shows the PDM bits in which uniform '0' and '1' are generated.

2 ⁿ ) or 2 ^N-1 minus the sequential sum (2 ^N-1-

2 ⁿ ), the specific pattern is repeated.

If the basic factor of the repeating pattern of PDM bits according to each digital input is defined as PDM pattern symbol P, M _m on the right side of Table 2 is a subgroup consisting of these PDM pattern symbols. Is expressed.

As shown in Table 3, when the MSB of S is '0', P ₁ = [1 0 ... 0], P0 = [0 0 ... 0], and MSB is '1'. P ₁ = [1 ... 1 1] and P ₀ = [1 ... 1 0].

The pattern symbol Pi can be obtained as shown in Equation 5 below.

When S <2 ^N-1 , P ₀ = (binary representation of 0) P ₁ = (binary representation of 2 ^m )

When S≥2 ^N-1 , P ₀ = (binary representation of 2 ^{m + 1} ) P ₁ = (representing all 1)

(The width of pattern symbol P _i is 2 ^m )

As an example of the present invention, when m = 0 (2 ^N-2 <S <2 ^N-1 +2 ^N-2 ), that is, when one bit is represented by one symbol, PDM bits are displayed in pairs. PDM bits [0 0] are represented by D ₀₀ , [0 1] by D ₀₁ , [10] by D ₁₀ , and [11] by D _11. That is, PDM bits of input value 2 ^N-1 [1] 0 1 0 1 0 ...] is expressed as [D ₁₀ D ₁₀ D ₁₀ D ₁₀ ...].

When S≥2 ^N-1 , an example of the present invention is 2 ^N-1 +2 ^N-2 (m = 1), that is, when two bits are represented by one symbol, [1 1] is P _1, and [1: 0] is represented as P _0, [P ₀ P _0] to D _00, [P ₀ P _1] is D _01, [P ₁ P _0] is D _10, [P ₁ P _1] to Expressed in D ₁₁ .

That is, input value 2 ^N-1 +2 ^N-2 bits [... 111011101110111011101110 ... 111011101110 ...] is [... P ₁ P ₀ P ₁ P ₀ P ₁ P ₀ P ₁ P ₀ .. P ₁ P ₀ P ₁ P ₀ P ₁ P ₀ ...], which is expressed as [... D ₁₀ D ₁₀ D ₁₀ D ₁₀ ... D ₁₀ D ₁₀ D ₁₀ ...]. .

When S is not 2 ^N-1 and the MSB of S is '1', that is, when S> 2 ^N-1 , the comparator result of the phase shift value S of S is '1', that is, the phase shift is For an odd-numbered phase shift that occurs at D _ij , when m = 0, [... D ^* ₁₀ [D ₁₀ ...]] of the subgroup reference value 2 ^N-1 is [... D ^* ₁₁ [D ₀₁ ...]] and D _10, which lasts until the end of the even phase shift, is changed to D ₀₁ . D ^* _ij is the position at which the phase whose comparator result is '1' is converted. For example, in the case of (2 ^N-1 +1), in the prior art, the PDM bit is expressed as [... D ₁₀ D ^* ₁₁ D ₁₀ D ₁₀ ... D ₁₀ D ₁₀ ...]. ... D ₁₀ D ^* ₁₁ D ₀₁ D ₀₁ ... D ₀₁ D ₁₀ ...] to express.

When the MSB of S is '0', that is, when S <2 ^N-1 , the comparator result of the phase shift value S of S is '1', i.e., for the odd-numbered phase shift in which the phase shift occurs. [... D ^* ₁₀ [D ₁₀ ...]] of the subgroup reference value 2 ^N-1 at m = 0 is changed to [... D ^* ₀₁ [D ₀₁ ...]] Sustained D ₁₀ is changed to D ₀₁ until the even phase shift position and [... D ^* ₁₀ ...] is changed to [... D ^* ₀₀ ...] at the even phase shift position. For example, in the case of (2N-1-1), the PDM bit is expressed as [... D ₁₀ D ^* ₀₀ D ₁₀ D ₁₀ ... D ₁₀ D ₁₀ D ₁₀ ...] in the prior art. Change to [... D ₁₀ D ^* ₁₀ D ₀₁ D ₀₁ ... D ₀₁ D ₀₀ D ₁₀ ...].

The PDM bit generator 414 converts the pattern symbols generated by the pattern symbol generator 412 into PDM bits.

5 is a flowchart illustrating a pulse density modulation method using a phase shift according to an embodiment of the present invention.

If S is 0 in step 500, all PDM bits are output as 0 in step 504. If S is not 0, m value for determining a subgroup is calculated through Equation 1 above.

In step 506, a bit necessary for phase shift is selected through Equation 2, a phase shift value S 'is obtained through Equation 3, and the width and value of the pattern symbol are determined by Equation 5.

In step 508, the sequence phase for checking whether a phase shift has been performed with the counter (counter = 0) is initialized to 0.

In step 508 a check sub-group number 2 ^Nm-1, depending on whether the m value, and if the counter value is 2 ^Nm-1 ends, the counter value is 2 ^Nm-1 or to a linear transformation in step 512.

In the step 514, when the phase shift value S 'is compared with the linearly converted counter value C, and S' is larger, the phase shift occurs. In step 516, the PDM pattern symbol is obtained through Equation 6, and 518 In the step, the sequence phase value that checks whether the odd or even phase shift is inverted is changed to Sequence Phase = 1 when Sequence Phase = 0 and Sequence Phase = 0 when Sequence Phase = 1. That is, if Sequence Phase = 0, it is an odd phase shift, and if Sequence Phase = 1, it is an even phase shift.

If S <2 ^N-1 , Sequence Phase = 0, PDM pattern symbol = P ₀ , P ₁

If S <2 ^N-1 , Sequence Phase = 1, PDM pattern symbol = P ₀ , P ₀

If S≥2 ^N-1 , Sequence Phase = 0, PDM Pattern Symbol = P ₁ , P ₁

If S≥2 ^N-1 , Sequence Phase = 1, PDM Pattern Symbol = P ₁ , P ₀

In the case of S '<C in step 514, the phase shift does not occur. In step 520, the PDM pattern symbol is obtained through Equation (7).

If Sequence Phase = 0, PDM Pattern Symbol = P ₁ , P ₀

If Sequence Phase = 1, PDM Pattern Symbol = P ₀ , P ₁

In step 522, the PDM pattern symbols obtained in steps 516 and 520 are collected in sequence, and the counter value is increased by one. In step 510, the step 522 is repeated until the counter value becomes 2 ^Nm-1 .

6A and 6B illustrate a comparison between the PDM of the present invention and the PDM scheme of the prior art when the input value S is 34 and the input value S is 50, respectively. FIG. 6B shows one period of PDM bits in the frequency domain when the digital input value S is 34,50 at N = 6. 6a and 6b show only up to 1 / Ts (Ts: clock period) for convenience. The bold lines represent the results in the frequency domain of the PDM bits corresponding to the present invention and their cumulative values, and the lines not representing the prior art PDM results using a comparator. In the case of cumulative values, the ratio is scaled down for the sake of convenience, and FIGS. 6A and 6B show a smaller contribution in the low frequency region, as shown in the figure. It can also increase.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

The present invention improves the phase conversion method of the pulse density modulator, adds a pattern symbol generator to realize simple hardware complexity, and distributes 0 or 1 uniformly to output pulse density to reduce noise in the post-modulation process. The present invention relates to a modulator and a pulse density modulation method.

Claims (14)

In pulse density modulator, A subgroup determination unit obtaining a subgroup determination value (m) and a most significant bit (MSB) according to an input value; A bit selector which selects some bits of the input values for phase shifting of the input values; A phase shifter for obtaining a phase shift value S 'using the bit selected by the bit selector and the subgroup decision value m and the most significant bit MSB obtained from the subgroup determiner; A counter unit for outputting a counter value corresponding to the number of subgroups according to the subgroup determination value (m); A linear conversion unit which receives the counter value of the counter unit and performs a linear conversion; A comparison unit comparing the phase shift value S ′ of the phase shift unit with the linearly converted counter value of the linear shift unit; A pattern symbol generator for outputting a pattern symbol according to an output value of the comparator, the sub-determined value m, and the most significant bit MSB of the subgroup determiner; And A pulse density modulator including a PDM bit generator for generating PDM bits according to the pattern symbols output from the pattern symbol generator The method of claim 1, The subgroup determination unit determines the subgroup determination value m according to an input value. The equation for obtaining the subgroup decision value m is as shown in Equation (8) below. M = N when S = 0 When S <2 ^N-1 , S ≠ 2 ^k , S ≠ 0, digit of '1' that comes first after '0' from MSB of S expressed as m = N-1-binary When S <2 ^N-1 , S = 2 ^k , m = N-digit digit of '1' that comes first after '0' from MSB of S expressed as binary When S≥2 ^N-1 , S ≠ 2 ^N-1 , digit of '0' that comes first after '1' from MSB of S expressed as m = N-1- binary When S = 2 ^N-1 , m = N-1 The method of claim 1, And wherein the bit selector selects a bit (B) necessary for phase conversion using Equation (9) below. B = From (N-m-2) th digit bit of S to binary bit (If N-m-2 is less than 1, B = 0.) The method of claim 1, S 'obtained through the phase shift unit is a pulse density modulator, characterized in that obtained by Equation (10) below. When MSB = 0, S '= {(2 ^Nm-2 -B) x 2}% 2 ^Nm-1 When MSB = 1, S '= (B × 2)% 2 ^Nm-1 (If N-m-2 is less than 1, B = 0.) The method of claim 1, The comparison result of the comparison unit of the phase change value (S ') and the linearly converted counter value (C) of the linear conversion unit, the phase change value (S') is a linear conversion of the linear conversion unit counter value (C) The pulse density modulator, characterized in that the larger the phase change occurs when the comparison unit outputs a '1'. The method of claim 1, The pattern symbol generation unit generates a PDM pattern symbol through Equation 11 below. If S '> C, MSB = 0, Sequence Phase = 0, PDM pattern symbol = P ₀ , P ₁ S '> C, MSB = 0, Sequence Phase = 1, PDM Pattern Symbol = P ₀ , P ₀ S '> C, MSB = 1, Sequence Phase = 0, PDM Pattern Symbol = P ₁ , P ₁ S '> C, MSB = 1, Sequence Phase = 1, PDM Pattern Symbol = P ₁ , P ₀ If S '<C, Sequence Phase = 0, PDM Pattern Symbol = P ₁ , P ₀ If S '<C, Sequence Phase = 1, PDM Pattern Symbol = P ₀ , P ₁ The method of claim 1, And the PDM pattern symbols Pi of the pattern symbol portion are defined as in Equation 12 below. When MSB = 0, P ₀ = (binary representation of 0) P ₁ = (binary representation of 2 ^m ) When MSB = 1, P ₀ = (binary representation of 2 ^{m + 1} ) P ₁ = (representing all 1) (The width of pattern symbol P _i is 2 ^m ) In the pulse density modulation method to a pulse density modulator, A subgroup determination step of obtaining a subgroup determination value (m) and a most significant bit (MSB) according to an input value; A bit selecting step of selecting some bits of the input value for phase shifting of the input value; A phase shifter for obtaining a phase shift value S 'using the bit selected in the bit selection step and the subgroup decision value m and the most significant bit MSB obtained in the subgroup decision step; A counter step of outputting a counter value by the number of subgroups according to the subgroup determination value (m); A linear conversion step of linearly receiving the counter value of the counter step; A comparison step of comparing the phase shift value S ′ of the phase shift step with the linearly converted counter value of the linear shift step; A pattern symbol generation step of outputting a pattern symbol according to the output value of the comparison step, the sub decision value m of the subgroup determination step, and the most significant bit (MSB); And And a PDM bit generation step of generating a PDM bit according to the pattern symbol output in the pattern symbol generation step. The method of claim 8, The subgroup determination step determines the subgroup determination value m according to an input value. The equation for obtaining the subgroup decision value m is as shown in Equation (13) below. M = N when S = 0 When S <2 ^N-1 , S ≠ 2 ^k , S ≠ 0, digit of '1' that comes first after '0' from MSB of S expressed as m = N-1-binary When S <2 ^N-1 , S = 2 ^k , m = N-digit digit of '1' that comes first after '0' from MSB of S expressed as binary When S≥2 ^N-1 , S ≠ 2 ^N-1 , m = N-1-digit of '0' which comes first after '1' from MSB of S expressed as binary When S = 2 ^N-1 , m = N-1 The method of claim 8, In the bit selection step, the pulse density modulation method of the pulse density modulator, characterized in that for selecting the bit (B) necessary for the phase conversion using Equation (14) below. B = From (N-m-2) th digit bit of S to binary bit (If N-m-2 is less than 1, B = 0.) The method of claim 8, S 'obtained through the phase shifting step is calculated by Equation (15) below. When MSB = 0, S '= {(2 ^Nm-2 -B) x 2}% 2 ^Nm-1 When MSB = 1, S '= (B × 2)% 2 ^Nm-1 (If N-m-2 is less than 1, B = 0.) The method of claim 8, The phase change value S 'is linearly converted in the linear conversion step as a result of the comparison between the phase change value S' and the counter value C linearly transformed in the linear conversion step. The pulse density modulation method of the pulse density modulator, characterized in that when the phase change occurs larger than (C), the comparison step outputs '1'. The method of claim 8, The pattern symbol generation step is a pulse density modulation method of the pulse density modulator, characterized in that to generate a PDM pattern symbol through the following equation (16). If S '> C, MSB = 0, Sequence Phase = 0, PDM pattern symbol = P ₀ , P ₁ S '> C, MSB = 0, Sequence Phase = 1, PDM Pattern Symbol = P ₀ , P ₀ S '> C, MSB = 1, Sequence Phase = 0, PDM Pattern Symbol = P ₁ , P ₁ S '> C, MSB = 1, Sequence Phase = 1, PDM Pattern Symbol = P ₁ , P ₀ If S '<C, Sequence Phase = 0, PDM Pattern Symbol = P ₁ , P ₀ If S '<C, Sequence Phase = 1, PDM Pattern Symbol = P ₀ , P ₁ The method of claim 8, The PDM pattern symbol Pi of the pattern symbol step is defined as shown in Equation 17 below. When MSB = 0, P ₀ = (binary representation of 0) P ₁ = (binary representation of 2 ^m ) When MSB = 1, P ₀ = (binary representation of 2 ^{m + 1} ) P ₁ = (representing all 1) (The width of pattern symbol P _i is 2 ^m )

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