JP2006050202A - Dem processing apparatus, d/a converter, and dem processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of suppressing production of an idle tone in the case that a DEM processing of a rotation system is applied to a digital signal for continuously representing a similar value such as a non-signal and a DC signal. <P>SOLUTION: A DEM processing apparatus that is connected to a D/A converter for generating an analog signal by receiving a first digital signal in a plurality of bits and selecting an analog value of a D/A conversion element associated with each bit of the first digital signal in response to a prescribed bit value denoted by each bit of the first digital signal and synthesizing the analog values and carries out DEM processing to match the D/A conversion element, assigns randomized selection priority to each bit of the first digital signal, sequentially selects the bits of the first digital signal in the order of higher selection priority by a value of a second digital signal when receiving the second digital signal being a D/A conversion object including the value in response to the number of analog values to be selected, generates the first digital signal wherein the values of the selected bits are prescribed bit values and transmits the first digital signal to the D/A converter. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a DEM processing apparatus, a D / A conversion apparatus, and a DEM processing method.

  As a D / A converter that converts a digital signal into an analog signal, for example, a switched capacitor type D / A converter, an R-2R ladder resistor type D / A converter, and the like have been proposed.

  For example, as shown in FIG. 6, the switched capacitor type D / A converter is associated with an amplifier AMP provided with a feedback capacitive element Cf and each bit D (1 to N) of an N-bit digital signal. Capacitance element C (1-N) having the same capacitance value and a switch for supplying either one of positive reference voltage Vref or negative reference voltage -Vref to one terminal of capacitance element C (1-N) SWA, switches SWB and SWC connected between the other terminal of the capacitive element C (1 to N) and the inverting input terminal of the amplifier AMP, and one of the output terminal of the amplifier AMP and the capacitive element C (1 to N) And a switch SWD connected between the two terminals.

  Note that the switch SWA is turned on / off by the logical product of the value of each bit D (1 to N) of the corresponding digital signal and the clock signal CK1, and the switch SWB is turned on / off by the clock signal CK1, and the switches SWC and SWD Is turned on / off by a clock signal CK2 obtained by inverting the phase of the clock signal CK1.

  That is, the switched-capacitor type D / A converter has the above-described configuration, based on the states of the clock signals CK1 and CK2 and the respective bits D (1 to N) of the digital signal, the capacitive elements C (1 N), charge distribution will occur. Then, according to the charge conservation law, an analog signal corresponding to the total amount of charges held by the capacitive elements C (1 to N) is output from the amplifier AMP.

  For example, as shown in FIG. 7, the R-2R ladder resistance type D / A converter includes an amplifier AMP provided with a feedback resistor Rf, and resistance elements R and 2R provided between the reference voltage Vref and the ground voltage GND. R-2R ladder resistor combined with each other, and one terminal of the resistance element 2R associated with each bit D (1 to N) of the N-bit digital signal is either the ground voltage GND or the inverting input terminal of the amplifier AMP. And switches SW (1 to N) for connection to either of them. Note that the switches SW (1 to N) are turned on / off by the respective bits D (1 to N) of the corresponding digital signal.

  That is, the R-2R ladder resistance type D / A converter has the above-described configuration, and the voltage value of one terminal of each resistance element 2R selected based on the state of each bit D (1 to N) of the digital signal. Is supplied to the inverting input terminal of the amplifier AMP. As a result, an analog signal corresponding to the sum of the voltage values at one terminal of each resistance element 2R is output from the amplifier AMP.

  As described above, the D / A converter is a capacitance element C (1 to N) having the same capacitance value in the switched capacitor type D / A converter, or a resistance element having the same resistance value in the R-2R ladder resistance type. It has “D / A conversion elements” of the same characteristic value (capacitance value, resistance value, etc.) associated with each bit of the digital signal, such as 2R. Then, the “analog value (charge amount, voltage value, etc.)” weighted to each D / A conversion element is selected and synthesized based on a predetermined bit value (eg, “1”) indicated by each bit of the digital signal. As a result, D / A conversion is performed.

  However, the D / A conversion element has a so-called element mismatch in which the characteristic value (capacitance value, resistance value, etc.) varies due to manufacturing variations and environmental conditions during the manufacturing process. It is a factor that causes deterioration. For this reason, a DEM (Dynamic Element Matching) technique has been proposed in order to eliminate element mismatch of the D / A conversion element (see, for example, Non-Patent Document 1). In addition, a rotation method has been proposed as the most common DEM algorithm. Here, as an outline of the rotation-type DEM algorithm, for example, the contents disclosed in Patent Document 1 will be described with reference to FIGS.

  The example of the system shown in FIG. 8 is a so-called D / A converter, which applies a digital signal to be D / A converted via a multi-bit ΔΣ modulator 200, a DEM circuit 210 and a D / A converter 220. Are converted into analog signals. Here, the DEM circuit 210 converts the value of the ΔΣ modulation output into a thermometer code, and performs rotation type DEM processing on the thermometer code. The thermometer code is a code representing a value by the number of bits “1”. For example, when the value of the ΔΣ modulation output is “3”, the thermometer code in the 8-bit notation is “11100000 (three left-justified“ 1 ”s)”, and “1” when the DEM processing is not performed. The analog value of the D / A conversion element corresponding to the bit "" is selected.

  FIG. 9 is a diagram for explaining a specific example of the rotation-type DEM processing. In the example shown in FIG. 9, the DEM circuit 210 receives the ΔΣ modulation outputs “4”, “5”, and “3” sequentially from the multi-bit ΔΣ modulator 200 for each cycle. The code is in the case of 8-bit notation.

  Here, the rotation type DEM processing is to rotate each bit value of the digital signal to be D / A converted clockwise by a predetermined rotation amount. The rotation amount can be defined as a remainder obtained by dividing the total sum of the predetermined bit values “1” of the digital signal subjected to the previous DEM processing by the number of bits of the thermometer code.

  First, the ΔΣ modulation output “4” received in cycle 1 is converted into a thermometer code “11110000”. Here, when the sum of the predetermined bit values “1” of the digital signal subjected to the previous (cycle 0) DEM processing is set to “0”, the thermometer code is not rotated and is D / It is transmitted to the A converter 220.

  Next, the ΔΣ modulation output “5” received in cycle 2 is converted into a thermometer code “11111000”. Here, since the sum of the bits “1” of the digital signal subjected to the DEM processing (cycles 0 and 1) is “4”, the thermometer code is rotated clockwise by 2 bits “100001111”. "To the D / A converter 220.

  Similarly, the ΔΣ modulation output “3” received in cycle 3 is also converted into thermometer code “1110000”, and the bit of the digital signal subjected to the DEM processing up to the previous (cycles 0, 1 and 2). Since the sum of “1” is “9”, the thermometer code is transmitted to the D / A converter 220 as “01110000” rotated clockwise by 9 bits.

As described above, according to the rotation type DEM processing, the D / A converter 220 can match the D / A conversion elements by equalizing the number of times the analog value of each D / A conversion element is selected. It can be done.
JP 2000-78015 A Shreier and B Zhang "Noise Shaped Multibit D / A Converter Employing Unit Elements" Electronics Letters vol.31 no.20 pp.1712-1713 September 1995.

In the example shown in FIG. 9, when the DEM circuit 210 continuously receives the ΔΣ modulation output “4” for each cycle from the multi-bit ΔΣ modulator 200, the rotation amount is “4” for each cycle. "It becomes constant. Therefore, the thermometer code changes with a periodicity of “11110000”, “000011111”, “11110000”, “000011111”.
That is, as in the example described above, when a DEM process of the rotation method as shown in FIG. 9 is performed on a digital signal that continuously shows the same value, such as no signal or DC signal, There will always be periodicity in the meter code.
When a frequency corresponding to the periodicity of the thermometer code is included in the audible band, noise called “idle tone” as shown in FIG. 10 is generated. For example, in the use of an audio D / A converter, the idle tone is heard as an unnatural sound by a human ear, and is a factor that deteriorates the sound quality.

  The main present invention for solving the above-described problem is to receive a first digital signal having a plurality of bits, and to convert an analog value of a D / A conversion element associated with each bit of the first digital signal into the first digital signal. A DEM (Dynamic Element Matching) process for matching the D / A conversion element connected to a D / A converter that generates an analog signal by selecting and synthesizing according to a predetermined bit value indicated by each bit of In the DEM processing apparatus that performs the processing, a selection priority having randomness is assigned to each bit of the first digital signal, and a D / A conversion target having a value corresponding to the number of analog values to be selected is assigned. When two digital signals are received, the bits of the first digital signal are selected in descending order of the selection priority according to the value of the second digital signal, and the selected bits are selected. To generate the first digital signal values to said predetermined bit value, transmitting to the D / A converter, and to.

  According to the present invention, it is possible to provide a DEM processing device, a D / A conversion device, and a DEM processing method capable of suppressing the occurrence of idle tones.

<D / A converter>
FIG. 1 is a diagram showing a configuration of a D / A conversion device 100 for audio equipment using a multi-bit ΔΣ modulator according to an embodiment of a “D / A conversion device” recited in the claims of the present application. .

  The D / A conversion device 100 includes an interpolation filter 10, a multi-bit ΔΣ modulation unit 20, a DEM processing unit 30, a D / A converter 40, and an LPF 50.

  The interpolation filter 10 receives a digital signal DIN having a predetermined sampling frequency fs (for example, 48 kHz) with a predetermined resolution (for example, 24 bits), and interpolates the digital signal DIN by a predetermined operation (for example, linear interpolation). . Furthermore, the interpolation filter 10 converts the digital signal DIN into a digital signal u having the same resolution (for example, 24 bits) by oversampling at a frequency (for example, 128 times) higher than the sampling frequency fs.

  The multi-bit ΔΣ modulation unit 20 receives the digital signal u from the interpolation filter 10 and performs multi-bit output ΔΣ modulation on the digital signal u to reduce the number of bits (for example, 5 bits). The signal v is converted into a “second digital signal” described in the claims of this application. In the delta-sigma modulation shown in FIG. 1, the digital signal u is converted into a digital signal v indicating one level intensity (scalar amount) out of the level intensity from “0 to 31” expressed by 5 bits. Is the case. In addition, as described above, the multi-bit ΔΣ modulation unit 20 converts the digital signal u into the digital signal v. As a result, the noise shaping of the quantization noise included in the digital signal u to a high frequency region outside the necessary band is performed. It can be done.

  The DEM processing unit 30 assigns “selection priority” having randomness to each bit of the finally generated digital signal sv (“first digital signal” recited in the claims of the present application). When the DEM processing unit 30 receives the scalar amount of the digital signal v from the multi-bit ΔΣ modulation unit 20, the DEM processing unit 30 corresponds to the number of analog values of the D / A conversion element to be selected according to the level intensity indicated by the digital signal v. Then, the bits of the digital signal sv are selected in descending order of the selection priority, and a digital signal sv having a vector amount with the selected bit value set to a predetermined bit value (for example, “1”) is generated. The data is transmitted to the converter 40.

  The D / A converter 40 has a D / A conversion element (for example, a capacitive element, a resistor, etc.) associated with each bit of the digital signal sv received from the DEM processing unit 30. Then, an analog value (for example, charge amount, voltage value, etc.) weighted to each D / A conversion element is selected and synthesized based on each bit value of the digital signal sv to generate an analog signal w. . Note that the D / A converter 40 includes various D / A converters such as a switched capacitor type D / A converter shown in FIG. 6 and an R-2R ladder resistance type D / A converter shown in FIG. A / A converter can be employed.

  An LPF (Low Pass Filter) 50 outputs an analog signal AOUT obtained by performing a low-pass filter process on the analog signal w input from the D / A converter 40 to remove a high frequency component.

<DEM processing unit>
=== Configuration ===
The configuration of the DEM processing unit 30 according to an embodiment of the “DEM processing apparatus” recited in the claims of the present application will be described with reference to FIG.
The DEM processing unit 30 includes a “random number generation unit 31”, a “vector operation unit 32”, and a “vector quantization unit 33”. Each function of the DEM processing unit 30 is implemented as hardware or software.

  The random number generation unit 31 generates a random number R (t) based on a well-known random number generation algorithm such as an average sampling method, a linear congruential method, an M-sequence random number, an exponential random number sequence, or the like. The random number R (t) is used as one parameter for setting a selection priority having randomness that can be varied for each cycle.

  The vector calculation unit 32 is a vector that is a result of performing a predetermined filtering process (for example, n-th order noise shaping process) on the digital signal sv (t) of the vector amount output from the vector quantization unit 33. A quantity sy (t) is generated and output to the vector quantization unit 33. The vector quantity sy (t) is used as one parameter for setting a selection priority having randomness that is variable for each cycle, together with the random number R (t).

  The vector calculation unit 32 subtracts the previous vector calculation unit 32 output sy (t−1) from the digital signal sv (t) to generate a deviation se (t), and a deviation se (t). A vector function unit 321 that generates a vector quantity sy ′ (t) that is a result of performing a predetermined filtering process defined by the vector function “H (z) −1”, and a vector function unit 321 output sy ′ ( a minimum value detecting unit 322 that detects a minimum value among the elements of t) and generates a vector quantity su (t) with all the values having the opposite polarity of the minimum value as an element, and an output sy of the vector function unit 321 '(T) and the minimum value detector 322 output su (t) are added to each other to generate a vector quantity sy (t).

  The vector quantization unit 33 is based on the selection priority that is variable based on the output sy (t−1) of the previous vector calculation unit 32 and the random number R (t) generated in the random number generation unit 31. The digital signal v (t) having a predetermined level intensity (scalar amount) input from the multi-bit ΔΣ modulation unit 20 is converted into a digital signal sv (t) having a vector amount having the same level intensity as the digital signal v (t). Are encoded and output to the D / A converter 40.

Here, the processing content of the DEM processing unit 30 described above can be expressed by the following mathematical formula 1.

Further, when the degree of mismatch of the D / A conversion elements in the D / A converter 40 is expressed by a vector ed of m rows × 1 column (however, the sum of all elements of ed is set to “0”), D / The error of the output of the A converter 40 can be expressed by the following formula 2.

  Based on Expression 2, it can be found that the error of the output of the D / A converter 40 due to the mismatch of the D / A conversion elements can be arbitrarily modulated by the vector function H (z). That is, as long as an appropriate vector function H (z) is selected, the so-called noise shaping effect that shifts the error of the output of the D / A converter 40 due to the mismatch of the D / A converter elements to a high band. Can be obtained.

=== Flow of DEM processing ===
The flow of DEM processing according to an embodiment of the present invention will be described based on the flowchart of FIG. Unless otherwise specified, the subject of the following operations is the DEM processing unit 30.
First, it is assumed that the vector quantization unit 33 receives a scalar amount digital signal v (t) having a predetermined level intensity from the multi-bit ΔΣ modulation unit 20 at time t (S300). At this time, the random number generation unit 31 generates a random number R (t) based on a predetermined random number generation algorithm (S301).
The vector quantization unit 33 finally generates a vector quantity based on the previous output sy (t−1) of the vector calculation unit 32 and the random number R (t) generated by the random number generation unit 31. The selection priority for setting which element among the elements of the digital signal sv (t) is set to “1” is determined (S302). In determining the selection priority, the following two conditions are considered.
(Condition 1) Among the elements of the previous output sy (t−1) of the vector calculation unit 32, the selection priority is increased from the element with the lowest value.
(Condition 2) The element group having the same value among the elements of the previous output sy (t−1) of the vector calculation unit 32 is determined in a predetermined order from the element specified by the random number R (t) (for example, right Assign a selection priority.
Based on the determined selection priority, the vector quantization unit 33 sets the element value to “1” by the number corresponding to the level strength of the digital signal v (t) in order from the highest selection priority. Then, the digital signal sv (t) with the values of the other elements set to “0” is generated (S303).

Next, the vector calculation unit 32 performs the following process to generate sy (t) that is referred to when determining the selection priority at time t + 1.
First, the adder 320 subtracts the previous output sy (t−1) of the vector calculator 32 from the digital signal sv (t) generated in the vector quantizer 33 to generate a deviation se (t). (S304). In the vector function unit 321, arithmetic processing using a predetermined vector function “H (z) −1” is performed on the deviation se (t) generated by the adding unit 320 to generate sy ′ (t) ( S305). The minimum value detection unit 322 detects the minimum value min (t) among all elements of the output sy ′ (t) of the vector function unit 321.
Here, the vector calculation unit 32 determines whether or not the minimum value min (t) detected by the minimum value detection unit 322 is a negative value (S306). If the minimum value min (t) is a negative value (S306: YES), the vector calculation unit 32 calculates the minimum value min (t from all elements of the output sy ′ (t) of the vector function unit 321. ) Is subtracted to generate sy (t). On the other hand, when the minimum value min (t) is not a negative value (S306: NO), the vector calculation unit 32 sets the output sy ′ (t) of the vector function unit 321 as it is to sy (t).

=== Specific Example of DEM Processing ===
FIG. 4 is a diagram for explaining a specific example of the DEM processing according to an embodiment of the present invention. In the example illustrated in FIG. 4, the DEM processing unit 30 sequentially receives ΔΣ modulation outputs “4”, “5”, and “4” from the multi-bit ΔΣ modulation unit 20 for each cycle. Assume that the generation unit 31 sequentially generates random numbers R “3”, “5”, and “2” for each cycle. Furthermore, the number of bits of the digital signal sv transmitted from the DEM processing unit 30 to the D / A converter 40 is assumed to be 8 bits. Furthermore, the vector function set in the vector function unit 321 is a primary noise shaping function (H (z) = z ^ (− 1)) represented by “z ^ (− 1) −1”. Furthermore, in the following description, it is assumed that cycles 0, 1, 2, and 3 shown in the figure are associated with times t-1, t, t + 1, and t + 2, respectively.

<< Cycle 1 >>
First, in cycle 1, the ΔΣ modulation output is “4”, sy (t−1), which is the output of the vector calculation unit 32 in the previous cycle 0, is “00000000”, and the random number R (t) generated in the random number generation unit 31 is “3”.
Here, since the output sy (t−1) of the vector calculation unit 32 is “00000000”, there is no superiority or inferiority of the effect of noise shaping regardless of which element is selected, but the random number R (t) is Since it is “3”, for each element of the vector operation unit 32 output sy (t−1), the element from the “4” bit next to the “3” bit goes in a predetermined direction (for example, clockwise). In order, the selection priority “67812345” is assigned. The selection priority is set to be higher in the order of “87654321”.

  Therefore, since the ΔΣ modulation output in cycle 1 is “4”, the vector quantization 33 output sv (t) is obtained by adding the values of the elements “4” in total from the elements of the “4” bit having the highest selection priority. “0001” is set to “1”, and the values of other elements are set to “0”. That is, in the D / A converter 40 in cycle 1, the D / A conversion corresponding to the elements from the “4” bit to the “7” bit is performed by “00011110” which is the vector quantization 33 output sv (t). The analog value of the element will be selected.

  In cycle 1, deviation se (t) and vector function unit 321 output sy ′ () are generated to generate vector operation unit 32 output sy (t) that is referred to in determining the selection priority in next cycle 2. t), the minimum value detection unit 322 output su (t) is sequentially generated as follows.

First, in the addition unit 320, the deviation se (t) is generated as a result of subtracting the vector calculation unit 32 output sy (t-1) from the vector quantization 33 output sv (t). The deviation se (t) is ““ 00011110 ”=“ 00011110 ”−“ 00000000 ””.
Next, the vector function unit 321 generates sy ′ (t) as a result of performing the calculation of the vector function “z ^ (− 1) −1” on the deviation se (t). The vector function unit 321 output sy ′ (t) is “000-1-1-1-10” obtained by inverting the polarity of the deviation se (t).
Next, the minimum value detection unit 322 detects the minimum value min (t) among all the elements of the vector function unit 321 output sy ′ (t). Since the minimum value min (t) is “−1”, the output of the minimum value detection unit 322 su (t) is “11111111” configured with elements obtained by inverting the polarity of the minimum value min (t). Become.
The adder 323 adds the vector function unit 321 output sy ′ (t) and the minimum value detector 322 output su (t) to generate the vector operation unit 32 output sy (t). Note that the output sy (t) of the vector calculation unit 32 is ““ 111100001 ”=“ 000-1-1-1-10 ”+“ 11111111 ”.

<< Cycle 2 >>
Next, in cycle 2, the ΔΣ modulation output is “5”, the sy (t) output from the vector calculation unit 32 in the previous cycle 1 is “11100001”, and the random number R (t + 1) generated in the random number generation unit 31 is “ 5 ".

  Here, since the output sy (t) of the vector operation unit 32 is “11100001”, the D / A conversion element corresponding to the elements from the “8” bit to the “3” bit in the previous cycles 0 and 1. It can be confirmed that the selected number of times is smaller than the analog value of the D / A conversion element corresponding to the elements from the “4” bit to the “7” bit.

  That is, if the analog value of the D / A conversion element corresponding to the elements from the “8” bit to the “3” bit is preferentially selected in cycle 2, the effect of noise shaping can be obtained efficiently. I understand. Accordingly, the selection priority “234 ***” is sequentially assigned to each element having the same “1” value from the “8” bit to the “3” bit of the output sy (t) of the vector operation unit 32. * 1 ”is assigned. At this time, the selection priority may be determined based on the random number R.

  Further, each element having the same “0” value from the “4” bit to the “7” bit of the output sy (t) of the vector operation unit 32 is designated by a random number R (t + 1). The selection priority is assigned in order from the element in a predetermined direction (for example, clockwise). Since the random number R (t + 1) is “5”, the selection priority “*** 7856 *” is assigned in order from the “6” bit next to the “5” bit. That is, the selection priority determined in cycle 2 is “2348561”.

  Therefore, since the ΔΣ modulation output is “5” in cycle 1, the vector quantization 33 output sv (t + 1) is set to “1” for the total “5” elements in order from the element having the highest selection priority. The other element values are “11100101” with “0”. That is, in the D / A converter 40 in cycle 2, the D / A conversion corresponding to the elements from the eighth bit to the third bit and the sixth bit is performed by “11100101” which is the vector quantization 33 output sv (t + 1). The analog value of the element will be selected.

Also, in cycle 2, in order to generate the vector operation unit 32 output sy (t + 1) referred to in determining the selection priority in the next cycle 3, the deviation se (t + 1), The vector function unit 321 output sy ′ (t + 1) and the minimum value detection unit 322 output su (t + 1) are sequentially generated as follows.
First, in the addition unit 320, a deviation se (t + 1) is generated as a result of subtracting the vector calculation unit 32 output sy (t) from the vector quantization 33 output sv (t + 1). The deviation se (t) is ““ 00000100 ”=“ 11100101 ”−“ 11100001 ””.
Next, the vector function unit 321 generates sy ′ (t + 1) as a result of performing the calculation of the vector function “z ^ (− 1) −1” on the deviation se (t + 1). The vector function unit 321 output sy ′ (t + 1) is “00000-100” obtained by inverting the polarity of the deviation se (t + 1).
Next, the minimum value detection unit 322 detects the minimum value min (t + 1) among all elements of the vector function unit 321 output sy ′ (t + 1). Since the minimum value min (t + 1) is “−1”, the minimum value detection unit 322 output su (t + 1) is “11111111” composed of elements obtained by inverting the polarity of the minimum value min (t + 1). Become.
Then, the adder 323 adds the vector function unit 321 output sy ′ (t + 1) and the minimum value detector 322 output su (t + 1) to generate the vector operation unit 32 output sy (t). The vector operation unit 32 output sy (t + 1) is ““ 11111011 ”=“ 000000−10 ”+“ 11111111 ””.

<< Cycle 3 >>
Next, in cycle 3, the ΔΣ modulation output is “4”, sy (t + 1), which is the output of the vector calculation unit 32 in the previous cycle 2, is “11111011”, and the random number R (t + 2) generated in the random number generation unit 31 is “ 2 ".
Here, since the output sy (t + 1) of the vector calculation unit 32 is “11111011”, the analog value of the D / A conversion element corresponding to the element of the “6th” bit in the previous cycles 0, 1, 2 is It can be confirmed that the selected number of times is small as compared with the analog values of the D / A conversion elements corresponding to other bit elements.

  That is, it can be seen that if the analog value of the D / A conversion element corresponding to an element other than the “6th” bit is preferentially selected in cycle 3, the effect of noise shaping can be obtained efficiently. Since the elements other than the sixth bit of the output sy (t + 1) of the vector operation unit 32 indicate the same “1” value, there is no superiority or inferiority of the noise shaping effect regardless of which element is selected. . For this reason, the selection priority in elements other than the 6th bit of the vector operation unit 32 output sy (t + 1) is determined based on the random number R (t).

  That is, since the random number R (t) is “2”, for each element other than the sixth bit of the output sy (t + 1) of the vector operation unit 32, the “3” bit next to the “2” bit. Selection priority “67123 * 45” is assigned in order from the element in a predetermined direction (for example, clockwise). Further, the lowest selection priority “8” is assigned to the sixth bit of the output sy (t + 1) of the vector operation unit 32. Therefore, the selection priority determined in cycle 3 is “67128345”.

  Here, since the ΔΣ modulation output is “4” in cycle 3, the vector quantization 33 output sv (t + 2) is set to the value of the total of “4” elements “1” in order from the element having the highest selection priority. And “00111010” where the values of the other elements are “0”. That is, the D / A converter 40 in cycle 2 performs D / A conversion corresponding to the elements from the third bit to the fifth bit and the seventh bit by “00111010” which is the vector quantization 33 output sv (t + 2). The analog value of the element will be selected.

<Examples of effects>
In the above-described embodiment, even when the DEM processing unit 30 receives the digital signal v indicating the same level intensity continuously such as no signal or DC signal from the multi-bit ΔΣ modulation unit 20, the digital signal sv Based on the selection priority having randomness assigned to each bit of the digital signal v, the opportunity that the bit content of the digital signal sv generated according to the level strength of the digital signal v has periodicity is generally eliminated. Can do. That is, it is possible to suppress the occurrence of idle tones, which has been a problem in the conventional rotation type DEM processing. Note that the output of the D / A converter 40 when the DEM processing according to the present invention is performed has, for example, a frequency characteristic that does not include an idle tone as shown in FIG.

  In the above-described embodiment, the selection priority is not randomly assigned to all bits of the digital signal sv, but the selection priority is randomly assigned only to some bits of the digital signal sv. Thus, the occurrence of idle tones can be sufficiently suppressed. Therefore, the number of past selections of the predetermined bit value is small according to the past selection state of the predetermined bit value (bit value for selecting an analog value of a desired D / A conversion element) in each bit of the digital signal sv. In order from the bit of the digital signal sv, a higher selection priority is assigned, and for the bit group of the digital signal sv having the same number of past selections of the predetermined bit value, the bit of the digital signal sv specified by the random number R is in the predetermined order A high selection priority is assigned. As a result, it is possible to suppress the occurrence of idle tones while ensuring the effect of noise shaping in the DEM processing. Furthermore, compared with a method in which selection priority is assigned to all bits of the digital signal sv completely at random, a complicated and large-scale circuit is not required.

  In the above-described embodiment, the D / A converter 100 for audio equipment, for example, equipped with the DEM processing unit 30 can provide excellent sound quality in which the generation of idle tones is suppressed.

  Although the present embodiment has been described above, the above-described examples are for facilitating the understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed / improved without departing from the spirit thereof, and the present invention includes equivalents thereof.

It is a figure which shows the structure of the D / A converter device concerning one Embodiment of this invention. It is a figure which shows the structure of the DEM process part concerning one Embodiment of this invention. It is a flowchart explaining operation | movement of the DEM process part concerning one Embodiment of this invention. It is a figure explaining the specific example of operation | movement of the DEM process part concerning one Embodiment of this invention. It is a figure which shows the frequency characteristic of DAC output concerning one Embodiment of this invention. It is a figure which shows the structure of a switched capacitor type D / A converter. It is a figure which shows the structure of a R-2R ladder resistance type | mold D / A converter. It is a figure which shows the structure of the conventional D / A converter. It is a figure explaining the specific example of the conventional DEM process. It is a figure which shows the frequency characteristic of the conventional DAC output.

Explanation of symbols

10 Interpolation Filter 20 Multibit ΔΣ Modulation Unit 30 DEM Processing Unit 31 Random Number Generation Unit 32 Vector Operation Unit 33 Vector Quantization Unit 40 D / A Converter 50 LPF
100 D / A converter 200 Multi-bit ΔΣ modulator 210 DEM circuit 220 D / A converter 320 Adder 321 Vector function unit 322 Minimum value detector 323 Adder

Claims (7)

The first digital signal of a plurality of bits is received, and the analog value of the D / A conversion element associated with each bit of the first digital signal is determined according to a predetermined bit value indicated by each bit of the first digital signal. In a DEM processing apparatus that is connected to a D / A converter that generates an analog signal by selecting and synthesizing and performs DEM (Dynamic Element Matching) processing for matching the D / A conversion elements,
A selection priority having randomness is assigned to each bit of the first digital signal,
When a second digital signal to be D / A converted having a value corresponding to the number of analog values to be selected is received,
For the value of the second digital signal, select the bits of the first digital signal in descending order of the selection priority,
Generating the first digital signal with the value of the selected bit as the predetermined bit value and transmitting the first digital signal to the D / A converter;
A DEM processing apparatus characterized by the above. Based on the number of selections in which the predetermined bit value in the past in each bit of the first digital signal is selected, the higher selection priority is assigned in order from the bit of the first digital signal with the smaller number of selections;
In the bit group of the first digital signal having the same number of selections, assigning a higher selection priority in a predetermined order from the bit specified by a random number in the bit group,
The DEM processing apparatus according to claim 1. A random number generator for generating the random number;
A vector calculation unit for generating a third digital signal for setting the selection priority in the current cycle based on the first digital signal in the previous cycle;
Based on the third digital signal generated in the vector operation unit in the previous cycle and the random number generated in the random number generation unit in the current cycle, the assignment of the selection priority in the current cycle is determined,
A vector quantization unit for generating the first digital signal in the current cycle based on the second digital signal received in the current cycle and the determined assignment of the selection priority in the current cycle;
The DEM processing apparatus according to claim 2, further comprising: The first digital signal of a plurality of bits is received, and the analog value of the D / A conversion element associated with each bit of the first digital signal is determined according to a predetermined bit value indicated by each bit of the first digital signal. A D / A converter that generates an analog signal by selecting and synthesizing; and
When a selection priority having randomness is assigned to each bit of the first digital signal and a second digital signal to be D / A converted having a value corresponding to the number of analog values to be selected is received The first digital signal is selected in order from the one having the highest selection priority, and the first digital signal having the value of the selected bit as the predetermined bit value corresponding to the value of the second digital signal. A DEM (Dynamic Element Matching) processing device that generates and transmits to the D / A converter;
A D / A converter characterized by comprising: The DEM processing apparatus includes:
Based on the number of selections in which the predetermined bit value in the past in each bit of the first digital signal is selected, the higher selection priority is assigned in order from the bit of the first digital signal with the smaller number of selections;
In the bit group of the first digital signal having the same number of selections, assigning a higher selection priority in a predetermined order from the bit specified by a random number in the bit group,
The D / A converter according to claim 4 characterized by things. The DEM processing apparatus includes:
A random number generator for generating the random number;
A vector calculation unit for generating a third digital signal for setting the selection priority in the current cycle based on the first digital signal in the previous cycle;
Based on the third digital signal generated in the vector operation unit in the previous cycle and the random number generated in the random number generation unit in the current cycle, the assignment of the selection priority in the current cycle is determined,
A vector quantization unit for generating the first digital signal in the current cycle based on the second digital signal received in the current cycle and the determined assignment of the selection priority in the current cycle;
The D / A conversion device according to claim 5, comprising: The first digital signal of a plurality of bits is received, and the analog value of the D / A conversion element associated with each bit of the first digital signal is determined according to a predetermined bit value indicated by each bit of the first digital signal. A method of performing DEM (Dynamic Element Matching) processing for matching the D / A conversion element in the D / A converter that generates an analog signal by selecting and synthesizing,
A selection priority having randomness is assigned to each bit of the first digital signal,
Receiving a second digital signal to be D / A converted having a value corresponding to the number of analog values to be selected;
Selecting the bits of the first digital signal in descending order of the selection priority according to the value of the second digital signal;
Generating the first digital signal with the value of the selected bit as the predetermined bit value;
Transmitting the generated first digital signal to the D / A converter;
A DEM processing method characterized by comprising: