KR100609527B1 - Phase change resistor cell and non-volatile memory device using the same - Google Patents

Abstract

The present invention relates to a phase change resistive cell and a nonvolatile memory device using the same, and discloses a technique for reducing the number of cell arrays by configuring a cell array including a resistive memory device and a series PN diode chain in multiple layers. The present invention provides a bit line on top of an interlayer insulating film, a series PN diode chain switch on top of a bit line, a resistance memory device on top of a series PN diode chain switch, and an interlayer insulating film. The series diode cell array can be configured in multiple layers to reduce the overall chip size.

Description

Phase change resistor cell and non-volatile memory device using the same

1A to 1D are diagrams for explaining a conventional phase change resistance element.

2 is a unit cell configuration diagram of a phase change resistance cell according to the present invention;

3 is a unit cell cross-sectional view of the phase change resistance cell of FIG. 2.

4 is a plan view of a bit line of the phase change resistance cell of FIG.

5 is a plan view of the phase change resistance cell of FIG.

6 is a cross-sectional view of the phase change resistance cell of FIG.

7 is a view for explaining the operation of the series diode switch of FIG.

8 is a configuration diagram of a nonvolatile memory device using a phase change resistance cell according to the present invention.

FIG. 9 is a layout diagram of the phase change resistance cell array of FIG. 8. FIG.

FIG. 10 is a detailed circuit diagram of the phase change resistance cell array of FIG. 8. FIG.

FIG. 11 is a detailed circuit diagram of the sense amplifier of FIG. 8. FIG.

12 is an operation timing diagram of a nonvolatile memory device using a phase change resistance cell according to the present invention in lead mode.

13 is a timing diagram of an operation in a write mode of a nonvolatile memory device using a phase change resistance cell according to the present invention;

14 is a view for explaining a temperature characteristic of a multilayer phase change resistance cell in the write mode of the nonvolatile memory device using the phase change resistance cell according to the present invention;

The present invention relates to a phase change resistance cell and a nonvolatile memory device using the same, and to reduce the overall size of the memory by configuring a multi-layer cell array including a resistor diode and a series diode cell that does not require a separate gate control signal. Technology

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A to 1D are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2.

That is, as shown in FIG. 1C, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 1D, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, if the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

Meanwhile, a conventional memory device includes one switching element and one memory element for storing data. Here, the switching element of the conventional memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

However, when the cell array is implemented using the NMOS transistor as a switching device, there is a problem in that the overall chip size is increased. Accordingly, as described above, a cross point cell is implemented by using a phase change resistance element having a nonvolatile characteristic and a series diode switch that does not require a separate gate control signal, and the cross point cell is formed in a multilayer to form an overall chip size. There is a need for the present invention that can reduce the number.

The present invention has been made to solve the above problems and has the following object.

First, the purpose of the present invention is to improve the process efficiency by forming a bit line on the interlayer insulating film, stacking a series diode switch on top of the bit line, and stacking a phase change resistance device on the top of the series diode switch. .

Second, the purpose of the present invention is to reduce the overall size of the nonvolatile memory by arranging a phase change resistive cell array in a multi-layer and a circuit element region in a lower portion of the interlayer insulating layer.

At least two phase change resistance cells of the present invention for achieving the above object are connected through the bit line contact node and the both ends of the bit line formed on the insulating layer, and at least two connected in series with the top of the bit line contact node A series diode switch having the above diode element; A phase change resistance element having a top electrode and a phase change layer, the crystallization state of which is changed according to a magnitude of a current applied from a word line; And a unit phase change resistance cell having a contact bottom electrode connecting a common node to which two or more diode elements are connected and a phase change layer.

A nonvolatile memory device using a phase change resistance cell of the present invention includes a plurality of phase change resistance cell arrays arranged in a row and column direction and including a plurality of phase change resistance cells stacked in a multilayer structure and separated from each other by an insulating layer. ; A plurality of word line drivers selectively driving word lines of the plurality of phase change resistance cell arrays; And a plurality of sense amplifiers for sensing and amplifying data applied from the plurality of phase change resistor cell arrays, each of the plurality of phase change resistor cells comprising a bit line formed over the insulating layer; A series diode switch connected to both ends of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the upper portion of the bit line contact node; A phase change resistance element having a top electrode and a phase change layer, the crystallization state of which is changed according to a magnitude of a current applied from a word line; And a contact bottom electrode connecting the common node to which two or more diode elements are connected and the phase change layer.

A nonvolatile memory device using a phase change resistance cell of the present invention includes: a plurality of phase change resistance cell arrays including a plurality of unit phase change resistance cells arranged in a row and column direction; A circuit element region formed on a silicon substrate provided under the plurality of phase change resistor cell arrays to drive control the plurality of phase change resistor cell arrays; And an insulating layer formed between the plurality of phase change resistance cell arrays and the circuit element region to insulate the plurality of phase change resistance cell arrays and the circuit element region from each other, wherein each of the plurality of unit phase change resistance cells is formed of an insulating layer. A bit line formed thereon; A series diode switch connected to both ends of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the upper portion of the bit line contact node; A phase change resistance element having a top electrode and a phase change layer, the crystallization state of which is changed according to a magnitude of a current applied from a word line; And a contact bottom electrode connecting the common node to which two or more diode elements are connected and the phase change layer.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a unit cell configuration diagram of a phase change resistance cell according to the present invention.

The unit phase change resistor (PCR) cell includes one phase change resistor element PCR and one series diode switch 10. Here, the series diode switch 10 includes a PNPN diode switch 11 and a PN diode switch 12. The PNPN diode switch 11 and the PN diode switch 12 are connected in parallel between the bottom electrode of the phase change resistance element PCR and the bit line BL.

The PNPN diode switch 11 is connected in the reverse direction between one electrode of the phase change resistance element PCR and the bit line BL, and the PN diode switch 12 is connected in the forward direction between one electrode of the phase change resistance element PCR and the bit line BL. do. The other electrode of the phase change resistance element PCR is connected to the word line WL.

3 is a unit cell cross-sectional configuration diagram of the phase change resistance cell of FIG. 2.

In the series diode switch 10, an insulating layer 31 made of SiO 2 is stacked on the silicon substrate 30, and a bit line BL is stacked on the insulating layer 31. The silicon layer 32 is formed on the bit line BL through the bit line contact node BLCN. The silicon layer 32 is formed by stacking a PNPN diode switch 11 and a PN diode switch 12 made of growth silicon or polysilicon to form a series-connected diode chain.

In the PNPN diode switch 11, the P-type region and the N-type region are alternately connected in series, and in the PN diode switch 12, the P-type region is formed adjacent to the N-type region of the PNPN diode switch 11.

The bit line BL is formed through the bit line contact node BLCN under the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11. In addition, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are connected to the phase change layer PCR (PCM) of the phase change resistance element PCR through the contact bottom electrode 22. Connected with

Accordingly, the present invention forms a series diode switch 10 between the bit line BL and the nonvolatile ferroelectric capacitor so that the bit line BL and the phase change resistance element PCR do not have a fair influence on each other.

Here, the phase change resistance device PCR includes a contact bottom electrode 22 connected to the top electrode 20, the phase change layer 21, and the series diode switch 10. The top electrode 20 itself of the phase change resistance element PCR serves as a word line WL.

4 is a plan view of the bit line BL and the insulating layer 31 of FIG. 3.

It can be seen that the phase change resistance cell forms a bit line BL electrode, which is a nano scale conductor wire, on the insulating layer 31.

5 is a plan view of a phase change resistance cell according to the present invention.

In the series diode switch 10, the PNPN diode switch 11 and the PN diode switch 12 made of the silicon layer 32 are continuously connected in series chain form. That is, one unit phase change resistance cell includes a PN diode switch 12 and a PNPN diode switch 11 connected in series. The PN diode switch 12 and the PNPN diode switch 11 are connected in series with each other in the unit phase change resistance cell adjacent to the same direction as one unit phase change resistance cell.

In addition, the series diode switch 10 is arranged in a plurality of layers with the insulating layer 31 interposed therebetween, and each of the upper series diode switch 10 and the lower series diode switch 10 is separated through the insulating layer 31. It is. Each silicon layer 32 is insulated from the upper and lower portions through the insulating layer 31.

Accordingly, one PN diode switch 12 and one PNPN diode switch 11 are sequentially selected among the diode elements connected in series to form one phase change resistance cell region.

In the series diode switch 10, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are formed adjacent to each other so as to be commonly connected to the contact bottom electrode CN of the phase change resistance element PCR. do.

In addition, the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 are connected to the bitline BL through the bitline contact node BLCN. The bitline contact node BLCN is commonly connected with the bitline contact node BLCN of the neighboring phase change resistance cell. That is, the same bit line contact node BLCN is commonly connected to the P-type region of the PNPN diode switch 11 and the N-type region of the PN diode switch 12 of the neighboring cell. In addition, the word line WL is formed on the upper top electrode 20 of the phase change resistance element PCR.

The phase change resistance cell having this structure forms a bit line BL electrode, which is a nanoscale conductor wire, on the insulating layer 31. The bit line contact node BLCN is formed at a portion connecting the series diode switch 10 and the bit line BL, and then the series diode switch 10 of the series PN diode chain structure is formed. Accordingly, the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 are connected to the bit line contact node BLCN.

Thereafter, a contact bottom electrode CN is formed on the series diode switch 10 to be connected to the phase change layer 21 of the phase change resistance element PCR. The top electrode 20 itself of the phase change resistance element PCR operates as a word line WL.

6 is a cross-sectional view of a phase change resistance cell according to the present invention forming a multilayer structure.

In the present invention, the phase change resistive cell array 40 is disposed in a multi-layer in view of the insulating layer 31. That is, the phase change resistance cell array 40 is formed as a first cell array, and a second layer cell array is stacked in a multi-layer structure on top of the first cell array. Here, an insulating layer 31 is deposited on the phase change resistance element PCR formed on the first cell array to insulate and separate the first cell array and the second cell array.

In addition, a plurality of circuit element regions 150 for driving the phase change resistance cell array 40 are disposed in the lower silicon substrate 30 based on the insulating layer 31. Here, the circuit element region 150 includes a word line driver, a sense amplifier, a data bus, a main amplifier, a data buffer, and an input / output port. The phase change resistor cell array 40 and the circuit element region 30 are insulated and separated based on the insulating layer 31.

FIG. 7 is a diagram for describing an operation of the series diode switch 10 of FIG. 2.

When the applied voltage of the bit line BL increases in the positive direction based on the phase change resistance element PCR, the series diode switch 10 is kept off at the operating voltage Vo due to the operating characteristics of the PNPN diode switch 11. No current flows

Subsequently, when the applied voltage of the bit line BL is further increased to reach the threshold voltage Vc, the PNPN diode switch 11 is turned on and the series diode switch 10 is turned on according to the forward operation characteristic of the diode, thereby rapidly increasing the current. . At this time, the value of the current I consumed when the applied voltage of the bit line BL is greater than or equal to the threshold voltage Vc is due to the value of a resistor (not shown) connected to the bit line BL and serving as a load.

After the PNPN diode switch 11 is turned on, even a small voltage Vs is applied to the bit line BL, so that a large amount of current can flow. At this time, the PN diode switch 10 is maintained in the off state by the reverse operating characteristics.

On the other hand, when the applied voltage of the bit line BL increases in the negative direction based on the phase change resistance element PCR, that is, when a constant voltage is applied to the word line WL, the forward operation characteristic of the PN diode switch 10 is reduced. As a result, the series diode switch 10 is turned on so that current flows at any operating voltage. At this time, the PNPN diode switch 11 maintains the off state due to the reverse operation characteristic.

8 is a configuration diagram of a nonvolatile memory device using a phase change resistance cell according to the present invention.

The present invention provides a plurality of PCR cell arrays 40, a plurality of word line drivers 50, a plurality of sense amplifiers 60, a data bus 70, a main amplifier 80, a data buffer 90 and input / output. The port 100 is provided.

Each PCR cell array 40 includes a plurality of unit phase change resistance cells having a structure as shown in FIG. 2 in a row and column direction. The plurality of word lines WLs arranged in the row direction are connected to the word line driver 50. The plurality of bit lines BL arranged in the column direction are connected to the sense amplifier 60.

Here, one PCR cell array 40 is connected in correspondence with one word line driver 50 and one sense amplifier 60.

The plurality of sense amplifiers 60 share one data bus 70. The data bus 70 is connected to the main amplifier 80, and the main amplifier 80 amplifies data applied from each sense amplifier 60 through the data bus 70.

The data buffer 90 buffers and outputs amplified data applied from the main amplifier 80. The input / output port 100 outputs output data applied from the data buffer 90 to the outside, or applies input data applied from the outside to the data buffer 90.

9 is a layout diagram of the PCR cell array 40 of FIG. 8.

In the PCR cell array 40, a plurality of word lines WL are arranged in a row direction, respectively, and a plurality of bit lines BL are arranged in a column direction, respectively. In addition, since the unit cell C is positioned only in an area where the word line WL and the bit line BL cross each other, a cross point cell requiring no additional area may be implemented.

Here, the cross point cell does not include an NMOS transistor device using a separate word line WL gate control signal. In addition, the structure of the phase change resistance device PCR using the series diode switch 10 having two connection electrode nodes can be positioned directly at the intersection of the bit line BL and the word line WL.

FIG. 10 is a detailed circuit diagram of the PCR cell array 40 of FIG. 8.

In the PCR cell array 40, a plurality of word lines WL <0> to WL <n> are arranged in a row direction, and a plurality of bit lines BL <0> to BL <m> are arranged in a column direction, respectively. The unit cell C is located only in an area where the word line WL and the bit line BL cross each other. Here, one unit cell C includes a phase change resistance element PCR and a series diode switch 10.

A plurality of sense amplifiers 60 are connected to each bit line BL in a one-to-one correspondence. Each sense amplifier 60 amplifies the result of comparing the voltage applied from the bit line BL with a predetermined reference voltage REF at the time of activation of the sense amplifier enable signal SEN.

In addition, the write switching element N1 is connected between the bit line BL <0> and the data bus 70. When the write switching signal WS0 is activated, the switching element N1 is turned on so that data input from the data bus 70 is applied to the bit line BL <0>. The switching element N2 is connected between the sense amplifier S / A0 and the data bus 70. When the lead switching signal RS0 is activated, the switching element N2 is turned on so that the output signal SOUT0 output from the sense amplifier S / A0 is output to the data bus 70.

In addition, the write switching element N3 is connected between the bit line BL <m> and the data bus 70. When the write switching signal WS1 is activated, the switching element N3 is turned on and data input from the data bus 70 is applied to the bit line BL <m>. The switching element N4 is connected between the sense amplifier S / Am and the data bus 70. When the read switching signal RS1 is activated, the switching device N4 is turned on and the output signal SOUT1 output from the sense amplifier S / Am is output to the data bus 70.

The PCR cell array 40 of this structure allows each phase change resistance element PCR to store one data.

11 is a detailed circuit diagram of the sense amplifier 60 described above.

The sense amplifier 60 includes a pull-down adjustment unit 61, a sensing unit 62, a latch unit 63, and a precharge adjustment unit 64.

Here, the pull-down adjusting unit 61 includes an NMOS transistor N5 connected between the bit line BL and the sensing voltage terminal VSEN to which the bit line pull-down signal BLPD is applied through the gate terminal.

In addition, the sensing unit 62 for sensing the sensing voltage of the bit line BL includes NMOS transistors N6 and N7 connected by cross couples. Here, the NMOS transistor N6 is connected between the bit line BL and the sensing voltage terminal VSEN so that the sensing precharge signal SPRE is applied through the gate terminal. The NMOS transistor N7 is connected between the latch unit 63 and the sensing voltage terminal VSEN so that the gate terminal is connected to the bit line BL.

The latch unit 63 includes inverters IV1 and IV2, and latches the sensing precharge signal SPRE for a predetermined time to output the output signal SOUT. The precharge adjusting unit 64 includes a PMOS transistor P1 that is turned on when the precharge signal PRE is activated to supply a power supply voltage to the latch unit 63.

In the sense amplifier 60 having this structure, the NMOS transistor N5 is turned on during the precharge period to precharge the bit line BL to a low level.

During the active period, the sensing voltage terminal VSEN is fixed at the ground voltage VSS voltage level and the word line WL voltage is increased. In addition, the sensing voltage terminal VSEN may be decreased to a negative voltage VNEG value by the threshold voltage Vtn of the NMOS transistor N5 during the active period. Accordingly, the NMOS transistor N5 of the pull-down adjuster 64 is turned on to determine the operating voltage at the threshold voltage Vtn value.

12 is a timing diagram of an operation of a nonvolatile memory device using a phase change resistance cell in a lead mode according to the present invention.

First, in the t0 period, when the bit line pulldown signal BLPD is activated, the NMOS transistor N5 is turned on. At this time, the voltage level of the sensing voltage terminal VSEN maintains the ground voltage VSS level.

Subsequently, when the selected word line WL transitions high when the t1 section enters, and a constant driving voltage is applied to the word line WL, the PN diode 12 of the series diode switch 10 is turned on. Accordingly, the data of the PCR cell is transferred to the bitline BL. At this time, the precharge signal PRE transitions high to turn off the PMOS transistor P1.

At this time, the bit line pull-down signal BLPD transitions to low. The voltage level of the sensing voltage terminal VSEN is changed from the ground voltage VSS level to the negative voltage VNEG value by the threshold voltage Vtn of the NMOS transistor N5 to apply the sensing voltage to the bit line BL.

Next, upon entering the t2 section, the sensing unit 62 operates to amplify the data carried on the bit line BL, thereby outputting the output signal SOUT.

That is, when cell data is applied to the bit line BL in the period t1, an amplification voltage is applied to the sensing unit 62. When the amplified voltage reaches an arbitrary threshold voltage value, the data of the latch unit 63 is inverted in the period t2 to invert the output signal SOUT.

Then, in the period t3, the word line WL transitions low and the sensing voltage terminal VSEN rises to the ground voltage VSS level. When the read switching signal RS0 transitions high, the NMOS transistors N2 and N4 are turned on and the sensed read data is output to the data bus 70.

13 is a timing diagram of an operation in the write mode of the nonvolatile memory device using the phase change resistance cell according to the present invention.

In the write mode of the present invention, the sense amplifier enable signal SEN is kept low.

First, in the t0 period, the bit line pull-down signal BLPD is activated to turn on the NMOS transistor N5 to precharge the bit line BL to the ground level.

Subsequently, when the write switching signal WS0 transitions high when the t1 period enters, the bit line pull-down signal BLPD transitions low. When the write switching signal WS0 transitions high, the NMOS transistors N1 and N3 are turned on so that new data to be written through the data bus 70 is input to the bit line BL. Here, it is assumed that data applied to the bit line BL in the write mode is "high" or "low".

In this state, the voltage of the word line WL transitions to a negative voltage that is less than or equal to the threshold voltage Vc. That is, the difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL does not reach the state of the threshold voltage Vc for turning on the PNPN diode switch 11 of the series diode switch 10.

However, according to the difference between the high amplification voltage of the bit line BL and the negative voltage of the word line WL, a voltage higher than or equal to the threshold voltage Vc for turning on the PNPN diode switch 11 is applied. As a result, the PNPN diode switch 11 is turned on so that data can be written to the phase change resistance element PCR.

At this time, after the PNPN diode switch 11 is turned on, as shown in the operating characteristic of FIG. 7, even if a small voltage Vs is applied to the phase change resistance device PCR, a large amount of current I can flow. Therefore, the current can flow sufficiently even if the voltage of the word line WL rises from the negative voltage to the low state again after the period t1.

Thereafter, the voltage drop level is different depending on the pattern of data applied to the bit line BL during the period t2 to tn.

That is, when the voltage level is applied to the bit line BL, the voltage level of the bit line BL is gradually decreased during the period t2 to tn. On the other hand, when the voltage level having the value of the data row is applied to the bit line BL, the voltage level of the bit line BL is continuously controlled during the t2 to tn period.

That is, as shown in FIG. 14, in order to keep the melting temperature of the phase change resistance element PCR that maintains the crystallization state at a low temperature at a low temperature when the data loaded on the bit line BL is "high". The level of the voltage applied to the voltage is dropped step by step. Accordingly, in the t1 section, the temperature characteristic of the data "high" gradually decreases after showing the peak value and shows low resistance characteristics.

Here, when the level of the voltage applied to the bit line BL is kept constant without dropping in voltage, the temperature of the phase change resistance element PCR is raised to change the phase change resistance element PCR in the crystallization state into an amorphous state. Accordingly, in the present invention, in order to maintain the crystallization temperature, the voltage level applied to the bit line BL is gradually dropped.

On the other hand, when the data loaded on the bit line BL is " low ", the level of the voltage applied to the bit line BL is kept constant in order to increase the melting temperature of the phase change resistance element PCR that maintains the amorphous state. That is, the higher the melting temperature, the higher the resistance characteristics and the characteristics of the phase change resistance element PCR in the amorphous state is improved. As a result, when a constant voltage is applied to the bit line BL, the temperature is increased to continuously maintain the amorphous state.

In the present invention, since data is stored in a phase change resistance device PCR having a nonvolatile characteristic, an operation process for restoring is unnecessary.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

As described above, the present invention provides the following effects.

First, a bit line is formed on the interlayer insulating film, a series diode switch is stacked on the bit line, and a phase change resistance device is stacked on the series diode switch to improve process efficiency.

Second, a multi-phase phase change resistance cell array is disposed in a multi-layer and a circuit element region in a lower portion of the interlayer insulating layer to reduce the overall size of the nonvolatile memory.

Claims (19)

A series diode switch connected to both ends of a bit line formed on the insulating layer and a bit line contact node, the series diode switch having at least two diode elements connected in series with the bit line contact node; A phase change resistance element having a top electrode and a phase change layer, the crystallization state of which is changed according to a magnitude of a current applied from a word line; And And a unit phase change resistance cell having a contact node connected to the phase change layer and a common node to which the at least two diode elements are connected. The phase change resistance cell of claim 1, wherein the unit phase change resistance cell is provided in plural in the row and column directions, and the plurality of unit phase change resistance cells are stacked in a multilayer structure and separated from each other by the insulating layer. . The phase change resistance cell of claim 1 or 2, wherein the series diode switch is configured by alternately connecting a plurality of PNPN diode switches and a plurality of PN diode switches in series to form a continuous diode chain. The phase change resistance cell of claim 3, wherein the bit line contact node is formed in a P-type region of the plurality of PNPN diode switches and an N-type region of the plurality of PN diode switches, respectively. The phase change resistance cell of claim 3, wherein the contact node is formed at the common node to which an N-type region of the plurality of PNPN diode switches and a P-type region of the plurality of PN diode switches are connected. A plurality of phase change resistance cell arrays arranged in a row and column direction and including a plurality of phase change resistance cells stacked in a multilayered structure and separated from each other by an insulating layer; A plurality of word line drivers selectively driving word lines of the plurality of phase change resistance cell arrays; And A plurality of sense amplifiers for sensing and amplifying data applied from the plurality of phase change resistance cell array, Each of the plurality of phase change resistance cells A bit line formed on the insulating layer; A series diode switch connected to both nodes of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the bit line contact node; A phase change resistance element having a top electrode and a phase change layer, the crystallization state of which is changed according to a magnitude of a current applied from a word line; And And a contact bottom electrode connecting the common node to which the at least two diode elements are connected and the phase change layer. The method of claim 6, A data bus shared by the plurality of sense amplifiers; A main amplifier for amplifying data applied from the data bus; A data buffer for buffering amplified data applied from the main amplifier; And And an input / output port configured to output the output data applied from the data buffer to the outside or to apply the input data applied from the outside to the data buffer. The method of claim 7, wherein each of the plurality of phase change resistance cell array, A plurality of phase change resistance cells positioned in an intersection region between the plurality of word lines and the plurality of bit lines arranged in the row and column directions, respectively; A plurality of light switching elements connected in a one-to-one correspondence between the plurality of bit lines and the data bus and outputting input data of the data bus to the bit lines by a light switching signal; And And a plurality of read switching elements connected in a one-to-one correspondence between the plurality of sense amplifiers and the data bus and outputting read data applied from the plurality of sense amplifiers to the data bus by a read switching signal. Nonvolatile memory device using a phase change resistance cell. The method of claim 8, wherein each of the plurality of sense amplifiers A pull-down adjuster which precharges the bit line to a low level during the precharge period, and supplies a negative voltage having a negative value to the bit line during the active period; A sensing unit for sensing and amplifying a sensing voltage of the bit line; A latch unit which latches an output of the sensing unit for a predetermined time and outputs the read switching element; And And a precharge adjusting unit configured to supply a precharge voltage to the latch unit when the pre-signal signal is activated. 10. The method of claim 9, wherein the pull-down adjuster is connected between the bit line and the sensing voltage terminal is switched in accordance with the bit line pull-down signal, characterized in that it comprises a first switching element having a threshold voltage equal to the negative voltage A nonvolatile memory device using a phase change resistance cell. The method of claim 9, wherein the sensing unit A second switching element controlling the connection of the bit line and the sensing voltage terminal according to an output of the precharge adjusting unit; And And a third switching element cross-coupled with the second switching element to control the connection between the latch unit and the sensing voltage terminal according to the voltage level of the bit line. Volatile memory device. The method of claim 6 or 7, wherein the series diode switch A PN diode switch connected in a forward direction between the contact bottom electrode and the bit line; And And a PNPN diode switch connected in a reverse direction between the contact bottom electrode and the bit line. The nonvolatile memory device of claim 12, wherein the P-type region of the PN diode switch is connected to the contact bottom electrode, and the N-type region is connected to the bit line contact node. The nonvolatile memory device of claim 12, wherein an upper N-type region of the PNPN diode switch is connected to the contact bottom electrode, and a lower P-type region is connected to the bit line contact node. . A plurality of phase change resistance cell arrays including a plurality of unit phase change resistance cells arranged in a row and column direction; A circuit element region formed on a silicon substrate disposed under the plurality of phase change resistor cell arrays to control driving of the plurality of phase change resistor cell arrays; And An insulating layer formed between the plurality of phase change resistance cell arrays and the circuit element region to insulate the plurality of phase change resistance cell arrays and the circuit element region from each other, Each of the plurality of unit phase change resistance cells A bit line formed on the insulating layer; A series diode switch connected to both nodes of the bit line through a bit line contact node, the series diode switch having at least two diode elements connected in series with the bit line contact node; A phase change resistance element having a top electrode and a phase change layer, the crystallization state of which is changed according to a magnitude of a current applied from a word line; And And a contact bottom electrode connecting the common node to which the at least two diode elements are connected and the phase change layer. The method of claim 15, wherein the series diode switch A PN diode switch connected in a forward direction between the contact bottom electrode and the bit line; And And a PNPN diode switch connected in a reverse direction between the contact bottom electrode and the bit line. 17. The nonvolatile memory device of claim 16, wherein the P-type region of the PN diode switch is connected to the contact bottom electrode and the N-type region is connected to the bit line contact node. The nonvolatile memory device of claim 16, wherein an upper N-type region of the PNPN diode switch is connected to the contact bottom electrode, and a lower P-type region is connected to the bit line contact node. . 16. The circuit device of claim 15, wherein the circuit element region is A plurality of word line drivers selectively driving word lines of the plurality of series diode cell arrays; A plurality of sense amplifiers for sensing and amplifying data applied from the plurality of series diode cell arrays; A data bus shared by the plurality of sense amplifiers; A main amplifier for amplifying data applied from the data bus; A data buffer for buffering amplified data applied from the main amplifier; And And an input / output port configured to output the output data applied from the data buffer to the outside or to apply input data applied from the outside to the data buffer.

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